Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 67
Integrated Interface Block for PCI Express Designs Switching Characteristics (XC7Z012S and
XC7Z015 Only)
This block is only available in the XC7Z012S and XC7Z015. More information and documentation on solutions for PCI Express
designs can be found at: www.xilinx.com/technology/protocols/pciexpress.htm
.
Table 98: CPRI Protocol Characteristics
Description Line Rate (Mb/s) Min Max Units
CPRI Transmitter Jitter Generation
Total transmitter jitter
614.4 – 0.35 UI
1228.8 – 0.35 UI
2457.6 – 0.35 UI
3072.0 – 0.35 UI
4915.2 – 0.3 UI
6144.0 – 0.3 UI
CPRI Receiver Frequency Jitter Tolerance
Total receiver jitter tolerance
614.4 0.65 – UI
1228.8 0.65 – UI
2457.6 0.65 – UI
3072.0 0.65 – UI
4915.2
(1)
0.60 – UI
6144.0
(1)
0.60 – UI
Notes:
1. Tested to CEI-6G-SR.
Table 99: Maximum Performance for PCI Express Designs (XC7Z012S and XC7Z015 only)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
F
PIPECLK
Pipe clock maximum frequency 250.00 250.00 250.00 N/A MHz
F
USERCLK
User clock maximum frequency 250.00 250.00 250.00 N/A MHz
F
USERCLK2
User clock 2 maximum frequency 250.00 250.00 250.00 N/A MHz
F
DRPCLK
DRP clock maximum frequency 250.00 250.00 250.00 N/A MHz
Notes:
1. Refer to the 7 Series FPGAs Integrated Block for PCI Express Product Guide (PG054) for specific supported core configurations.