Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 69
Configuration Switching Characteristics
XADC Reference
(5)
External Reference V
REFP
Externally supplied reference voltage 1.20 1.25 1.30 V
On-Chip Reference Ground V
REFP
pin to AGND,
–40°C ≤ T
j
≤ 100°C
1.2375 1.25 1.2625 V
Ground V
REFP
pin to AGND,
–55°C ≤ T
j
< –40°C; 100°C < T
j
≤ 125°C
1.225 1.25 1.275 V
Notes:
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
2. Only specified for bitstream option XADCEnhancedLinearity = ON.
3. See the ADC chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter
User Guide (UG480
) for a detailed description.
4. See the Timing chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480
) for a detailed description.
5. Any variation in the reference voltage from the nominal V
REFP
= 1.25V and V
REFN
= 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted.
Table 101: Configuration Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Power-up Timing Characteristics
T
PL
(1)
Program latency 5.00 5.00 5.00 5.00 ms, Max
T
POR
Power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50
ms,
Min/Max
Power-on reset (1 ms ramp rate time) with the
power-on reset override function disabled;
(devcfg.CTRL.PCFG_POR_CNT_4K = 0).
(2)
10/35 10/35 10/35 10/35
ms,
Min/Max
Power-on reset (1 ms ramp rate time) with the
power-on reset override function enabled;
(devcfg.CTRL.PCFG_POR_CNT_4K = 1).
(2)
2/8 2/8 2/8 2/8
ms,
Min/Max
T
PROGRAM
Program pulse width 250.00 250.00 250.00 250.00 ns, Min
Boundary-Scan Port Timing Specifications
T
TAPTCK
/T
TCKTAP
TMS and TDI setup/hold 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 ns, Min
T
TCKTDO
TCK falling edge to TDO output 7.00 7.00 7.00 7.00 ns, Max
F
TCK
TCK frequency 66.00 66.00 66.00 66.00 MHz, Max
Internal Configuration Access Port
F
ICAPCK
Internal configuration access port (ICAPE2) 100.00 100.00 100.00 100.00 MHz, Max
Device DNA Access Port
F
DNACK
DNA access port (DNA_PORT) 100.00 100.00 100.00 100.00 MHz, Max
Notes:
1. To support longer delays in configuration, use the design solutions described in the 7 Series FPGA Configuration User Guide (UG470).
2. For non-secure boot only. Measurement is made when the PS is already powered and stable, before power cycling the PL.
Table 100: XADC Specifications (Cont’d)
Parameter Symbol Comments/Conditions Min Typ Max Units