Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 71
02/14/2013 1.4 Corrected T
QSPICKD2
minimum equation in Table 34. Updated timing parameter names in Figure 4 and
Figure 5 to match those in the accompanying table.
02/19/2013 1.4.1 Corrected version history.
03/19/2013 1.5 Updated Table 15 and Table 16 to the product status of production for the XC7Z010 devices with -2 and
-1 speed specifications.
Updated Figure 4 by adding OUT0. Added Note 2 to Table 33. Added Table 38 and Figure 9.
04/24/2013 1.6 All the devices listed in this data sheet are production released. Updated the AC Switching
Characteristics based upon ISE tools 14.5 and Vivado tools 2013.1, both at v1.06 for the -3, -2, and -1
speed specifications throughout the document. Updated Table 15 and Table 16 for production release
of the XC7Z010 and XC7Z020 in the -3 speed designations.
Removed the PS Power-on Reset section. Updated the PS—PL Power Sequencing section.
In Table 1, revised V
IN
(I/O input voltage) to match values in Table 4, and combined Note 4 with old
Note 5 and then added new Note 6. Revised V
IN
description and added Note 8 in Table 2. Updated first
3 rows in Table 4. Revised PCI33_3 voltage minimum in Table 10 to match values in Table 1 and
Table 4. Added Note 1 to Table 13. Clarified the load conditions in Table 34 by adding new data.
Clarified title of Table 51. Throughout the data sheet (Table 62, Table 63, Table 64, and Table 79)
removed the obvious note “A Zero “0” Hold Time listing indicates no hold time or a negative hold time.”
07/08/2013 1.7 Added Note 5 to Table 2. Revised the frequency of CPU clock performance (6:2:1) in Table 17.
Updated F
DDR3L_MAX
values in Table 18. Moved and added F
AXI_MAX
to Table 19. Updated the
minimum T
DQVALID
values in Table 25 and Table 26. In Table 37, corrected the F
SDSCLK
maximum
value. In Table 38, corrected F
SDSCLK
and fixed the F
SDIDCLK
typographical unit error. Values in
Table 78 and Table 82 were reported incorrectly and have been updated to match speed specifications.
09/12/2013 1.8 Added the XC7Z015 throughout the document. The XC7Z015 is the only device in this data sheet that
includes GTP transceivers. Added the GTP transceivers specifications to Table 1, Table 2, and Table 7,
and the PL Power-On/Off Power Supply Sequencing, PS—PL Power Sequencing, GTP Transceiver
Specifications (Only available in the XC7Z012S and XC7Z015), Integrated Interface Block for PCI
Express Designs Switching Characteristics (XC7Z012S and XC7Z015 Only) and sections. Added
USRCCLK Output section and clarified values for T
POR
in Table 101. Added I
PSFS
to Table 102.
Updated Notice of Disclaimer.
11/26/2013 1.9 Added specifications for the XQ7Z020 with the -1Q speed specification/temperature range. Added
specifications for the XA7Z010 and XA7Z020 with the -1Q speed specification/temperature range.
Removed Note 1 and Note 2 from Table 6. Added Table 14. Updated Table 100 specifications. In
Table 101, removed the USRCCLK Output section, added T
PL
, T
PROGRAM
, Note 1, and the Device
DNA Access Port section, and updated the T
POR
description.
01/20/2014 1.10 Update Note 7 in Table 2. Added Note 2 to Table 4. Updated speed files in data sheet and Table 14.
Updated Table 15 and Table 16 for production release of the XA7Z010 and XA7Z020 in the -1I and -1Q
speed designations. Added I/O standards to Table 52 and improved all of the T
IOTP
speed
specifications.
02/25/2014 1.11 Production release of the XC7Z015 for all speed specifications and temperature ranges, including
finalizing information in Table 15 and Table 16. Added XC7Z015 data to Table 5, Table 6, and Table 71.
Added Table 27.
07/14/2014 1.12 In Table 4, updated Note 2 per the customer notice 7 Series FPGA and Zynq-7000 AP SoC I/O
Undershoot Voltage Data Sheet Update (XCN14014). Added heading LVDS DC Specifications
(LVDS_25). Fixed units for T
DQSS
in Table 27. Updated heading Input/Output Delay Switching
Characteristics. Updated F
IDELAYCTRL_REF
, T
IDELAYPAT_JIT
and T
ODELAYPAT_JIT
, and Note 1 in Table 60.
Removed note from Table 62. Updated description of T
ICKOF
and added Note 2 to Table 74. Updated
description of T
ICKOFFAR
and added Note 2 to Table 75. Revised DV
PPOUT
and V
IN
, and added Note 2
to Table 85. Revised labels in Figure 20 and Figure 21 and added a note after Figure 21. Added Note 1
to Table 99.
10/09/2014 1.13 Added -1LI speed grade throughout. Updated Introduction. Removed 3.3V as descriptor of HR I/O
banks throughout. In PL Power-On/Off Power Supply Sequencing, added sentence about there being
no recommended sequence for supplies not shown. In PS—PL Power Sequencing, removed list of PL
power supplies. In Table 20, removed typical value and added maximum value for T
RFPSCLK
. Added
note about measurement being taken from V
REF
to V
REF
in Table 25 to Table 32. Added I/O Standard
Adjustment Measurement Methodology.
Date Version Description of Revisions