Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 8
PS Power-On/Off Power Supply Sequencing
The recommended power-on sequence is V
CCPINT
, then V
CCPAUX
and V
CCPLL
together, then the PS V
CCO
supplies (V
CCO_MIO0
,
V
CCO_MIO1
, and V
CCO_DDR
) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The
PS_POR_B input is required to be asserted to GND during the power-on sequence until V
CCPINT
, V
CCPAUX
and V
CCO_MIO0
have
reached minimum operating levels to ensure PS eFUSE integrity. For additional information about PS_POR_B timing
requirements refer to Resets.
The recommended power-off sequence is the reverse of the power-on sequence. If V
CCPAUX
, V
CCPLL
, and the PS V
CCO
supplies
(V
CCO_MIO0
, V
CCO_MIO1
, and V
CCO_DDR
) have the same recommended voltage levels, then they can be powered by the same
supply and ramped simultaneously. Xilinx recommends powering V
CCPLL
with the same supply as V
CCPAUX
, with an optional
ferrite bead filter. Before V
CCPINT
reaches 0.80V at least one of the four following conditions is required during the power-off
stage: the PS_POR_B input is asserted to GND, the reference clock to the PS_CLK input is disabled, V
CCPAUX
is lower than
0.70V, or V
CCO_MIO0
is lower than 0.90V. The condition must be held until V
CCPINT
reaches 0.40V to ensure PS eFUSE integrity.
For V
CCO_MIO0
and V
CCO_MIO1
voltages of 3.3V:
• The voltage difference between V
CCO_MIO0
/V
CCO_MIO1
and V
CCPAUX
must not exceed 2.625V for longer than
T
VCCO2VCCAUX
for each power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX
time can be allocated in any percentage between the power-on and power-off ramps.
PL Power-On/Off Power Supply Sequencing
The recommended power-on sequence for the PL is V
CCINT
, V
CCBRAM
, V
CCAUX
, and V
CCO
to achieve minimum current draw
and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If V
CCINT
and V
CCBRAM
have the same recommended voltage levels then both can be powered by the same supply
and ramped simultaneously. If V
CCAUX
and V
CCO
have the same recommended voltage levels then both can be powered by
the same supply and ramped simultaneously.
For V
CCO
voltages of 3.3V in HR I/O banks and configuration bank 0:
• The voltage difference between V
CCO
and V
CCAUX
must not exceed 2.625V for longer than T
VCCO2VCCAUX
for each
power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX
time can be allocated in any percentage between the power-on and power-off ramps.
GTP Transceivers (XC7Z015 Only)
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers (XC7Z015 only) is V
CCINT
,
V
MGTAVCC
, V
MGTAVTT
OR V
MGTAVCC
, V
CCINT
, V
MGTAVTT
. Both V
MGTAVCC
and V
CCINT
can be ramped simultaneously. The
recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from V
MGTAVTT
can be higher than specifications during
power-up and power-down.
•When V
MGTAVTT
is powered before V
MGTAVCC
and V
MGTAVTT
–V
MGTAVCC
> 150 mV and V
MGTAVCC
<0.7V, the V
MGTAVTT
current draw can increase by 460 mA per transceiver during V
MGTAVCC
ramp up. The duration of the current draw can be
up to 0.3 x T
MGTAVCC
(ramp time from GND to 90% of V
MGTAVCC
). The reverse is true for power-down.
•When V
MGTAVTT
is powered before V
CCINT
and V
MGTAVTT
–V
CCINT
> 150 mV and V
CCINT
<0.7V, the V
MGTAVTT
current
draw can increase by 50 mA per transceiver during V
CCINT
ramp up. The duration of the current draw can be up to
0.3 x T
VCCINT
(ramp time from GND to 90% of V
CCINT
). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
PS—PL Power Sequencing
The PS and PL power supplies are fully independent. PS power supplies (V
CCPINT
, V
CCPAUX
, V
CCPLL
, V
CCO_DDR
, V
CCO_MIO0
, and
V
CCO_MIO1
) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent
damage.