Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 9
Power Supply Requirements
Table 6 shows the minimum current, in addition to I
CCQ
, that is required by Zynq-7000 devices for proper power-on and
configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four PL supplies
have passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after
V
CCINT
is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at
www.xilinx.com/power
) to estimate current drain on these supplies.
Table 6: Power-On Current for Zynq-7000 Devices
Device I
CCPINTMIN
I
CCPAUXMIN
I
CCDDRMIN
I
CCINTMIN
I
CCAUXMIN
I
CCOMIN
I
CCBRAMMIN
Units
XC7Z007S I
CCPINTQ
+70 I
CCPAUXQ
+40
I
CCDDRQ
+100mA
per bank
I
CCINTQ
+40 I
CCAUXQ
+60
I
CCOQ
+90mA
per bank
I
CCBRAMQ
+40 mA
XC7Z012S I
CCPINTQ
+70 I
CCPAUXQ
+40
I
CCDDRQ
+100mA
per bank
I
CCINTQ
+130 I
CCAUXQ
+60
I
CCOQ
+90mA
per bank
I
CCBRAMQ
+40 mA
XC7Z014S I
CCPINTQ
+70 I
CCPAUXQ
+40
I
CCDDRQ
+100mA
per bank
I
CCINTQ
+70 I
CCAUXQ
+60
I
CCOQ
+90mA
per bank
I
CCBRAMQ
+40 mA
XC7Z010
XA7Z010
I
CCPINTQ
+70 I
CCPAUXQ
+40
I
CCDDRQ
+100mA
per bank
I
CCINTQ
+40 I
CCAUXQ
+60
I
CCOQ
+90mA
per bank
I
CCBRAMQ
+40 mA
XC7Z015 I
CCPINTQ
+70 I
CCPAUXQ
+40
I
CCDDRQ
+100mA
per bank
I
CCINTQ
+130 I
CCAUXQ
+60
I
CCOQ
+90mA
per bank
I
CCBRAMQ
+40 mA
XC7Z020
XA7Z020
XQ7Z020
I
CCPINTQ
+70 I
CCPAUXQ
+40
I
CCDDRQ
+100mA
per bank
I
CCINTQ
+70 I
CCAUXQ
+60
I
CCOQ
+90mA
per bank
I
CCBRAMQ
+40 mA
Table 7: Power Supply Ramp Time
Symbol Description Conditions Min Max Units
T
VCCPINT
Ramp time from GND to 90% of V
CCPINT
0.2 50 ms
T
VCCPAUX
Ramp time from GND to 90% of V
CCPAUX
0.2 50 ms
T
VCCO_DDR
Ramp time from GND to 90% of V
CCO_DDR
0.2 50 ms
T
VCCO_MIO
Ramp time from GND to 90% of V
CCO_MIO
0.2 50 ms
T
VCCINT
Ramp time from GND to 90% of V
CCINT
0.2 50 ms
T
VCCO
Ramp time from GND to 90% of V
CCO
0.2 50 ms
T
VCCAUX
Ramp time from GND to 90% of V
CCAUX
0.2 50 ms
T
VCCBRAM
Ramp time from GND to 90% of V
CCBRAM
0.2 50 ms
T
VCCO2VCCAUX
Allowed time per power cycle for V
CCO
–V
CCAUX
> 2.625V
and V
CCO_MIO
–V
CCPAUX
> 2.625V
T
j
= 125°C
(1)
–300
msT
j
= 100°C
(1)
–500
T
j
= 85°C
(1)
–800
T
MGTAVCC
Ramp time from GND to 90% of V
MGTAVCC
0.2 50 ms
T
MGTAVTT
Ramp time from GND to 90% of V
MGTAVTT
0.2 50 ms
Notes:
1. Based on 240,000 power cycles with nominal V
CCO
of 3.3V or 36,500 power cycles with worst case V
CCO
of 3.465V.