Zynq-7000 All Programmable SoC Technical Reference Manual UG585 (v1.
Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products.
Date Version Revision 08/08/2012 1.2 (Cont’d) Reorganized, clarified, and expanded Chapter 19 to include programming models (added sections 19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated Table 22-2 and Table 22-3 in Chapter 22. Added section CPU Clock Divisor Restriction in Chapter 25. Updated Table 26-4 in Chapter 26. Clarified section 27.3 I/O Signals in Chapter 27. Added section 28.1.2 Notices in Chapter 28.
Date Version Revision 03/07/2013 1.5 Added 7z100 device and made minor clarifications to Chapter 1, Introduction. Made minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application Processing Unit, Chapter 4, System Addresses, and Chapter 5, Interconnect. Clarified section 6.1 Introduction and other sections, and added PS Independent JTAG Non-Secure Boot section in Chapter 6, Boot and Configuration.
Date Version Revision 06/28/2013 1.6 (Cont’d) Added section 31.5 Root Complex Use Case. Added FIPS standards and clarified section 32.1.2 Features, updated configuration file and secure boot process steps in Figure 32-1, added boot time penalty to Power on Reset section, changed “Secure Boot” heading to ”Secure FSBL Decryption”, changed “ROM code” to “OCM ROM Memory” in Figure 32-2 and “ROM” to “OCM ROM” in Table 32-3, updated sections 32.2.7 Boot Image and Bitstream Decryption and Authentication, 32.
Table of Contents Chapter 1: Introduction 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.1.2 Documentation Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3: Application Processing Unit 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1.1 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.1.2 System-Level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 PS I/O Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.7 Miscellaneous PS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Chapter 5: Interconnect 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.
6.1.7 PL Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.1.8 PL Configuration Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.1.9 Device Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 6.1.10 Starting Code on CPU 1 . . . . .
7.2.5 Wait for Interrupt Event Signal (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 7.3 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.3.1 Write Protection Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 7.4 Programming Model. . . . . . . . . . . . . . . . . .
9.2.5 Memory-to-Memory Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 9.2.6 PL Peripheral AXI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 9.2.7 PL Peripheral Request Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 9.2.8 PL Peripheral - Length Managed by PL Peripheral . . . .
10.4.4 Stage 1 – AXI Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 10.4.5 Stage 2 – Read Versus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 10.4.6 High Priority Read Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 10.4.7 Stage 3 – Transaction State . . . . . . . .
11.3 11.4 11.5 11.6 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 Data Transfer Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 Data Transfers Without DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 Using DMA . . . . . . . . . . .
.2.2 15.2.3 15.2.4 15.2.5 15.2.6 DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.11.8 Port Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449 15.12 Host Data Structures Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 15.12.1 15.12.2 15.12.3 15.12.4 15.12.5 15.12.6 15.12.7 15.12.8 Descriptor Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.6 Configure Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513 16.3.7 Enable the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513 16.3.8 Transmitting Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514 16.3.9 Receiving Frames . . . . . . .
17.5.3 MIO/EMIO Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551 17.5.4 Wiring Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .552 17.5.5 MIO/EMIO Signal Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555 Chapter 18: CAN Controller 18.
.2.11 Modem Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .594 19.3 Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.2 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623 21.2.3 Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .624 21.2.4 Digital Signal Processing — DSP Slice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626 21.3 Input/Output . . . . . . . . . . . .
Chapter 24: Power Management 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 24.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .670 24.2 System Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 24.2.1 24.2.2 24.2.3 24.2.4 24.
Chapter 26: Reset System 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 26.1.1 26.1.2 26.1.3 26.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 28.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .728 28.4.2 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .729 28.5 Programming Model. . . . . . . . . . .
30.7 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 30.7.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .759 30.7.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .760 Chapter 31: PCI Express 31.
Appendix B: Register Details B.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 B.2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 B.3 Module Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 B.4 AXI_HP Interface (AFI) (axi_hp) . .
Chapter 1 Introduction 1.1 Overview The Zynq®-7000 family is based on the Xilinx® All Programmable SoC (AP SoC) architecture. These products integrate a feature-rich dual or single-core ARM® Cortex™-A9 MPCore™ based processing system (PS) and Xilinx programmable logic (PL) in a single device, built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, and high-k metal gate (HKMG) process technology.
Chapter 1: Introduction The processor(s) in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL.
Chapter 1: Introduction The Zynq-7000 AP SoC is composed of the following major functional blocks: • • Processing System (PS) ° Application processor unit (APU) ° Memory interfaces ° I/O peripherals (IOP) ° Interconnect Programmable Logic (PL) 1.1.2 Documentation Resources Table 1-1 identifies the versions of third-party IP used in the Zynq-7000 AP SoC devices.
Chapter 1: Introduction To learn more about the PL resources, refer to the following Xilinx 7 series FPGA User Guides: • UG471, 7 Series FPGAs SelectIO Resources User Guide • UG472, 7 Series FPGAs Clocking Resources User Guide • UG473, 7 Series FPGAs Memory Resources User Guide • UG474, 7 Series FPGAs Configurable Logic Block User Guide • UG476, 7 Series FPGAs GTX Transceiver User Guide • UG482, 7 Series FPGAs GTP Transceiver User Guide • UG477 7 Series FPGAs Integrated Block v1.
Chapter 1: Introduction 1.1.3 Notices Zynq-7000 AP SoC Device Family The PS structure for all Zynq-7000 AP SoC devices is the same except for the following: 7z007s and 7z010 CLG225 Devices The 7z007s single core and 7z010 dual core CLG225 devices have a limited number of pins (225). This reduces the capability of the MIO, DDR and XADC subsystems. • 32 MIO pins, see section 2.5.3 MIO Pin Assignment Considerations • 16 DDR data, see section 10.1.
Chapter 1: Introduction 1.2 Processing System (PS) Features and Descriptions 1.2.1 Application Processor Unit (APU) The application processor unit (APU) provides an extensive offering of high-performance features and standards-compliant capabilities.
Chapter 1: Introduction • General interrupt controller (GIC) ° Individual interrupt masks and interrupt prioritization ° Five CPU-private peripheral interrupts (PPI) ° Sixteen CPU-private software generated interrupts (SGI) ° Distributes shared peripheral interrupts (SPI) from the rest of the system, PS and PL - • 20 from the PL ° Wait for interrupt (WFI) and wait for event (WFE) signals from CPU sent to PL ° Enhanced security features to support TrustZone™ technology Watchdog timer, triple
Chapter 1: Introduction Quad-SPI Controller Key features of the linear Quad-SPI controller (which can be a primary boot device) are: • Single or dual • 1x and 2x read support • 32-bit APB 3.
Chapter 1: Introduction ° • Asynchronous memory operating mode Parallel SRAM/NOR controller ° 8-bit data bus width ° One chip select with up to 26 address signals (64 MB) ° Two chip selects with up to 25 address signals (32 MB + 32 MB) ° 16-word read and 16-word write data FIFOs ° 8-word command FIFO ° Programmable I/O cycle timing on a per chip select basis ° Asynchronous memory operating mode 1.2.
Chapter 1: Introduction • MIO pins only (one USB controller is available in the 7x010 device) • Built-in DMA • USB 2.0 high speed device • USB 2.0 high speed host controller • The USB host controller registers and data structures are EHCI compatible • Direct support for USB transceiver low pin interface (ULPI).
Chapter 1: Introduction • ° Drives into 3-state if not enabled ° Identifies an error condition if more than one master detected Supports 50 MHz maximum external SPI clock rate through MIO ° 25 MHz maximum through EMIO to PL SelectIO pins • Selectable master clock reference • Programmable master baud rate divisor • Supports 128-byte read and 128-byte write FIFOs ° Each FIFO is 8-bit wide • Programmable FIFO thresholds • Supports programmable clock phase and polarity • Supports manual or a
Chapter 1: Introduction • Odd, even, space, mark, or no parity • Parity, framing and overrun error detection • Line-break generation and detection • Automatic echo, local loopback, and remote loopback channel modes • Interrupts generation • Rx and Tx signals are on the MIO and EMIO interfaces • Modem control signals: CTS, RTS, DSR, DTR, RI, and DCD are available on the EMIO interface I2C Controllers (two) • Supports 16-byte FIFO • I2C bus specification version 2 • Programmable normal and
Chapter 1: Introduction ° 1.8 and 2.5/3.3 volts ° CMOS single ended or HSTL differential receiver mode 1.3 Programmable Logic Features and Descriptions The PL provides a rich architecture of user-configurable capabilities.
Chapter 1: Introduction • • ° High-performance transceivers capable of up to 6.
Chapter 1: Introduction 1.4.2 PS-PL Interfaces The PS-PL interface contains all the signals available to the PL designer for integrating the PL-based functions and the PS. There are two types of interfaces between the PL and the PS. 1. Functional interfaces which include AXI interconnect, extended MIO interfaces (EMIO) for most of the I/O peripherals, interrupts, DMA flow control, clocks, and debug interfaces. These signals are available for connecting with user-designed IP blocks in the PL. 2.
Chapter 1: Introduction 1.5 System Software Xilinx provides device drivers for all of the I/O peripherals. These device drivers are provided in source format and support bare-metal or stand-alone and Linux. An example first-stage boot loader (FSBL) is also provided in source code format. The source drivers for stand-alone and FSBL are provided as part of the Xilinx IDE Design Suite Embedded Edition. The Linux drivers are provided through the Xilinx Open Source Wiki at wiki.xilinx.
Chapter 2 Signals, Interfaces, and Pins 2.1 Introduction This chapter identifies the user visible signals and interfaces in Zynq-7000 AP SoC devices. The interfaces and signals are organized into major groups as shown in Figure 2-1. The Zynq-7000 AP SoC devices consist of a Processing System (PS) with a Xilinx Artix™-7 or Kintex™-7 based Programmable Logic (PL) block. 2.1.
Chapter 2: Signals, Interfaces, and Pins X-Ref Target - Figure 2-1 Zynq 7000 Device Boundary Processing System (PS) AXI Interfaces Programmable Logic (PL) M_AXI_GP x2 S_AXI_GP x2 S_AXI_HP x4 S_AXI_ACP x1 PS Signals and Interfaces Misc.
Chapter 2: Signals, Interfaces, and Pins 2.2 Power Pins The PS and PL power supplies are fully independent, however the PS power supply must be present whenever the PL power supply is active. PL power up needs to maintain a certain timing relationship with the POR reset signal of the PS. For more details refer to section 6.3.3 BootROM Performance: PS_POR_B De-assertion Guidelines, page 177. The PS includes an independent power supply for the DDR I/O and two independent voltage banks for MIO.
Chapter 2: Signals, Interfaces, and Pins 2.3 PS I/O Pins A summary of the dedicated PS signal pins is shown in Table 2-2. CAUTION! For MIO pins, the allowable Vin High level voltage depends on the settings of the slcr.MIO_PIN_xx [IO_Type] and [DisableRcvr] bits. These restrictions and the restrictions for all I/O pins are defined in the Zynq-7000 AP SoC data sheets. Damage to the input buffer can occur when the limits are exceeded.
Chapter 2: Signals, Interfaces, and Pins 2.4 PS–PL Voltage Level Shifter Enables All of the signals and interfaces that go between the PS and PL traverse a voltage boundary. These input and output signals are routed through voltage level shifters. The majority of the voltage level shifters are enabled by the slcr.LVL_SHFTR_EN register. The voltage level shifter enables for some PS-PL traversing signals are controlled with the PL power state.
Chapter 2: Signals, Interfaces, and Pins 2.5 PS-PL MIO-EMIO Signals and Interfaces The MIO is fundamental to the I/O peripheral connections due to the limited number of MIO pins. Software programs the routing of the I/O signals to the MIO pins. The I/O peripheral signals can also be routed to the PL (including PL device pins) through the EMIO interface. This is useful to gain access to more device pins (PL pins) and to allow an I/O peripheral controller to interface to user logic in the PL.
Chapter 2: Table 2-3: Signals, Interfaces, and Pins I/O Peripheral MIO-EMIO Interface Routing Peripheral MIO Routing EMIO Routing Cross Reference TTC [0,1] Clock In, Wave Out. Clock In, Wave Out. One pair of signals from Three pairs of signals each counter. from each counter.
Chapter 2: Signals, Interfaces, and Pins On the interconnect side, the USB, Ethernet and SDIO peripherals are connected to the central interconnect to service the six DMA masters. Software accesses the slave-only Quad-SPI and SMC peripherals via the AHB interconnect. The GPIO, SPI, CAN, UART, and I2C save-only controllers are accessed via the APB bus. All control and status registers are also accessed via the APB interconnect except for the SDIO controllers which each have two AHB interfaces.
Chapter 2: Signals, Interfaces, and Pins 2.5.3 MIO Pin Assignment Considerations Normally, each pin is assigned to one function. One exception to this is the dual use boot mode strapping resistors (MIO [2:8]). IMPORTANT: There are several important MIO pin assignment considerations. The MIO-at-a-Glance table, the interface routing table, and these pin assignment considerations are helpful when doing pin planning.
Chapter 2: Signals, Interfaces, and Pins Quad-SPI Interface: The lower memory Quad-SPI interface (QSPI_0) must be used if the Quad-SPI memory subsystem is to be used. The upper interface (QSPI_1) is optional and is only used for a two-memory arrangement (parallel or stacked). Do not use the Quad-SPI 1 interface alone. MIO Pins [8:7] are Outputs: These MIO pins are available as output only. GPIO channels 7 and 8 can only be configured as outputs.
Chapter 2: Signals, Interfaces, and Pins 2.5.4 MIO-at-a-Glance Table Table 2-4 presents MIO information in a compact format for easy reference; the gray boxes represent signals that are not usable in devices with CLG225 packages (7z010 dual core and 7z007s single core devices). Refer to section PS-PL MIO-EMIO Signals and Interfaces for background information. This section also includes important pin assignment considerations.
Chapter 2: Signals, Interfaces, and Pins 2.5.5 MIO Signal Routing Signal routing through the MIO is controlled by the MIO_PIN_[53:0] configuration registers located in the slcr registers set. The MIO multiplexes and de-multiplexes the various input and output signals to the MIO pins using four stages of multiplexing, as shown in Figure 2-4. The high-speed data signals (such as RGMII for Gigabit Ethernet and ULPI for USB) are routed through only one multiplexer stage.
Chapter 2: Signals, Interfaces, and Pins The default input signal logic levels are designed to be benign to the I/O peripheral. As a precaution, the related peripheral core should also be disabled when not in use. The logic levels are shown in the signal tables in each chapter for each I/O peripheral. X-Ref Target - Figure 2-5 Programmable Logic EMIO Input Voltage translation and drives a default value to the MIO mux.
Chapter 2: Signals, Interfaces, and Pins VREF Source Considerations The VREF pins for HSTL signaling can be from an internal or external source. The user should choose based system design needs. The reference source is selected using the slcr.GPIOB_CTRL [VREF_SW_EN] register bit. 2.6 PS–PL AXI Interfaces The PS side of the AXI interfaces are based on the AXI 3 interface specification. Each interface consists of multiple AXI channels. The interfaces are summarized in Table 2-6.
Chapter 2: Table 2-7: Signals, Interfaces, and Pins PS-PL Signal Groups PS-PL Signal Group Signal Name Reference PL clocks and resets FCLKx 2.7.1 Clocks and Resets PL interrupts to PS IRQF2Px 2.7.2 Interrupt Signals IOP interrupts to PL IRQP2Fx 2.7.2 Interrupt Signals Events EVENTx 2.7.3 Event Signals IdleAXI, DDR ARB, SRAM interrupt, FPGA FPGA, DDR, EMIO 2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals DMA controller DMACx 2.7.
Chapter 2: Signals, Interfaces, and Pins 2.7.2 Interrupt Signals The interrupts from the processing system I/O peripherals (IOP) are routed to the PL and assert asynchronously to the FCLK clocks. In the other direction, the PL can asynchronously assert up to 20 interrupts to the PS. Sixteen of these interrupt signals are mapped to the interrupt controller as a peripheral interrupt where each interrupt signal is set to a priority level and mapped to one or both of the CPUs.
Chapter 2: Table 2-11: Signals, Interfaces, and Pins PL AXI Idle, DDR Urgent/Arb and SRAM Interrupt Signals Type PL Signal Name I/O Destination Reference Idle PL AXI Interfaces FPGAIDLEN I Central interconnect clock disable logic Central Interconnect Clock Disable in section 25.1.4 Power Management DDR Urgent Signal DDRARB[3:0] I DDR memory controller Chapter 10, DDR Memory Controller SRAM EMIOSRAMINTIN I Static memory controller interrupt Chapter 11, Static Memory Controller 2.7.
Chapter 2: Signals, Interfaces, and Pins CAUTION! The allowable Vin High level voltages are defined in the Zynq-7000 AP SoC data sheets. Damage to the input buffer can occur when the limits are exceeded. Table 2-13: PL Pin Summary Group User I/O Pins Multi-Gigabit Serial Transceivers Name IO_LXXY_#, IO_XX_# Type Description I/O Most user I/O pins are capable of differential signaling and can be implemented as pairs. The top and bottom I/O pins are always single ended.
Chapter 3 Application Processing Unit 3.1 Introduction 3.1.1 Basic Functionality The application processing unit (APU), located within the PS, contains one processor for single-core devices or two processors for dual-core devices. These are ARM® Cortex™-A9 processors with NEON co-processors connected in an MP configuration sharing a 512 KB L2 cache. Each processor is a high-performance and low-power core that implements two separate 32 KB L1 caches for instruction and data.
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-1 APU Accelerator Coherency Port (ACP) CPUs Snoopable Data buffers and caches PL Fabric Read/Write Requests M L1 Cache Line Updates Cache Coherent Transactions S S SCU Maintain L1 Cache Coherency M0 Cacheable and Noncacheable Accesses Flush Cache Line to Memory M1 Tag RAM Cache Tag RAM Update Cacheable and Noncacheable Accesses to DDR, PL, Peripherals, and PS registers System Interconnect S OCM Tag RAM L2 Cache Data RAM M
Chapter 3: Application Processing Unit 3.1.2 System-Level View The APU is the most critical component of the system that comprises the PS, the IP cores implemented in the PL, and board-level devices such as the external memories and the peripherals. The main interfaces through which the APU communicates to the rest of the system are two interfaces through the L2 controller and an interface to the OCM that is parallel to the L2 cache. See Figure 3-1.
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-2 High Performance AXI Controllers (AXI_HP) Cache Coherent ACP Port PL Clocks M1 M0 32-/ 64-bit 32-/ 64-bit PL Fabric S0 M2 32-/ 64-bit M3 32-/ 64-bit ASYNC ASYNC M M0 Application Processing Unit ASYNC ASYNC FIFO FIFO ASYNC ASYNC ASYNC DAP ASYNC NEON MMU L1 I/D Caches 4 Instruction Data Snoop FIFO S1 M1 DevC Cortex-A9 ASYNC FIFO General Purpose AXI Slaves General Purpose AXI Masters 8 8 1 Slave Interconnect f
Chapter 3: Application Processing Unit 3.2 Cortex-A9 Processors 3.2.1 Summary The APU implements a dual/single-core Cortex-A9 MP configuration. Each processor has its own SIMD media processing engine (NEON), memory management unit (MMU), and separate 32 KB level-one (L1) instruction and data caches. Each Cortex-A9 processor provides two 64-bit AXI master interfaces for independent instruction and data transactions to the SCU.
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-3 Cortex A9 Processor Coresight Debug Coresight Trace CoreSight Debug Access Port 3 + 1 Dispatch Stage Profiling Monitor Block ALU/MUL Register Rename Stage Program Trace Unit Virtual to Physical Register Pool ALU Instruction Queue & Dispatch Out of Order Write-back Stage FPU/NEON Dual Instruction Decode Stage Out of Order Multi-issue with Speculation Prediction Queue Instruction Queue Branches Address MemorySystem Instruction P
Chapter 3: Application Processing Unit loops, and increases the pipeline utilization by removing data dependencies between adjacent instructions, which also indirectly reduces interrupt latency. In the Cortex-A9 CPU, dependent load-store instructions can be forwarded for resolution within the memory system to further reduce pipeline stalls. The core supports up to four data cache line fill requests that can be through automatic or user-driven pre-fetching.
Chapter 3: Application Processing Unit Cortex-A9 also employs an 8-entry return stack cache that holds the 32-bit subroutine return addresses. This feature greatly reduces the penalty of executing subroutine calls and can address nested routines up to eight levels deep. Instruction and Data Alignment ARM architecture specifies the ARM instructions as being 32-bits wide and requires them to be word-aligned. Thumb instructions are 16-bits wide and are required to be half-word aligned.
Chapter 3: Application Processing Unit • Each cache can be disabled independently, using the system control coprocessor. Refer to the System Control Register in the ARM Cortex-A9 Technical Reference Manual. • The cache line lengths for both L1 caches are 32 bytes. • Both caches are 4-way set-associative. • L1 caches support 4 KB, 64 KB, 1 MB, and 16 MB virtual memory page. • Neither of the two L1 caches supports the lock-down feature.
Chapter 3: Application Processing Unit • Both data cache read misses and write misses are non-blocking, with up to four outstanding data cache read misses and up to four outstanding data cache write misses being supported. • The APU data caches offer full snoop coherency control using the MESI algorithm. • The data cache in Cortex-A9 contains local load/store exclusive monitor for LDREX/STREX synchronizations. These instructions are used to implement semaphores.
Chapter 3: Application Processing Unit 3.2.4 Memory Ordering Memory Ordering Model The Cortex-A9 architecture defines a set of memory attributes with the characteristics required to support all memory and devices in the system memory map. The following mutually-exclusive main memory type attributes describe the memory regions: • Normal • Device • Strongly-ordered Device and Strongly Ordered Accesses to strongly ordered and device memory have the same memory ordering model.
Chapter 3: Application Processing Unit • Unaligned accesses can be performed. • Multiple accesses can be merged by processor hardware into a smaller number of accesses of a larger size. Multiple byte writes could be merged into a single double-word write, for example. Memory Attributes In addition to memory types, the ordering of accesses for regions of memory is also defined by the memory attributes. The following sub-sections discuss these attributes.
Chapter 3: Application Processing Unit See the Cache Policies of ARM architecture, for information on these attributes. The Cortex-A9 CPU also provides independent cacheability attributes for normal memory for two conceptual levels of cache, the inner and the outer cacheable. Inner refers to the innermost caches, and always includes the lowest level of cache, that is, L1 cache. Outer cache refers to L2 cache.
Chapter 3: Application Processing Unit Data Synchronization Barrier (DSB) The DSB instruction has the same effect as the DMB, but in addition to this, it also synchronizes the memory accesses with the full instruction stream, not just other memory accesses. This means that when a DSB is issued, execution stalls until all outstanding explicit memory accesses have completed. When all outstanding reads have completed and the write buffer is drained, execution resumes as normal.
Chapter 3: • Memory types: strongly-ordered, device, or normal • Shareability • Cacheability Application Processing Unit The following rules apply when a physical memory location is accessed with mismatched attributes: 1. When a memory location is accessed with mismatched attributes, the only software visible effects are one or more of the following: ° Uni-processor semantics for reads and writes to that memory location might be lost.
Chapter 3: ° ° Application Processing Unit After writing to the location with the write-back attribute, a thread of execution must clean the location from the caches to make the write visible to external memory. Before reading the location with a cacheable attribute, a thread of execution must invalidate the location from the caches to ensure that any value held in the caches reflects the last value made visible in external memory. In all cases: 5.
Chapter 3: Application Processing Unit MMU Functional Description The key feature of MMU is the address translation. It translates addresses of code and data from the virtual view of memory to the physical addresses in the real system. It enables tasks or applications to be written in a way which requires them to have no knowledge of the physical memory map of the system, or about other programs which might be running at the same time.
Chapter 3: Application Processing Unit support 4 KB and 64 KB pages, a 1 MB section, and a 16 MB super-section. Using bigger page sizes means a smaller translation table. Using a smaller page size, 4 KB, greatly increases the efficiency of dynamic memory allocation and defragmentation, but it would require one million entries to span the entire 4 GB address range.
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-5 14 31 23 24 20 19 18 17 16 15 13 11 9 10 Fault 12 0 AP[2] TEX[2:0] NS 1 nG S TEX[2:0] 0 Domain S 0 Extended Base Address PA[39:36] nG AP[1:0] 0 AP[1:0] NS AP[2] Extended Base Address PA[35:32] Supersection Base Address PA[31:24] Section Base Address, PA [31:20] Page Table Base Address, bits [31:10] Domain Page Table Section 4 3 2 IGNORE Reserved Supersection 8 7 6 5 SBZ NS SBZ XN C B Reserv
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-6 Translation Table Base Address 31 14 13 0 Virtual Address 31 31 Level 1 Table 14 13 20 19 0 2 10 First Level Descriptor Address 0 31 20 19 18 17 10 2 10 Section Base Address Descriptor 31 20 19 0 Physical Address UG585_c3_07_102112 Figure 3-6: Generating a Physical Address from an L1 Page Table Entry Level 2 Page Tables An L2 page table has 256 word-sized entries, requires 1KB of memory space and must be aligned to a
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-7 31 16 15 14 13 12 11 10 9 6 5 4 3 2 0 0 SBZ AP C B 0 1 TEX [2:0] AP C B 1 XN S 0 APX Small Page Base Address S 1 APX TEX [2:0] nG Small Page Large Page Base Address nG Large Page 7 IGNORE XN Fault 8 UG585_c3_08_1022112 Figure 3-7: L2 Page Table Entry Format The fields mentioned in Figure 3-7 are discussed in Description of Page Table Entry Fields.
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-8 Translation Table Base Address 31 14 13 0 Virtual Address 31 31 Level 1 Table 14 13 20 19 12 11 0 2 10 Level 1 Descriptor Address TTB 01 31 10 9 2 10 Level 2 Table Base Address Level 2 Table 31 10 9 2 10 Level 2 Descriptor Address 2TB 10 31 12 11 2 10 Small Page Base Address 31 12 11 0 Physical Address UG585_c3_09_102112 Figure 3-8: Generating a Physical Address from an L2 Page Table Entry Description of Pag
Chapter 3: Table 3-2: Application Processing Unit Access Permission Encodings APX AP1 AP0 Privileged Unprivileged Description 0 0 0 No access No access Permission fault 0 0 1 Read/Write No access Privileged access only 0 1 0 Read/Write Read No user-mode write 0 1 1 Read/Write Read/Write Full access 1 0 0 ~ ~ Reserved 1 0 1 Read No access Privileged Read only 1 1 0 Read Read Read only 1 1 1 ~ ~~ Reserved Memory Attributes (TEX, C and B bits) TEX, C, a
Chapter 3: Application Processing Unit Domains A domain is a collection of memory regions. Domains are only valid for L1 page table entries. The L1 page table entry format supports 16 domains, and requires the software that defines a translation table to assign each memory region to a domain. The domain field specifies which of the 16 domains the entry is in, and a two-bit field in the Domain Access Control register (DACR) defines the permitted access for each domain.
Chapter 3: Application Processing Unit TLB uses a pseudo round-robin replacement policy to determine which entry in the TLB should be replaced in the case of a miss. Unlike some other RISC processors that require software to manage the updates of the TLB from the page table that resides in the memory, the main TLB in Cortex-A9 supports hardware page table walks to perform look-ups in the L1 data cache. This allows the page tables to be cached.
Chapter 3: Application Processing Unit Entries in the lockable region of the main TLB are lockable at the granularity of a single entry. As long as the lockable region does not contain any locked entries, it can be allocated with non-locked entries to increase overall main TLB storage size. Translation Table Base Register 0 and 1 When managing multiple applications with their individual page tables, there is a need to have multiple copies of the L1 page table, one for each application.
Chapter 3: Application Processing Unit Supersections, sections, and large pages are supported to permit mapping of a large region of memory while using only a single entry in a TLB. If no mapping for an address is found within the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB.
Chapter 3: Application Processing Unit X-Ref Target - Figure 3-9 Is the translation in TLB? Translation Request Yes Perform Translation Translation Result No TLB Update Yes Table walking enabled? Yes Entry exists in Page Table? No No Translation Fault UG585_c3_10_102112 Figure 3-9: Translation Process TLB Maintenance Operations The following rules describe the TLB maintenance operations: • A TLB invalidate operation is complete when all memory accesses using the TLB entries that have bee
Chapter 3: • Application Processing Unit ° The execution of a DSB instruction to ensure the completion of the TLB operation. ° A subsequent ISB instruction, or taking an exception, or returning from an exception. The execution of an instruction or unified TLB maintenance operation is only guaranteed to be visible to subsequent instruction fetch after both: ° The execution of a DSB instruction to ensure the completion of the TLB operation.
Chapter 3: Application Processing Unit Debug and Trace Interfaces Each Cortex-A9 processor has a standard 32-bit APB slave port that operates at the CPU_1x clock frequency and is accessed through the debug APB bus master in the SOC debug block. The operation of this block is explained in the corresponding chapter of this document. The Cortex-A9 processors also include a pair of interfaces for trace generation and cross trigger control.
Chapter 3: • 8 or 16-bit polynomial computation for single-bit coefficients • Structured data load capabilities • Dual issue with Cortex-A9 processor ARM or Thumb instructions • Independent pipelines for VFPv3 and advanced SIMD instructions • Large, shared register file, addressable as: ° Thirty-two 32-bit S (single) registers ° Thirty-two 64-bit D (double) registers ° Sixteen 128-bit Q (quad) registers Application Processing Unit See the ARM Architecture Reference Manual for details of the
Chapter 3: Application Processing Unit The SCU can also copy clean data from one processor cache to another and eliminate the need for main memory accesses to perform this task. Furthermore, it can move dirty data between the processors, skipping the shared state and avoiding the latency associated with the write-back. IMPORTANT: It is important to note that the Cortex-A9 does not guarantee coherency between the L1 instructions caches as the processor is not capable of modifying the L1 contents directly.
Chapter 3: Application Processing Unit 3.4 L2-Cache 3.4.1 Summary The L2 cache controller is based on the ARM PL310 and includes an 8-way set-associative 512 KB cache for dual/single Cortex-A9 cores. The L2 cache is physically addressed and physically tagged and supports a fixed 32-byte line size. These are the main features of the L2 cache: • Supports snoop coherency control utilizing MESI algorithm. • Offers parity check for L2 cache memory. • Supports speculative read operations in the SMP mode.
Chapter 3: Application Processing Unit Cache Response This section describes the general behavior of the cache controller depending on the Cortex-A9 transactions. These are the descriptions for the different type of transactions: Bufferable The transaction can be delayed by the interconnect or any of its components for an arbitrary number of cycles before reaching its final destination. This is usually only relevant to writes.
Chapter 3: Table 3-5: Application Processing Unit Cache Controller Behavior for SCU Requests Transaction Type ARMv7 Equivalent L2 Cache Controller Behavior Non-cacheable and non-bufferable Strongly ordered • Read: Not cached in L2, results in memory access. • Write: Not buffered, results in memory access. Bufferable only Device • Read: Not cached in L2, results in memory access. • Write: Placed in store buffer, not merged, immediately drained to memory.
Chapter 3: Table 3-5: Application Processing Unit Cache Controller Behavior for SCU Requests (Cont’d) Transaction Type ARMv7 Equivalent L2 Cache Controller Behavior Cacheable write-through, allocate on read and write Outer write-through, allocate on both reads and writes • Read hit: Read from L2. • Read miss: Line fill to L2. • Write hit: Put in store buffer, write to L2 and memory when store buffer is drained. • Write miss: Put in store buffer.
Chapter 3: • Application Processing Unit For a miss, if the cache line is evicted (AWUSERS[8] is 1), the cache line is allocated and its dirty status depends on if it is evicted dirty or not. If the cache line is evicted dirty (AWUSERS[8] is 0), the cache line is allocated only if it is write allocate. 3.4.3 Cache Replacement Strategy Bit [25] of the Auxiliary Control register configures the replacement strategy. It can be either round-robin or pseudo-random.
Chapter 3: Application Processing Unit 32-bit cache address consists of the following fields: [Tag Field], [Index Field], [Word Field], [Byte Field]. When a cache lookup occurs, the index defines where to look in the cache ways. The number of ways defines the number of locations with the same index referred to as a set. Therefore, an 8-way set associative cache has eight locations where an address with index A can exist. There are 2 11 or 2,048 indices in the 512K L2 cache.
Chapter 3: Application Processing Unit 3.4.5 Enabling and Disabling the L2 Cache Controller The L2 cache is disabled by default and can be enabled by setting bit 0 of the L2 cache control register independently of the L1 caches. When the cache controller block is not enabled, depending on their addresses, transactions pass through to the DDR memory or the main interconnect on the cache controller master ports.
Chapter 3: Application Processing Unit Merging condition is based on address and security attribute. Merging takes place only when data is in the store buffer and it is not draining. When a write-allocate cacheable slot is drained, misses in the cache, and is not full, the store buffer sends a request through the master ports to the main interconnects or DDR to complete the cache line.
Chapter 3: Application Processing Unit No additional programming of the L2 Controller is required. Application of the pre-fetch hints to the OCM memory space does not cause any action because, unlike caches, transfer of data into OCM RAM requires explicit operations by software. Full Line of Zero Write When this feature is enabled, the Cortex-A9 processor can write entire non-coherent cache lines of zeroes to the L2 cache, using a single write command cycle.
Chapter 3: Application Processing Unit By default, the pre-fetch offset is 5'b00000. For example, if S0 receives a cacheable read at address 0x100, the cache line at address 0x120 is pre-fetched. Pre-fetching the next cache line might not necessarily result in optimal performance. In some systems, it might be better to pre-fetch more in advance to achieve better performance. The pre-fetch offset enables this by setting the address of the pre-fetched cache line to Cache Line + 1 + Offset.
Chapter 3: Application Processing Unit • Write to the interrupt clear register to clear any residual raw interrupts set. • Write to the interrupt mask register if it is desired to enable interrupts. • Write to control register 1 with the LSB set to 1 to enable the cache. If a write is performed to the auxiliary, tag RAM latency, or data RAM latency control register with the L2 cache enabled, a SLVERR (error) results.
Chapter 3: Application Processing Unit 3.5 APU Interfaces 3.5.1 PL Co-processing Interfaces ACP Interface The accelerator coherency port (ACP) is a 64-bit AXI slave interface on the SCU that provides an asynchronous cache-coherent access point directly from the PL to the Cortex-A9 MP-Core processor subsystem.
Chapter 3: Application Processing Unit Note: The transaction can optionally allocate into the L2 cache if the write parameters are set accordingly. ACP non-coherent write requests: An ACP write request is non-coherent when AWUSER[0] = 0 or AWCACHE[1] = 0 alongside AWVALID. In this case, the SCU does not enforce coherency and the write request is forwarded directly to one of the available SCU AXI master ports.
Chapter 3: Table 3-7: Application Processing Unit ACP Read and Write Behavior (Cont’d) Action Description ACP write – S (shared) Data is written to external memory through one of two AXI master interfaces. L1 cache previously with S status is changed to I state ACP write – E (exclusive) Data is written to external memory through one of two AXI master interfaces. Any L1 cache previously with S status is changed to I status.
Chapter 3: Application Processing Unit EVENTEVENTO A toggle output signal indicating that either CPU is executing the SEV instruction. EVENTEVENTI A toggle input signal that wakes up either one or both CPUs if they are in a standby state initiated by the WFE instruction. EVENTSTANDBYWFE[1:0] Two-level output signals indicating the state of the two CPUs. A bit is asserted if the corresponding CPU is in standby state following the execution of the WFE (wait for event) instruction.
Chapter 3: Table 3-8: Application Processing Unit APU Interrupts Interrupt Description 37 Performance monitor unit (PMU) of CPU0 38 Performance monitor unit (PMU) of CPU1 3.6 Support for TrustZone TrustZone is hardware that is built into all Zynq-7000 AP SoC devices. For more information, see Programming ARM TrustZone Architecture on the Xilinx Zynq-7000 All Programmable SoC (UG1019). 3.7 Application Processing Unit (APU) Reset 3.7.
Chapter 3: Application Processing Unit Note: Unlike the POR or system resets, when the user applies a software reset to a single processor, the user must stop the associated clock, de-assert the reset, and then restart the clock. During a system or POR reset, hardware automatically takes care of this. Therefore, a CPU cannot run the code that applies the software reset to itself. This reset needs to be applied by the other CPU or through JTAG or PL.
Chapter 3: Application Processing Unit • The L2 cache can be put in the standby mode when the CPUs are in that mode. • Clock gating is extensively used in all the sub-blocks within the module. Dynamic clock gating in the Cortex-A9 can be enabled in the CP15 power control register. If enabled, the clocks to the CPU internal blocks are dynamically disabled in idle periods. The gated blocks include the integer core, the system control block, and the data engine.
Chapter 3: • Application Processing Unit No remaining activity in the SCU The SCU resumes normal operation when a CPU leaves WFI mode or a request on the ACP occurs. The standby mode of the L2 cache controller can be enabled by setting bit 0 of the L2 controller power control register (l2cpl310.reg15_power_ctrl). This mode is used in conjunction with the wait state (WFI/WFE) of the processor that drives the controller.
Chapter 3: Application Processing Unit 3.10 Implementation-Defined Configurations The Zynq-7000 AP SoC APU has implemented some configurations which determine the reset values of some CP15 register fields. Table 3-10 shows these configuration signals and the reset values of the corresponding register fields. Table 3-10: Implementation Configuration Signals and Register Fields Configuration Signal Register Fields Bits Reset Value [10:8] b111 MAXCLKLATENCY c15.Power control register CFGEND c1.
Chapter 4 System Addresses 4.1 Address Map The comprehensive system level address map is shown in Table 4-1. The shaded entries indicate that the address range is reserved and should not be accessed. Table 4-2 identifies reserved address ranges.
Chapter4: SystemAddresses Notes: 1. The other bus masters include the S_AXI_GP interfaces, Device configuration interface (DevC), DAP controller, DMA controller and the various controllers with local DMA units (Ethernet, USB and SDIO). 2. The OCM is divided into four 64 KB sections. Each section is mapped independently to either the low or high addresses ranges, but not both at the same time.
Chapter4: SystemAddresses 4.2 System Bus Masters The CPUs and AXI_ACP see the same memory map, except the CPUs have a private bus to access their private timer, interrupt controller, and shared L2 cache / SCU registers. The AXI_HP interfaces provide high bandwidth to the DDR DRAM and OCM memory.
Chapter4: SystemAddresses 4.4 CPU Private Bus Registers The registers shown in Table 4-4 are only accessible by the CPU on the CPU private bus. The accelerator coherency port (ACP) cannot access any of the private CPU registers. The private CPU registers are used to control subsystems in the APU.
Chapter4: SystemAddresses 4.6 PS I/O Peripherals The I/O Peripheral registers are accessed via a 32-bit APB bus, shown in Table 4-6.
Chapter4: Table 4-7: SystemAddresses PS System Register Map (Cont’d) Register Base Address F880_0000 Description (Acronym) CoreSight debug control Register Set cti. Notes: 1. One-time programmable non-volatile memory used to support RSA authentication of the FSBL. Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Chapter 5 Interconnect 5.1 Introduction The interconnect located within the PS comprises multiple switches to connect system resources using AXI point-to-point channels for communicating addresses, data, and response transactions between master and slave clients. This ARM AMBA 3.0 interconnect implements a full array of the interconnect communications capabilities and overlays for QoS, debug, and test monitoring.
Chapter 5: Interconnect 5.1.2 Block Diagram This section discusses the block diagram for all the interconnect, including the interconnect masters, the snoop control unit, central interconnect, master interconnect, slave interconnect, memory interconnect, and OCM interconnect. Figure 5-1 shows the block diagram for the interconnect.
Chapter 5: Interconnect X-Ref Target - Figure 5-1 Synchronous CPU clock domain Asynchronous to is asynchronous to all else. all else.
Chapter 5: Interconnect L2 Cache Controller The functionality of the L2 cache controller is described in Chapter 3, Application Processing Unit. The address filtering feature of the L2 cache controller makes the L2 cache controller function like a switch from the perspective of the traffic from its AXI slave ports to its AXI master ports. Interconnect Slaves The interconnect slaves are shown toward the bottom of Figure 5-1.
Chapter 5: Interconnect Table 5-1: Interconnect Datapaths (Cont’d) Source Destination Type Clock at source Clock at destination Sync or Async(1) Data width Memory interconnect OCM interconnect AXI DDR_2x CPU_2x Async 64 - - Central interconnect OCM interconnect AXI CPU_2x CPU_2x Sync 64 - - L2 Cache Slave interconnect AXI CPU_6x4x CPU_2x Sync 64 8, 8 - Central interconnect Slave interconnect AXI CPU_2x CPU_2x Sync 64 - - SCU On-chip RAM AXI CPU_6x4x CPU_2x S
Chapter 5: Interconnect Table 5-2: Clocks used by Interconnect, Masters, and Slaves (Cont’d) CPU_6x4x: CPUs, SCU, L2 Cache controller, On-Chip RAM SAXIACPACLK AXI_ACP slave port SAXIHP0ACLK AXI_HP0 slave port SAXIHP1ACLK AXI_HP1 slave port SAXIHP2ACLK AXI_HP2 slave port SAXIHP3ACLK AXI_HP3 slave port SAXIGP0ACLK AXI_GP0 slave port SAXIGP1ACLK AXI_GP1 slave port MAXIGP0ACLK AXI_GP0 master port MAXIGP1ACLK AXI_GP1 master port Except for CPU_6X4X, CPU_2X, and CPU_1X, which are synchronou
Chapter 5: Interconnect X-Ref Target - Figure 5-2 Cache Coherent AXI P port (AXI_ACP) High Performance AXI Controllers (AXI_HP) Async S_AXI_GP Async Async DevC DAP CPUs CPU_6x4x Snoop Control Unit (SCU) CPU_6x4x Memory Interconnect DDR_2x Async Slave Interconnect Masters DMA Controller CPU_2x CPU_1x CPU_2x 6:2:1 or 4:2:1 Ratio CPU_6x4x CPU_2x CPU_6x4x On-chip RAM L2 Cache Central Interconnect CPU_2x OCM Interconnect CPU_2x Master Interconnect Async Async DDR Memory Controller
Chapter 5: Interconnect 5.1.5 Connectivity The interconnect is not a full cross-bar structure. Table 5-3 shows which master can access which slave. Master - Slave Access Slave Table 5-3: On-chip RAM DDR Port 0 M_AXI _GP AHB Slaves APB Slaves GPV CPUs X X X X X X AXI_ACP X X X X X X AXI_HP{0,1} X AXI_HP{2,3} X S_AXI_GP{0,1} X X X X X DMA Controller X X X X X AHB Masters X X X X X DevC, DAP X X X X X Master DDR Port 1 DDR Port 2 DDR Port 3 X X 5.1.
Chapter 5: Interconnect Table 5-4: Slave Visible AXI ID Values (Cont’d) Master Master ID Width AXI ID (as seen by the slaves) DAP 0 13’b0100000000001 S_AXI_GP0 6 13’b01000xxxxxx10 S_AXI_GP1 6 13’b01000xxxxxx11 CPUs, AXI_ACP through L2 M1 port 8 13’b011xxxxxxxx00 CPUs, AXI_ACP through L2 M0 port 8 13’b100xxxxxxxx00 Notes: 1. x, which can be either 0 or 1, originates from the requesting master. 5.1.
Chapter 5: Interconnect 5.2 Quality of Service (QoS) 5.2.1 Basic Arbitration Each interconnect (central, master, slave, memory) uses a two-level arbitration scheme to resolve contention. The first-level arbitration is based on the priority indicated by the AXI QoS signals from the master or programmable registers. The highest QoS value has the highest priority.
Chapter 5: Interconnect (through L2 cache), the DMA controller, and the IOP masters can interfere with traffic from the PL. The QoS modules allow you to throttle these PS masters to ensure expected/consistent throughput and latency for the user design in the PL or specific PS masters. This is especially useful for video, which requires guaranteed maximum latency.
Chapter 5: Interconnect • Large slave interface write acceptance capability in the range of 8 to 32 commands (burst length dependent) 5.3.2 Block Diagram Figure 5-3 shows the block diagram for the AXI_HP interfaces.
Chapter 5: Interconnect 5.3.3 Functional Description There are two sets of AXI ports, one set connecting directly to the PL and the other connecting to the AXI interconnect matrix, allowing access to DDR and OCM memory (see Figure 5-4).
Chapter 5: Interconnect 5.3.5 Register Overview A partial list of registers related to the high performance AXI port is listed in Table 5-6 Table 5-6: High Performance (AFI) AXI Register Overview Module AXI_HP OCM DDRC SLCR Register Name Overview AFI_RDCHAN_CTRL AFI_WRCHAN_CTRL Select 64- or 32-bit interface width mode. Various bandwidth management control settings.
Chapter 5: Interconnect Table 5-7: Additional per-port HP PL Signals Type FIFO occupancy PS-PL Signal Name I/O SAXIHP{0-3}RCOUNT[7:0] O Fill level of the RdData channel FIFO SAXIHP{0-3}WCOUNT[7:0] O Fill level of the WrData channel FIFO SAXIHP{0-3}RACOUNT[2:0] O Fill level of the RdAddr channel FIFO SAXIHP{0-3}WACOUNT[5:0] O Fill level of the WrAddr channel FIFO SAXIHP{0-3}AWQOS[3:0] I WrAddr channel QOS input.
Chapter 5: Interconnect Interconnect Issuance Throttling To optimize the latency or throughput of other masters in the system such as the CPUs, it might be desirable to constrain the number of outstanding transactions that a high-performance port requests to the system interconnect. Issuing capability is the maximum number of outstanding commands that a HP can request at any one time.
Chapter 5: Interconnect For the 32-bit mode, an “expansion” or “upsizing” must be performed to the 64-bit bus. These are defined as follows: • Expansion. The AxSIZE[] and AxLEN[] signals remain unchanged on the 64-bit bus. The number of data beats in the 64-bit domain is therefore the same as the number of data beats in the 32-bit domain. This is the simplest option but also the most inefficient in terms of bandwidth utilization. • Upsizing.
Chapter 5: Interconnect 5.3.7 Transaction Types Table 5-8 summarizes the command types issued to the high performance AXI interface from the PL, and the command modifications that occur. Table 5-8: High Performance AXI Interface Command Types No. Mode Command Type Translation Comments 1 64-bit 64-bit reads all burst types None Best optimization possible 2 64-bit Narrow read None Because no upsizing is performed, the narrower the width, the more inefficient the transaction.
Chapter 5: Interconnect 5.3.9 Performance Optimization Summary This section summarizes the most important considerations when using the high performance AXI interface module from a software or user perspective. • For general purpose AXI transfers, use the general purpose PS AXI ports and not these ports. These ports are optimized for high throughput applications, but have various limitations.
Chapter 5: Interconnect 5.4 AXI_ACP Interface The accelerator coherency port provides low-latency access to programmable logic masters, with optional coherency with L1 and L2 cache. From a system perspective, the ACP interface has similar connectivity as the APU CPUs. Due to this close connectivity, the ACP directly competes with them for resource access outside of the APU block. Figure 5-5 gives an overview of the ACP connectivity.
Chapter 5: Interconnect 5.5 AXI_GP Interfaces 5.5.1 Features AXI_GP features include: • Standard AXI protocol • Data bus width: 32 • Master port ID width: 12 • Master port issuing capability: 8 reads, 8 writes • Slave port ID width: 6 • Slave port acceptance capability: 8 reads, 8 writes 5.5.
Chapter 5: Interconnect Table 5-9: AXI Signals Summary AXI PS Masters AXI Channel AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP M_AXI_GP{0,1} I/O I/O MAXIGP{0,1}ACLK I SAXIGP{0,1}ACLK SAXIHP{0:3}ACLK SAXIACPACLK I MAXIGP{0,1}ARESETN O SAXIGP{0,1}ARESETN SAXIHP{0:3}ARESETN SAXIACPARESETN O MAXIGP{0,1}ARADDR[31:0] O SAXIGP{0,1}ARADDR[31:0] SAXIHP{0:3}ARADDR[31:0] SAXIACPARADDR[31:0] I MAXIGP{0,1}ARVALID O SAXIGP{0,1}ARVALID SAXIHP{0:3}ARVALID SAXIACPARVALID I MAXIGP{0,1}ARREADY
Chapter 5: Interconnect Table 5-9: AXI Signals Summary (Cont’d) AXI PS Masters AXI Channel M_AXI_GP{0,1} AXI PS Slaves I/O ~ S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP I/O ~ ~ SAXIACPARUSER[4:0] I Read Data MAXIGP{0,1}RDATA[31:0] I SAXIGP{0,1}RDATA[31:0] SAXIHP{0:3}RDATA[63:0] SAXIACPRDATA[63:0] O MAXIGP{0,1}RVALID I SAXIGP{0,1}RVALID SAXIHP{0:3}RVALID SAXIACPRVALID O MAXIGP{0,1}RREADY O SAXIGP{0,1}RREADY SAXIHP{0:3}RREADY SAXIACPRREADY I MAXIGP{0,1}RID[11:0] I SAXIGP{0,1}RID[5:0] SAXIHP
Chapter 5: Interconnect Table 5-9: AXI Signals Summary (Cont’d) AXI PS Masters AXI Channel AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP M_AXI_GP{0,1} I/O MAXIGP{0,1}AWREADY I SAXIGP{0,1}AWREADY SAXIHP{0:3}AWREADY SAXIACPAWREADY O MAXIGP{0,1}AWID[11:0] O SAXIGP{0,1}AWID[5:0] SAXIHP{0:3}AWID[5:0] SAXIACPAWID[2:0] I MAXIGP{0,1}AWLOCK[1:0] O SAXIGP{0,1}AWLOCK[1:0] SAXIHP{0:3}AWLOCK[1:0] SAXIACPAWLOCK[1:0] I MAXIGP{0,1}AWCACHE[3:0] O SAXIGP{0,1}AWCACHE[3:0] SAXIHP{0:3}AWCACHE[3:0] SAX
Chapter 5: Interconnect Table 5-9: AXI Signals Summary (Cont’d) AXI PS Masters AXI Channel AXI PS Slaves S_AXI_GP{0,1} S_AXI_HP{0:3} S_AXI_ACP M_AXI_GP{0,1} I/O I/O MAXIGP{0,1}WID[11:0] O SAXIGP{0,1}WID[5:0] SAXIHP{0:3}WID[5:0] SAXIACPWID[2:0] I MAXIGP{0,1}WLAST O SAXIGP{0,1}WLAST SAXIHP{0:3}WLAST SAXIACPWLAST I MAXIGP{0,1}WSTRB[3:0] O SAXIGP{0,1}WSTRB[3:0] SAXIHP{0:3}WSTRB[7:0] SAXIACPWSTRB[7:0] I ~ ~ SAXIHP{0:3}WCOUNT[7:0] ~ O ~ ~ SAXIHP{0:3}WACOUNT[5:0] ~ O ~ ~ SAXIHP{0:3}WRISS
Chapter 5: Interconnect attempted. Therefore, no GPV access should be attempted if not all of the clocks for the PS-PL AXI interfaces are connected and operating. 5.7 Loopback Sometimes it can be advantageous to provide a loopback path from the PS to PL and back. A loopback path means that there will be an AXI connection between a PS master and PS slave through the PL, so that designs can manipulate AXI transaction address and/or data in the PL before the data reaches the intended target in the PS.
Chapter 5: Interconnect X-Ref Target - Figure 5-6 SLCR Quad-SPI 1,2,4,8-bit Parallel 8-bit NOR/SRAM System Level Control Registers NEON NEON SP, DP FPU 128-bit Vector DSP SP, DP FPU 128-bit Vector DSP NAND 8,16-bit APB USB USB GigE GigE Register Access DMA DMA ARM A9 32 KB I-Cache 32 KB D-Cache IRQ PS_SRST_B CLK / PLL SCU – Snoop Control Unit 20 I, 29 O ARM, I/O, DDR GPIO x54, x64 L2 OCM UART UART Cache Memory 512 KB On Chip Memory 256 KB I2C I2C CAN CAN DDR DDR DAP DMA 8 chann
Chapter 5: Interconnect To use the L1 exclusive monitor, the addressed MMU region must be set to be inner cacheable and inner cache write-back with write-allocate. This allows an address targeted by a particular exclusive access to always be allocated to L1 cache. To use the L3 exclusive monitor, the access must not terminate at the APU L2 cache. From the ARM CPU perspective, this means the address must be shareable, normal and non-cacheable.
Chapter 5: Interconnect exclusive monitor picks the slot to be used using round-robin mechanism.
Chapter 5: Interconnect 5.8.4 System Summary Exclusive AXI accesses are summarized inTable 5-12. Table 5-12: Exclusive AXI Accesses Summary Exclusive Operation Exclusive Accesses Supported Notes Two A9 CPUs to L1 cache Yes Normal, inner-cacheable, write-back with write-allocate memory regions only ACP doing exclusive access to L1 No ACP does not support exclusive access to coherent memory. CPU0 and CPU1 to location in L2 No L2 does not have exclusive monitors.
Chapter 6 Boot and Configuration 6.1 Introduction Immediately after the PS_POR_B reset pin deasserts, the hardware samples the boot strap pins and optionally enables the PS clock PLLs. Then, the PS begins executing the BootROM code in the on-chip ROM to boot the system. The POR resets the entire device with no previous state saved. The non-POR type resets also cause the BootROM to execute, but without the hardware sampling the strap pins.
Chapter 6: Boot and Configuration In secure mode, the boot image is always written to OCM memory by the CPU. From there, it is sent (using DMA) in and out of the AES/HMAC units for decryption and authentication. The decrypted boot image is written back to OCM memory and executed after the BootROM is finished. Security hardware is described in this chapter and in Chapter 32, Device Secure Boot.
Chapter 6: Boot and Configuration Device Boot Flowchart The POR reset causes the hardware to samples the pin straps, disable modules in the device, and optionally enables the PS clock PLLs. These hardware actions are not performed after a non-POR reset. The first software to run is the BootROM, then the FSBL/User code and system code. All of these steps are shown in Figure 6-1.
Chapter 6: Boot and Configuration from the boot device (execute-in-place). All of the header parameters are described in section 6.3.2 BootROM Header. The last two functions of the BootROM are to disable access to its ROM code and transfer CPU code execution to the FSBL/User code. The execution of the BootROM is detailed in section 6.3.1 BootROM Flowchart. PL Initialization and Configuration The PL must be powered-up before it can be initialized and then configured with the bitstream.
Chapter 6: Boot and Configuration Software Developers Guide and Kit The boot modes and operations are summarized in chapter 3 of the UG821 Zynq-7000 Software Developers Guide. The chapter describes boot methods and ways to program the hardware using the FSBL. The software developers guide also discusses software architectures, tools, and various boot environments, including Linux U-Boot. The software developers kit (SDK) can be used to develop and debug bare-metal applications.
Chapter 6: Boot and Configuration located at address 0x0 (where the OCM ROM is initially located) to determine their own identity. Note that single-core devices contain one processor, dual-core devices contain two. CPU 1, when present, parks itself by executing the WFE instruction. CPU 0 continues to execute the BootROM. Stage 1 (FSBL / User code) This is generally the First Stage Boot Loader, but it can be any user-controlled code.
Chapter 6: Boot and Configuration JTAG (Slave Mode Boot) The JTAG boot mode is considered a Slave Mode boot and is always a non-secure boot mode. The JTAG chain can be configured in cascade or independent mode. During the boot sequence, the chain is configured according to the setting of the MIO [2] boot strapping pin. Normally, the system is configured for cascade mode. When the TRM refers to JTAG boot mode, it means JTAG cascade mode unless stated otherwise.
Chapter 6: Boot and Configuration If the system is booted in secure mode and then reset by a non-POR reset with a BootROM Header that indicates a non-secure boot, then the system goes into a secure lockdown with error code 0x201A. BootROM Header Search If the BootROM does not detect a valid BootROM Header, the BootROM performs a search function to find another BootROM Header. The search function is described in section 6.3.10 BootROM Header Search.
Chapter 6: Boot and Configuration The user code can force the device into a secure lockdown, if desired, by writing to the devcfg.CTRL [FORCE_RST] bit. A POR reset is required to start up the system from this and all secure lockdowns. FSBL Image Fallback and Multiboot If the FSBL detects an error or wants to use a different FSBL image, then it writes the boot image address to the devcfg.MULTIBOOT_ADDR [MULTIBOOT_ADDR] field and performs a software system reset. This is briefly described in section 6.3.
Chapter 6: Boot and Configuration X-Ref Target - Figure 6-2 ICAP Path PCAP Path PL pre-programmed. PL or PS-based Software PS Software JTAG Debug PL Logic Serial Interface Non-secure DevC with DMA AXI_HWICAP PCAP Controller ICAP Controller TAP Controller 1 0 Fabric Multiplexer Multiplexer 1 PL Configuration Module 0 devc.CTRL [PCAP_PR] devc.
Chapter 6: Boot and Configuration 6.1.9 Device Configuration Interface The device configuration interface (DevC) includes three logic modules to initialize and configure the PL under PS software control (PCAP path), manage device security, and access the XADC. The DevC also includes a set of control/status registers for these three main functional modules. Features • • • PCAP Bridge with DMA is used by the PS software to configure the PL and decrypt images.
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Chapter 6: Boot and Configuration 6.1.10 Starting Code on CPU 1 CPU 0 is in charge of starting code execution on CPU 1. The BootROM puts CPU 1 into the Wait for Event mode. Nothing has been enabled and only a few general purpose registers have been modified to place it in a state where it is waiting at the WFE instruction. There is a small amount of protocol required for CPU 0 to start an application on CPU1.
Chapter 6: Boot and Configuration 6.2 Device Start-up This section includes the following subsections: • section 6.2.1 Introduction • section 6.2.2 Power Requirements • section 6.2.3 Clocks and PLLs • section 6.2.4 Reset Operations • section 6.2.5 Boot Mode Pin Settings • section 6.2.6 I/O Pin Connections for Boot Devices 6.2.1 Introduction The Zynq-7000 device start-up requires proper voltage sequencing and I/O pin control.
Chapter 6: Boot and Configuration PL Power-Down The PL power-down sequence includes stopping the use of all signals between the PS and PL, disabling the voltage level shifters, and powering off the PL. An example sequence is shown in section 2.4 PS–PL Voltage Level Shifter Enables. 6.2.3 Clocks and PLLs The PS_CLK reference clock is routed to multiple sections of the device, including the three PS clock PLLs. The frequency of the PS_CLK affects the boot time of the device.
Chapter 6: Boot and Configuration External Reset Signal Pins There are two external reset pins: • PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low during PS power supply ramp-up. PS_POR_B can be generated by the power supply “power-good” signal. The POR reset is the only reset to sample the boot mode pin strap resistors.
Chapter 6: Boot and Configuration Internal Resets The internal resets are all non-POR resets. Resets are described in Chapter 26, Reset System. • Software controlled reset: write 1 to slcr.PSS_RST_CTRL [SOFT_RST]. • Watchdog timers: AWDT0, AWDT1, and SWDT controllers. • JTAG interface and debug. Reset Reason The type of reset that last occurred (reset reason) is recorded in the slcr.REBOOT_STATUS register. This register also includes the BootROM error code, when it is generated.
Chapter 6: Table 6-3: System Reset Effects (Cont’d) Reset Type Resets PL Boot and Configuration POR Yes Non-POR Yes Notes: 1. The Boot_Mode [4] pin strap determines if the PLLs are enabled or bypassed. 2. There are a number of register and individual register bit fields that are not affected by a non-POR reset. Refer to Table 26-2, page 707 for a list . User Defined Persistent Bit Field The 16-bit user defined persistent bit field is located in the devcfg.MULTIBOOT_ADDR register, bits 31:16.
Chapter 6: Table 6-4: Boot and Configuration Boot Mode MIO Strapping Pins Pin-signal / Mode MIO[8] MIO[7] MIO[6] MIO[5] MIO[4] MIO[3] MIO[2] VMODE[1] VMODE[0] BOOT_MODE[4] BOOT_MODE[0] BOOT_MODE[2] BOOT_MODE[1] BOOT_MODE[3] Boot Devices JTAG Boot Mode; cascaded is most common(1) 0 0 0 NOR Boot(3) 0 0 1 NAND 0 1 0 Quad-SPI(3) 1 0 0 SD Card 1 1 0 JTAG Chain Routing(2) 0: Cascade mode 1: Independent mode Mode for all 3 PLLs PLL Enabled 0 PLL Bypassed 1 Hardware waits
Chapter 6: Boot and Configuration 6.3 BootROM The BootROM executes after a system reset to configure the PS as described in the introduction. This section provides the details of the boot process, the format of the BootROM Header, the BootROM performance with examples, the functions and needs of each boot device, the various boot images, and the boot failure error codes. This section includes the following subsections: • 6.3.1 BootROM Flowchart • 6.3.2 BootROM Header • 6.3.
Chapter 6: Boot and Configuration Secure/Non-Secure For security reasons, CPU 0 is always the first device out of reset among all master modules within the PS. CPU 1 is held in an WFE state. While the BootROM is running, JTAG is always disabled, regardless of the reset type, to ensure security. After the BootROM runs, JTAG is enabled if the boot mode is non-secure. The BootROM code is also responsible for loading the FSBL/User code.
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Chapter 6: Boot and Configuration APU Initialization The BootROM configures the APU and MIO multiplexer to support the boot process. The state of the MIO pins for each boot mode is described in tables in the Boot Device sections (for example, Table 6-9 for Quad-SPI). The BootROM uses the CPU 0 to execute the ROM code. CPU 1 executed the WFE instruction. The caches and TLBs are invalidated. The BootROM configures the MMU and other system resources to meet the needs of the BootROM execution.
Chapter 6: Table 6-5: Boot and Configuration BootROM Header Parameters (Cont’d) Boot Device Header Address 32-bit Word Secure Usage Parameter 19 - 39 FSBL/User Defined(84-Byte) (3) 0x0A0 - 0x89F 40 - 551 Register Initialization (2048-Byte) (4) 0x8A0 - 0x8BF 552 - 559 0x8C0 560 and up 0x04C - 0x09F FSBL/User Defined (32-Byte) (3) FSBL Image or User Code Non-Secure Usages OCM OCM Execute In Place (6) ~ ~ ~ yes yes yes ~ ~ ~ 192 KB 192 KB see (5) Notes: 1.
Chapter 6: Boot and Configuration matched, the BootROM performs a BootROM Header search if the boot mode is either Quad-SPI, NAND, or NOR. If the boot mode is SD card, the BootROM lockdowns the system and generates an error code. Encryption Status — 0x028 Encryption Status determines if the boot is secure (the boot image is encrypted) or non-secure mode. Valid values for this field are: • 0xA5C3C5A3 Encrypted FSBL/User code (requires eFUSE key source).
Chapter 6: Boot and Configuration Reserved — 0x038 This word is reserved and must be initialized to 0x0. Start of Execution — 0x03C • • This is a byte address that is relative to the start of system memory and is used for both executing the FSBL/User code from the OCM or using the optional execute-in-place feature of Quad-SPI and NOR boot modes. The byte address must be aligned to a 64-byte boundary.
Chapter 6: Boot and Configuration are commonly used to optimize the boot device interface and set its clock frequency to maximize performance. These register writes are done toward the end of the BootROM execution. A register initialization pair appears as two 32-bit words, first a register address, then a register write value. Register initializations can be in any order, and the same register can be initialized with different values as many times as desired.
Chapter 6: Table 6-7: Boot and Configuration BootROM Accessible Address Ranges for Register Initialization (Cont’d) Control Registers Non-Secure Boot Mode UART 0, USB, I2C, SPI, CAN, GPIO, GigE, TTC, DMAC, SWDT, DDR, DevC, AXI HP Secure Boot Mode Exceptions to Range(1) Ranges Not accessible Not accessible Notes: 1. The registers in this column are not accessible by the Register Initialization writes. FSBL/User Defined — 0x8A0 - 0x8BF This memory area may be used by the FSBL or User code.
Chapter 6: 7. ° BootROM RSA authentication, if enabled by eFuse. ° BootROM AES/SHA decryption/authentication (secure boot). Boot and Configuration BootROM branches to FSBL/User code. Start-up details and PL configuration information is provided in section 6.4 Device Boot and PL Configuration. PS PLL Lock Time The PLL is enabled by a pin strap. If the PLL is in bypass mode and then enabled by PS software, the PLL with take some time to lock.
Chapter 6: Boot and Configuration When the PL power is required, the BootROM checks to determine if the PL is powered on before accessing modules in the PL. If the PL is powered-up, then it checks to see if the PL clearing process completed. It waits up to 90 seconds (PS_CLK = 60 MHz) for the process to be done. A slower PS_CLK frequency means the BootROM will wait longer than the 90 seconds. If the PL is not cleared by this time, then the BootROM locks down the system and generate an error code.
Chapter 6: Boot and Configuration A timing window calculator that also takes into account PVT variations provides a quick way to assess if the design is exposed to the risk of a secure lock down as described above. The calculator is available through AR# 63149. PS_POR_B must be de-asserted outside the Secure Lock Down window shown in the calculator to avoid the risk. Note: Tslw(min) and Tslw(max) values can be negative in some cases.
Chapter 6: Boot and Configuration RSA authentication time, or the time for the 128 KB CRC check on the BootROM is not included. The PL TPOR time includes power-up and internal hardware sequencing. 6.3.4 Quad-SPI Boot Quad-SPI boot has these features: • x1, x2, and x4 single device configuration. • Dual SS, 8-bit parallel I/O device configuration. • Dual SS, 4-bit stacked I/O configuration. • Execute-in-place option.
Chapter 6: Boot and Configuration header is split across both devices. The BootROM forms a 32-bit word that includes the even bits of the Width Detection ( 0x20 ) and Image Identification (0x24 ) parameter values. When the BootROM detects this condition, it assumes the system uses the 8-bit parallel configuration and programs the controller for the x8 operating mode. This mode is used for the rest of the boot process. The Quad-SPI I/O configurations are shown in section 12.5 I/O Interface.
Chapter 6: Boot and Configuration Execute-in-Place Option For the execute-in-place option, the BootROM uses the linear addressing feature of the Quad-SPI controller for non-secure boot modes. In this case, the initial FSBL/User code must fit inside the first 16 MB of memory for a single device and 32 MB of memory for a x8 dual Quad-SPI device system. Configuration Register Settings The BootROM sets qspi.
Chapter 6: Table 6-10: Boot and Configuration Quad-SPI Boot Time Optimization Register Setting Examples (Cont’d) Register qspi.LQSPI_CFG Width Security (2) Register Value All Non-secure (1) Description Device Configuration 1. The qspi.LQSPI_CFG register value depends on the type of device, the interface width and the number of devices attached. Optimized values for the qspi.LQSPI_CFG register are shown in Table 12-3, page 344. 2. In secure mode, the qspi and slcr.
Chapter 6: Table 6-11: Boot and Configuration NAND Boot MIO Register Settings (Cont’d) NAND Flash I/O Interface Signal Name (SMC controller) Pin State MIO Pin Number MIO_PIN Register Setting(1) I/O I/O Buffer Output, Pull-up External Connection MIO 9 to 12 0x1610 I/O Enabled, pull-up ~ NAND_IO[3] MIO 13 0x1610 I/O Enabled, pull-up ~ NAND_BUSY MIO 14 0x0610 I 3-state ~ not NAND MIO 15 0x1601 I 3-state ~ not NAND MIO 24 to 53 0x1601 I 3-state ~ 3-state ~ Enabled, pull
Chapter 6: • Boot and Configuration Partition Memory: dividing flash memory into logical sections (partitions) with consideration for bad blocks. Bad Block Management The BootROM manages bad blocks in the following ways: • It looks for a bad block table (BBT) in the last four blocks of the NAND flash device. • It supports a primary and secondary BBT with versioning allowing safe software updates.
Chapter 6: Boot and Configuration ECC Management The NAND controller can manage 1 bit of ECC in hardware. For more details on the ECC capabilities of the controller, see Chapter 11, Static Memory Controller. The BootROM is aware of on-die ECC devices and disables the controller ECC checking, allowing the NAND device to take care of ECC. Memory Partitions The BootROM treats NAND flash as one continuous partition. From a user perspective, this only affects the Multiboot register.
Chapter 6: Table 6-13: Boot and Configuration NOR Boot MIO Register Settings NOR Flash I/O Interface Signal Name (SMC controller) Pin State MIO Pin Number MIO_PIN Register Setting(1) I/O I/O Buffer Output, Pull-up External Connection SRAM_CE_B[0] MIO 0 0x0608 O Enabled ~ Not used for NOR boot MIO 1 0x1601 I 3-state ~ Not NOR/SRAM MIO 2 0x0601 I 3-state Pull-up/down MIO 3 to 6 0x0608 I/O Enabled Pull-up/down SRAM_OE_B MIO 7 0x0608 O Enabled Pull-up/down SRAM_BLS_B MIO
Chapter 6: Boot and Configuration 6.3.7 SD Card Boot SD card boot supports these features: • Boot from standard SD or SDHC cards • FAT 16/32 file system • Up to 32 GB card densities Note: The SD card boot mode is not supported in 7z010 dual core and 7z007s single core CLG225 devices. Note: The SD card boot mode does not support header search or multiboot. BootROM Steps The BootROM performs these steps in SD card boot mode: 1. Initializes the MIO pins listed in Table 6-15. 2.
Chapter 6: Boot and Configuration Boot Page Access When the SD card is reset, it defaults to providing access to the boot page. The BootROM assumes that the boot page is accessible when it executes. If user code changes to a different page and a Zynq system reset occurs without resetting the SD card, then the BootROM will not be able to read the BootROM Header from the boot page of the SD card.
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Chapter 6: Table 6-17: Boot and Configuration JTAG Requirements and Control Function DAP Controller TAP Controller Power requirements PS and PL PS and PL PL configuration Not required Not required for Cascade mode. Required for Independent mode. devcfg.CTRL [JTAG_CHAIN_DIS] Must = 0 Must = 0 devcfg.CTRL [DAP_EN] Must = 111 Must = 111 for Cascade mode. Don’t care for Independent mode.
Chapter 6: Boot and Configuration b. Independent: BootROM waits until the PL to initialized and then shuts down. The EMIO JTAG interface for the DAP controller must be routed through the PL using a bitstream to be operational. 9. User can access the DAP controller for PS system debug: a. Cascade: First device on the PL JTAG interface chain. b. Independent: Single device on the EMIO JTAG interface chain. 10. User can access the TAP controller to configure PL: a.
Chapter 6: Boot and Configuration Note: This functionality is only supported on production silicon and requires for the system to be booted in independent JTAG boot mode. In this mode, the BootROM waits until the PL is self initialized, then enables the PS-PL level shifters, enables the PL JTAG interface, and issues the WFE instruction on the CPU.
Chapter 6: • • • • • Boot and Configuration Quad-SPI Boot ° Table 6-9: ° Table 6-10: Quad-SPI Boot MIO Register Settings Quad-SPI Boot Time Optimization Register Setting Examples NAND Boot ° Table 6-11: NAND Boot MIO Register Settings ° Table 6-12: NAND Boot Time Optimization Register Setting Example NOR Boot ° Table 6-13: NOR Boot MIO Register Settings ° Table 6-14: NOR Boot Time Optimization Register Setting Example SD Card Boot ° Table 6-15: SD Card Boot MIO Register Settings °
Chapter 6: Table 6-19: Boot and Configuration MIO Pin States for Reset, and Lockdown (Cont’d)Boot Mode (Cont’d) MIO Pin MIO pin [9:53] MIO_PIN Register Setting Pin State Reset Value Lockdown Value (1) I/O I/O Buffer (GPIOB) External Connection 0x1601 0x1601 I 3-state, Pull-up ~ Notes: 1. These register values are based on the VMODE [0, 1] strapping pins. The register values shown are for LVCMOS 25/33. For LVCMOS18, use: 0x1201 and 0x0201 (bits 11:9 change from 011 to 001 ). 6.3.
Chapter 6: Boot and Configuration • An update that was started on the first image but the system was interrupted after erasing the section requiring an update. • The write operation began but the write process did not finish. The BootROM Header search mechanism does not protect against: • The memory holding the BootROM Header becoming corrupt. • A complete header was written but it did not pass the tests. If a header is non-functional, this might lead to a system lockdown.
Chapter 6: Boot and Configuration Multiboot is shown in Figure 6-9 along with the BootROM Header search function.
Chapter 6: Boot and Configuration 6.3.12 BootROM Error Codes The BootROM can detect an error while processing the BootROM Header or while processing the FSBL/User code for decryption and authentication. When a boot failure occurs, the BootROM puts the device into either a secure or non-secure lockdown; an Error Code is normally generated. The BootROM flowchart with error conditions is shown in Figure 6-5. The error codes are listed in Table 6-20.
Chapter 6: Boot and Configuration Lockdown Types The Lockdown Type column includes information based on the type of reset that started the BootROM execution. • POR reset (P) • Non-POR reset (NP) The type of lockdown indicated in Table 6-20 includes the following notations: • Non-secure: A non-secure lockdown occurs (system can be accessed by JTAG). • Header: The lockdown type is defined by the Encryption Status parameter in the header.
Chapter 6: Table 6-20: Error Code Boot and Configuration BootROM Error Codes (Cont’d) Lockdown Type(1) Description Solution • Check that there is a valid image written within the boot partition address search space for the device, refer to the BootROM Header Search and Multiboot sections. 0x200D P: Non-secure NP: Previous NAND boot mode. The BootROM is unable to find a valid header within the image search range.
Chapter 6: Table 6-20: Error Code Boot and Configuration BootROM Error Codes (Cont’d) Lockdown Type(1) Description Solution 0x2102 P: Non-secure NP: Previous The address value in the Source Offset word points to a location within the BootROM Header instead of where the image is actually located. • Check the address value in the Source Offset word. 0x2103 P: Non-secure NP: Previous The address value in the Source Offset word is not aligned to a 64B boundary.
Chapter 6: Table 6-20: Error Code BootROM Error Codes (Cont’d) Lockdown Type(1) 0x2200 Boot and Configuration P: Secure NP: Previous Description Secure boot mode. The image size after decryption does fit into the 192 KB of available OCM memory. Solution • Reduce the size of the initial FSBL/User code that is loaded into the OCM. Notes: 1. There are two reset types, POR (P) and non-POR (NP). Refer to the text preceding the table for an explanation of the lockdown type column. 6.3.
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Chapter 6: Boot and Configuration If a failure occurs while booting in secure mode, the BootROM disables the AES unit, clears the OCM, clears the PL, and halts the processor. JTAG is not enabled, consequently, the REBOOT_STATUS value is not available to be read. Instead, the 16-bit error code is shown by toggling the INIT_B pin. 6.3.14 Registers Modified by the BootROM – Examples Examples of registers modified by the BootROM are listed in Table 6-22.
Chapter 6: Table 6-22: Boot and Configuration BootROM Modified Registers (Cont’d) Address Register Name(1) Reset Value JTAG Boot 0xF800_0258 REBOOT_STATUS (2) 0x00400000 0xF800_0910 OCM_CFG 0xF800_0A1C Quad-SPI Boot SD Card Boot 0x00400002 0x00400000 0x00600000 0x00400000 0x00600000 0x00000000 0x00000018 0x00000018 0x00000018 Reserved 0x00010101 0x00010101 0x00020202 0x00020202 0xF800_0B04 GIOB_CFG_CMOS18 0x00000000 0x0C301166 0x0C301166 0x0C301166 0xF800_0B08 GIOB_CFG_CMO
Chapter 6: Boot and Configuration 3. FSBL/User Code to Configure PS. Refer to UG821, Zynq-7000 All Programmable SoC Software Developers Guide for information on creating FSBL/User code. 4. FSBL/User Code to Initialize and Configure PL. The controls are shown in Figure 6-12. Refer to UG821, Zynq-7000 All Programmable SoC Software Developers Guide for information on creating FSBL/User code.
Chapter 6: Boot and Configuration Low until the [PCFG_PROG_B] bit is set High by the hardware. The programming sequence to initialize the PL include these steps: 1. Set [PCFG_PROG_B] signal to High 2. Set [PCFG_PROG_B] signal to Low 3. Poll the [PCAP_INIT] status for Reset 4. Set [PCFG_PROG_B] signal to High 5.
Chapter 6: Boot and Configuration PS Non-secure Bring-up Example The PS and PL can be brought up together in a secure or non-secure mode. The simultaneous bring-up of the PS and PL is shown in Figure 6-12. Also refer to Figure 6-4, page 163 for details on power, reset, and clock interactions and timing examples.The PS non-secure bring-up using a flash device without JTAG illustrates a simple example with minimal resources. The example is shown in Figure 6-14.
Chapter 6: Boot and Configuration b. Reads BootROM Header to determine encryption status and image destination. c. 4. Secure: Ensures PL is powered on to begin FSBL/User code decryption. BootROM prepares for the CPU to execute the FSBL/User code: a. Non-Secure: BootROM loads the FSBL/User code into OCM (or prepares for execute-in-place) on Quad-SPI and NOR devices. b.
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Chapter 6: Boot and Configuration 4. Check that there is room in the Command Queue. Verify devcfg.STATUS [DMA_CMD_Q_F] = 0. Note, this step is not necessary if the PL is in the initialized state. 5. Disable the PCAP loopback. Write a zero (0) to the devcfg.MCTRL [INT_PCAP_LPBK] bit. 6. Program the PCAP_2x clock divider. a. Secure Mode: Set devcfg.CTRL [QUARTER_PCAP_RATE_EN] bit = 1. b. Non-secure Mode: Clear [QUARTER_PCAP_RATE_EN] bit = 0. 7.
Chapter 6: Boot and Configuration The bridge supports both concurrent (bidirectional) and non-concurrent (unidirectional) download and upload of boot images. Transmit and receive FIFOs buffer data between the PS AXI Interconnect and the PCAP interface. For PCAP data, the bridge converts 32-bit AXI formatted data to the 32-bit PCAP protocol and vice versa. Non-secure bitstreams and boot images sent to the PCAP interface can be sent every PCAP clock cycle.
Chapter 6: Boot and Configuration 6.4.4 PCAP Datapath Configurations The PCAP bridge provides the FSBL/User code software with access to the PL configuration module and decryption unit. The configuration module processes the bitstream and loads the SRAM in the PL. The decryption unit is used to decrypt the bitstream and code files. The PL must be powered up to use the bridge. There are four common datapaths used with the PCAP bridge. The paths are illustrated in Figure 6-18 and Figure 6-19.
Chapter 6: Boot and Configuration triggered when both the AXI and PCAP interfaces are done. For all other DMA commands, the DMA done interrupt is set when the AXI transfers are done; however, there might still be on-going PCAP transfers. This distinction is made to allow overlapping AXI and PCAP transfers for all except the last DMA transfer.
Chapter 6: Boot and Configuration bitstream from the PCAP. The smallest amount of bitstream data that can be read back from the PL is one configuration frame which contains 101 32-bit words. An example program sequence is shown below. The datapath is illustrated in Figure 6-19. Example: PL Bitstream Readback This example shows the first DMA access for a PL bitstream readback: 1. DMA Source Address – location of PL readback command sequence. 2.
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Chapter 6: Table 6-23: Boot and Configuration PL Control and Status Register Bits (Cont’d) Bit Field Bit Type Description 29 RW Power-up Reset Timer Rate Select. Timer is used during PL initialization. 0: Use 64K timer. 1: Use 4K timer (faster initialization of reset stage). [PCFG_POR_B] 8 RO PL power on/off indicator: 0: power is off. 1: power is on. [INT_PCAP_LPBK] 4 RW PCAP Loopback: 0: disabled, 1: enabled. 4 RO PL initialization complete indicator: 0: not ready.
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Chapter 6: Boot and Configuration 6.5 Reference Section This section includes content on these topics: • Section 6.5.1 PL Configuration Considerations • Section 6.5.2 Boot Time Reference • Section 6.5.3 Register Overview • Section 6.5.4 PS Version and Device Revision 6.5.1 PL Configuration Considerations In master boot mode, the PL can be configured by PS software using the PCAP interface.
Chapter 6: Boot and Configuration Additional information about the PL power-up status can be obtained by reading the devcfg.STATUS [PSS_CFG_RESET_B] register bit. If the bit is Low, then the PL is in a reset state. A transition from a Low to a High indicates the start of the PL initialization process. PL Initialization Time Optimization The devcfg.
Chapter 6: Boot and Configuration • The Zynq-7000 device version (affects the PL initialization time and bitstream load time). • The size of the loaded images (e.g., Linux image size). IMPORTANT: The time it takes for each boot and configuration process to complete can be hard to calculate because of all the variables involved. The values provided here are meant as a guide, not a definitive answer. If you have any questions, please contact your Xilinx FAE Sales Engineer.
Chapter 6: Table 6-25: Boot and Configuration Factors that Affect Boot and Configuration Time (Cont’d) Functional Area CRC check of 128 KB ROM Description Boot Time Considerations This is an eFuse option that causes the BootROM to check the integrity of its own code at the beginning of execution. Requires about 26 ms to perform (PS_CLK frequency = 33 MHz). PL Hardware Functions PL Voltage Ramp This is power supply performance specification. A typical board might have a 10 ms voltage ramp time.
Chapter 6: Table 6-26: Function DevC status PCAPDMA Boot Boot and Configuration DevC and Boot Registers (Cont’d) Description Hardware Register Type Interrupt status: PL init, done, DMA/AXI errors devcfg.INT_STS R + Clr or W Interrupt mask devcfg.INT_MASK Read/Write Status: eFuse, Init, Lockdown, PS control, DevC DMA/FIFOs devcfg.STATUS Read-only DMA source address devcfg.DMA_SRC_ADDR Read/Write DMA destination address devcfg.DMA_DST_ADDR Read/Write DMA source length devcfg.
Chapter 7 Interrupts 7.1 Environment This chapter describes the system-level interrupt environment and the functions of the interrupt controller (see Figure 7-1). The PS is based on ARM architecture, utilizing one or two Cortex-A9 processors (CPUs) and the GIC pl390 interrupt controller. Note that single-core devices contain one Cortex-A9 processor (CPU), dual-core devices contain two. This chapter discusses the dual-core configuration.
Chapter 7: Interrupts 7.1.1 Private, Shared and Software Interrupts Each CPU has a set of private peripheral interrupts (PPIs) with private access using banked registers. The PPIs include the global timer, private watchdog timer, private timer, and FIQ/IRQ from the PL. Software generated interrupts (SGIs) are routed to one or both CPUs. The SGIs are generated by writing to the registers in the generic interrupt controller (GIC), refer to section 7.3 Register Overview.
Chapter 7: Interrupts X-Ref Target - Figure 7-2 Private Peripheral Interrupts (PPI) CPU 0 Timer and AWDT nIRQ nFIQ CPU 0 Distributor PL FIQ 0, IRQ 0 CPU 0 nIRQ nFIQ nIRQ nFIQ Interrupt Controller Distributor (ICD) SGI Distributor System Watchdog Timer Software Generated Interrupts (SGI) Shared Peripheral Interrupts (SPI) IOP CPU 0 Interface PL CPU 0 CPU 1 Private Peripheral Interrupts (PPI) CPU 1 Timer and AWDT CPU 1 Distributor nIRQ nFIQ nIRQ nFIQ CPU 1 Interface nIRQ nFIQ PL FIQ 1, I
Chapter 7: Interrupts X-Ref Target - Figure 7-3 mpcore.ICCICR [3,1:0] GIC Interrupt Distributors CPU x Interface IRQ / FIQ !0 IRQ / FIQ IRQ / FIQ Programmable Logic (PL) CPU0, IRQ: IRQF2P[16] CPU0, FIQ: IRQF2P[18] To CPU x 0 Pass-through Mux CPU1, IRQ: IRQF2P[17] CPU1, FIQ: IRQF2P[19] Note: There are separate ICCICR registers for each CPU.
Chapter 7: Interrupts All SGIs are edge triggered. The sensitivity types for SGIs are fixed and cannot be changed; the ICDICFR0 register is read-only, since it specifies the sensitivity types of all the 16 SGIs. Table 7-2: Software Generated Interrupts (SGI) IRQ ID# Name SGI# Type Description 0 Software 0 0 Rising edge 1 Software 1 1 Rising edge ~ ... ~ 15 Software 15 15 ...
Chapter 7: Interrupts For an interrupt of level sensitivity type, the requesting source must provide a mechanism for the interrupt handler to clear the interrupt after the interrupt has been acknowledged. This requirement applies to any IRQF2P[n] (from PL) with a high level sensitivity type. For an interrupt of rising edge sensitivity, the requesting source must provide a pulse wide enough for the GIC to catch. This is normally at least 2 CPU_2x3x periods.
Chapter 7: Interrupts Table 7-4: Source PS and PL Shared Peripheral Interrupts (SPI) (Cont’d) Interrupt Name IRQ ID# Status Bits Required Type PS-PL Signal Name (mpcore Registers) I/O Input PL [2:0] 63:61 spi_status_0[31:29] Rising edge/ High level IRQF2P[2:0] PL [7:3] 68:64 spi_status_1[4:0] Rising edge/ High level IRQF2P[7:3] Timer TTC 1 71:69 spi_status_1[7:5] High level ~ DMAC DMAC[7:4] 75:72 spi_status_1[11:8] High level IRQP2F[27:24] Output USB 1 76 spi_status_1[12] Hig
Chapter 7: Interrupts Table 7-4, PS and PL Shared Peripheral Interrupts (SPI). The sensitivity is programmed using the ICDICFR [5:2] registers. Private Peripheral Interrupts (PPI) Each CPU has its own separate PPI interrupts with fixed functionality; the sensitivity, handling, and targeting of these interrupts are not programmable. Each interrupt only goes to its own CPU and is handled by that CPU. The ICDICFR [1] register is read-only and the ICDIPTR [5:2] registers are essentially reserved.
Chapter 7: Interrupts X-Ref Target - Figure 7-5 IRQ # 3 IRQ # 7 IRQ # 11 IRQ # 15 ICD IPTR [3:0] SGI IRQ # 2 IRQ # 6 IRQ # 10 IRQ # 14 reserved 31 ICD IPTR [7:4] IRQ # 1 IRQ # 5 IRQ # 9 IRQ # 13 reserved IRQ # 0 IRQ # 4 IRQ # 8 IRQ # 12 reserved 24 16 reserved 8 0 00: not targeted 01: targeted to CPU 0 10: targeted to CPU 1 11: targeted to both CPUs Reserved, these interrupts are always targeted to their private CPU.
Chapter 7: Interrupts Table 7-5: Interrupt Controller Register Overview (Cont’d) Register Description Name Write Protection Lock ICCIAR Interrupt acknowledge ~ ICCEOIR End of interrupt ~ ICCRPR Running priority ~ ICCHPIR Highest pending interrupt ~ ICCABPR Aliased non-secure binary point ~ Interrupt Controller Distributor (ICD) ICDDCR Secure/non-secure mode select Yes ICDICTR, ICDIIDR Controller implementation ICDISR [2:0] Interrupt security ICDISER [2:0], ICDICER [2:0] Interrupt
Chapter 7: Interrupts Controller registers. The CFGSDISABLE bit can only be cleared by a power-on reset (POR.) After the CFGSDISABLE bit is set, it changes the protected register bits to read-only and therefore the behavior of these secure interrupts cannot be changed, even in the presence of rogue code executing in the secure domain. 7.4 Programming Model 7.4.1 Interrupt Prioritization All of the interrupt requests (PPI, SGI and SPI) are assigned a unique ID number.
Chapter 7: Interrupts 7.4.3 ARM Programming Topics The ARM GIC architecture specification includes these programming topics: • GIC register access • Distributor and CPU Interfaces • Affects of the GIC security extensions • PU Interface registers • Preserving and restoring controller state 7.4.
Chapter 8 Timers 8.1 Introduction Each Cortex-A9 processor has its own private 32-bit timer and 32-bit watchdog timer. Both processors share a global 64-bit timer. These timers are always clocked at 1/2 of the CPU frequency (CPU_3x2x). On the system level, there is a 24-bit watchdog timer and two 16-bit triple timer/counters. The system watchdog timer is clocked at 1/4 or 1/6 of the CPU frequency (CPU_1x), or can be clocked by an external signal from an MIO pin or from the PL.
Chapter 8: Timers 8.1.1 System Diagram The relationships of the system timers are shown in Figure 8-1. X-Ref Target - Figure 8-1 System Reset (POR) The System Watchdog Timer can optionally reset the whole chip. Clock in Reset Out The CPU Private WatchDogs can optionally reset the whole chip.
Chapter 8: Timers 8.2 CPU Private Timers and Watchdog Timers The CPU private timers and watchdog timers are fully documented in the Cortex-A9 MPCore Technical Requirements Document, sections 4.1 and 4.2 (see Appendix A, Additional Resources).
Chapter 8: Table 8-1: Timers CPU Private Timers Register Overview (Cont’d) Function Name Overview Reset status Watchdog Reset Status Reset status as a result of watchdog reaching 0. Cleared with POR only, so SW can tell if the reset was caused by watchdog. Disable Watchdog Disable Disable watchdog through a sequence of writes of two specific words. 8.3 Global Timer (GT) The Global Timer is fully documented in the Cortex-A9 MPCore Technical Requirements Document, sections 4.3 and 4.
Chapter 8: Timers 8.4 System Watchdog Timer (SWDT) In addition to the two CPU private watchdog timers, there is a system watchdog timer (SWDT) for signaling additional catastrophic system failure, such as a PS PLL failure. Unlike the AWDT, the SWDT can run off the clock from an external device or the PL, and provides a reset output to an external device or the PL. 8.4.
Chapter 8: Timers 8.4.2 Block Diagram A block diagram of the SWDT is shown in Figure 8-2. X-Ref Target - Figure 8-2 INTERCONNECT slcr.WDT_CLK_SEL[0] slcr.
Chapter 8: Timers The Status register shows whether the 24-bit counter reaches zero. Regardless of the WDEN bit in the Zero Mode register, the 24-bit counter always keeps counting down to zero if it is not zero and the selected clock source is present. Once it reaches zero, the WDZ bit of the Status register is set and remains set until the 24-bit counter is restarted. The prescaler block divides down the selected clock input. The CLKSEL signal is sampled at every rising clock edge.
Chapter 8: Timers 8.4.5 Programming Model System Watchdog Timer Enable Sequence 1. Select clock input source using the slcr.WDT_CLK_SEL[SEL] bit: Ensure that the SWDT is disabled (swdt.MODE[WDEN] = 0) and the clock input source to be selected is running before proceeding with this step. Changing the clock input source when the SWDT is enabled results in unpredictable behavior. Changing the clock input source to a non-running clock results in APB access hang. 2.
Chapter 8: Timers 8.5 Triple Timer Counters (TTC) The TTC contains three independent timers/counters. There are two TTC modules in the PS, for a total of six timers/counters. TTC 1 controller can be configured for secure or non-secure mode using the nic301_addr_region_ctrl_registers.security_apb [ttc1_apb] register bit. The three timers within a TTC controller have the same security state. 8.5.
Chapter 8: Timers X-Ref Target - Figure 8-3 slcr.MIO_PIN_xx Timer/Clock 0 Wave-Out 16-bit Counter Pre-scaler CPU_1x MIO EMIO Interrupt MIO Clock-In Interrupt (GIC) TTC_0: IRQ ID # 42 TTC_1: IRQ ID # 69 Event Timer EMIO Timer/Clock 1 slcr.MIO_PIN_xx .
Chapter 8: Timers Overflow mode: The counter increments or decrements continuously between 0 and 0xFFFF, with the direction of counting determined by the DEC bit of the Counter Control register. An overflow interrupt is generated when the counter passes through zero. The corresponding match interrupt is generated when the counter value equals one of the Match registers.
Chapter 8: Table 8-4: Triple Timer Counter Register Overview (Cont’d) Function Counter Control Interrupt Event Timers Name Overview Interval register Sets interval value Match register 1 Match register 2 Match register 3 Sets match values, total 3 Interrupt register Shows current interrupt status Interrupt Enable register Enable interrupts Event Control Timer register Enable event timer, stop timer, sets phrase Event register Shows width of external pulse 8.5.
Chapter 8: Timers 2. Set overflow handling, select external pulse level, enable the event timer (Event Control Timer register). This step starts measuring the width of the selected level (High or Low) of the external pulse. 3. Enable interrupt (Interrupt Enable register). This step is optional, if interrupt is to be enabled. 4. Read the measured width (Event register). Note that the returned value is not correct when overflow happened.
Chapter 8: Timers 8.6 I/O Signals Timer I/O signals are identified in Table 8-5. The MIO pins and any restrictions based on device version are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. There are two triple timer counters (TTC0 and TTC1) in the system. Each TTC has three sets of interface signals: clock in and wave out for counter/timers 0, 1, and 2. For each triple timer counter, the signals for counter/timer 0 can be routed to the MIO using the MIO_PIN registers.
Chapter 9 DMA Controller 9.1 Introduction The DMA controller (DMAC) uses a 64-bit AXI master interface operating at the CPU_2x clock rate to perform DMA data transfers to/from system memories and PL peripherals. The transfers are controlled by the DMA instruction execution engine. The DMA engine runs on a small instruction set that provides a flexible method of specifying DMA transfers. This method provides greater flexibility than the capabilities of DMA controller methods.
Chapter 9: DMA Controller 9.1.
Chapter 9: DMA Controller 9.1.2 System Viewpoint The system viewpoint of the DMA controller is shown in Figure 9-1.
Chapter 9: DMA Controller 9.1.3 Block Diagram The block diagram of the DMA controller is shown in Figure 9-2.
Chapter 9: DMA Controller Instruction Cache The controller stores instructions temporarily in a cache. When a thread requests an instruction from an address, the cache performs a look-up. If a cache hit occurs then the cache immediately provides the data, otherwise the thread is stalled while the controller uses the AXI interface to perform a cache line fill from system memory.
Chapter 9: DMA Controller DMA itself. The request/acknowledge signals to and from the PL are described in section 9.2.6 PL Peripheral AXI Transactions. Reset Initialization Interface This interface enables the software to initialize the operating state of the DMAC as it exits from reset. Refer to section 9.6.3 Reset Configuration of Controller for more information. 9.1.
Chapter 9: DMA Controller 9.2 Functional Description Common to all DMAC operating conditions • 9.2.1 DMA Transfers on the AXI Interconnect • 9.2.2 AXI Transaction Considerations • 9.2.3 DMA Manager • 9.2.4 Multi-channel Data FIFO (MFIFO) Memory-to-memory transfers are managed by the DMAC • 9.2.5 Memory-to-Memory Transfers When the PL Peripheral Request Interface is used • 9.2.6 PL Peripheral AXI Transactions • Length management option: 9.2.
Chapter 9: DMA Controller 9.2.1 DMA Transfers on the AXI Interconnect All of the DMA transactions use AXI interfaces to move data between the on-chip memory, DDR memory and slave peripherals in the PL. The slave peripherals in the PL normally connect to the DMAC peripheral request interface to control data flow. The DMAC can conceivable access IOPs in the PS, but this is normally not useful because these paths offer no flow control signals.
Chapter 9: DMA Controller X-Ref Target - Figure 9-3 DMA Controller PL Memory (Read and Write) On-Chip RAM (Read and Write) DDR Memory (Read and Write) 64-bit IOP Masters M S0 AXI_GP, DevC and DAP S2 S1 Central Interconnect M0 64-bit M1 M2 AXI_HP Memory Interconnect L2 Cache S1 S0 OCM Interconnect M 64-bit S1 S0 Slave Interconnect 32-bit SCU M0 S0 64-bit -bit AXI_GP0 AXI_GP1 AHB slaves PL AXI_HP Memory Interconnect S3 M2 M3 S1 On-chip RAM 256 KB M1 APB slaves L2 Cache
Chapter 9: DMA Controller 9.2.2 AXI Transaction Considerations • • AXI data transfer size ° Performs data accesses up to the 64-bit width of the AXI data bus ° Signals a precise abort if the user programs the src_burst_size or dst_burst_size fields to be larger than 64 bits ° Maximum burst length is 16 data beats AXI bursts crossing 4 KB boundaries ° ° • • Can be programmed to generate only fixed-address or incrementing-address burst types for data accesses.
Chapter 9: DMA Controller The appropriate APB interface must be used depending on the security state in which the SLCR register TZ_DMA_NS initializes the DMA manager to operate. For example, if the DMA manager is in the secure state, the instruction using the secure APB interface must be used or the DMAC ignores the instruction.
Chapter 9: DMA Controller 9.2.4 Multi-channel Data FIFO (MFIFO) The MFIFO is a shared resource utilized on a first-come, first-served basis by all currently active channels. To a program, it appears as a set of variable-depth parallel FIFOs, one per channel, with the restriction that the total depth of all the FIFOs cannot exceed the size of the MFIFO. The DMAC maximum MFIFO depth is 128 (64-bit) words. The controller is capable of realigning data from the source to the destination.
Chapter 9: DMA Controller The memory map for the DMA controller is shown in Chapter 4, System Addresses. For more information on the AXI Interfaces, refer to . Examples of memory-to-memory transfer are provided in section 9.4.2 Memory-to-Memory Transfers. 9.2.6 PL Peripheral AXI Transactions The majority of PL peripherals allow transferring data through FIFOs. These FIFOs must be managed to avoid overflow and underflow situations.
Chapter 9: DMA Controller X-Ref Target - Figure 9-4 DMA{3:0}_DRVALID DMA{3:0}_DRTYPE[1:0] DMA{3:0}_DRLAST DMA{3:0}_DRREADY Peripheral {3:0} DMA{3:0}_DAVALID DMA{3:0}_DATYPE[1:0] Peripheral Request Interface {3:0} DMAC DMA{3:0}_DAREADY DMA{3:0}_ACLK UG585_c9_05_030312 Figure 9-4: DMAC PL Peripheral Request Interface Request/Acknowledge Signals Both buses use the valid-ready handshake that the AXI protocol describes.
Chapter 9: Table 9-1: DMA Controller DMAC PL Peripheral Request Interface Handshake Rules (Cont’d) Description(1) Rule 3 DMA{3:0}_DRLAST can only change when either: • DMA{3:0}_DRREADY is High • DMA{3:0}_DRVALID is Low 4 DMA{3:0}_DAVALID can change from Low to High on any DMA{3:0}_ACLK cycle, but must only change from High to Low when DMA{3:0}_DAREADY is High 5 DMA{3:0}_DATYPE can only change when either: • DMA{3:0}_DAREADY is High • DMA{3:0}_DAVALID is Low Notes: 1.
Chapter 9: T7 DMA Controller The DMAC sets DMA{3:0}_DAVALID High and sets DMA{3:0}_DATYPE[1:0] to indicate that the transaction is complete. For more timing diagrams refer to ARM PrimeCell DMA Controller (PL330) Technical Reference Manual: Peripheral Request Interface Timing Diagrams, keeping in mind that each PL peripheral request interface is asynchronous to one another and asynchronous to the DMA itself. 9.2.
Chapter 9: DMA Controller DMALDP, DMASTP The DMAC executes a DMANOP if the request_type flag does not match the B|S suffix. DMALPEND When the nf bit is 0, the DMAC executes a DMANOP if the request_last flag is set. The DMALDB, DMALDPB, DMASTB and DMASTPB instructions should be used if the DMAC is required to issue an AXI burst transaction when the DMAC receives a burst request, that is, when DMA{3:0}_DRTYPE[1:0] = b01.
Chapter 9: DMA Controller The DMAWFP burst instruction should be used when the program thread is required to halt execution until the PL peripheral request interface receives a burst request. If the head entry request type in the request FIFO is: Single: The DMAC removes the entry from the FIFO and program execution remains halted. Burst: The DMAC pops the entry from the FIFO and continues program execution.
Chapter 9: • DMA Controller If the INTEN register sets the event/interrupt resource to function as an interrupt, the DMAC sets irq High, where event_num is the number of the specified event-resource. To clear the interrupt, the user must write to the INTCLR register. Refer to the Interrupt Clear register in Appendix B, Register Details. Refer to section 9.3 Programming Guide for DMA Controller for more information and Chapter 7, Interrupts for more details about the System IRQs. 9.2.
Chapter 9: Table 9-3: DMA Controller DMAC Abort Types and Conditions (Cont’d) Abort Types Condition Error on Data Load The DMAC receives an ERROR response on the AXI master interface when it performs a data load. Error on Data Store The DMAC receives an ERROR response on the AXI master interface when it performs a data store.
Chapter 9: Table 9-5: DMA Controller DMAC Thread Termination (Cont’d) Processor or PL Peripheral Actions Programs the Debug Instruction-0 register with the encoding for the DMAKILL instruction Writes to the Debug Command register. 9.2.
Chapter 9: Table 9-6: DMA Controller DMAC Security Nomenclature (Cont’d) ARM Name XILINX Name ns ns in DMAGO instruction Description DMAGO Non-secure Bit 1 of the DMAGO instruction: 0: DMA channel thread starts in the secure state 1: DMA channel thread starts in the secure state CHANNEL Non-secure CNS CNS in CSR The security state of each DMA channel is provided by bit CNS in the Channel Status register: 0: DMA channel thread operates in the secure state 1: DMA channel thread operates in the
Chapter 9: DMA Controller Security by DMA Channel Thread A quick summary of the security usage for the DMA Channel Threads is given in Table 9-8.
Chapter 9: Table 9-9: DMA Controller DMAC IP Configuration Options (Cont’d) Value IP Configuration Option Write queue depth 16 Read issuing capability 8 Write issuing capability 8 Peripheral request capabilities All capabilities Secure APB base address 0xF800_3000 Non-secure APB base address 0xF800_4000 9.3 Programming Guide for DMA Controller 9.3.1 Startup Example: Start-up Controller 1. Configure Clocks. Refer to section 9.6.1 Clocks 2. Configure Security State. Refer to section 9.6.
Chapter 9: DMA Controller Example: IRQ Interrupt Service Routine The following steps need to be performed in this routine. This routine can support all 8 DMAC IRQs. 1. Check which event has caused the interrupt. Read dmac.INT_EVENT_RIS. 2. Clear the corresponding event. Write to the dmac.INTCLR register. 3. Inform the application that the DMA transfer has finished. Call the user callback function if registered during DMA transfer setup.
Chapter 9: Table 9-10: DMA Controller DMAC Register Overview (Cont’d) Function Register Name Overview Fault Status and Type dmac.FSRD dmac.FSRC dmac.FTRD dmac.FTR{7:0} Provides the fault status and type for the manager and the channels. Channel Thread Status dmac.CPC{7:0} dmac.CSR{7:0} dmac.SAR{7:0} dmac.DAR{7:0} dmac.CCR{7:0} dmac.LC0_{7:0} dmac.LC1_{7:0} These registers provide the status of the DMA channel threads. Debug dmac.DBGSTATUS dmac.DBGCMD dmac.
Chapter 9: DMA Controller 9.4.1 Write Microcode to Program CCRx for AXI Transactions The channel microcode is used to set the dmac.CCRx registers to define the attributes of the AXI transactions. This is done using the DMAMOV CCR instruction. The user should program the microcode to write to the dmac.CCR{7:0} register before it initiates a DMA transfer. Here are the AXI attributes that the microcode writes: 1.
Chapter 9: Table 9-11: DMA Controller DMAC Aligned Memory-to-Memory Transfers Description Code MFIFO Usage Simple Aligned Program In this program the source address and destination address are aligned with the AXI data bus width. DMAMOV CCR, SB4 SS64 DB4 DS64 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4000 Each DMALD requires four entries and each DMAST removes four entries. This example has a static requirement of zero MFIFO entries and a dynamic requirement of four MFIFO entries.
Chapter 9: Table 9-12: DMA Controller DMAC Unaligned Transfers Description Code MFIFO Usage Aligned source address to unaligned destination address In this program, the source address is aligned with the AXI data bus width but the destination address is unaligned. The destination address is not aligned to the destination burst size so the first DMAST instruction removes less data than the first DMALD instruction reads.
Chapter 9: Table 9-12: DMA Controller DMAC Unaligned Transfers (Cont’d) Description Code MFIFO Usage Unaligned source address to aligned destination address, with excess initial load This program is an alternative to that described in unaligned source address to aligned destination address. The program uses a different sequence of source bursts which might be less efficient but requires fewer MFIFO entries.
Chapter 9: DMA Controller 9.4.3 PL Peripheral DMA Transfer Length Management Example: Length Managed by Peripheral The following example shows a DMAC program that transfers 64 words from memory to peripheral 0 when the peripheral sends a burst request (DMA{3:0}_DRTYPE[1:0] = 01). When the peripheral sends a single request (DMA{3:0}_DRTYPE[1:0] = 00) then the DMAC program transfers one word from memory to peripheral 0.
Chapter 9: DMA Controller DMALDS DMASTPS P0 # Exit loop if DMAC receives the last request, that is, drlast_0 = 1 DMALPEND DMAEND Example: Length Managed by DMAC This example shows a DMAC program that can transfer 1,027 words when a peripheral signals 16 consecutive burst requests and 3 consecutive single requests. # Set up for AXI burst transfer # (4-beat burst, so SB4 and DB4), (word data width, so SS32 and DS32) DMAMOV CCR SB4 SS32 DB4 DS32 DMAMOV SAR ... DMAMOV DAR ...
Chapter 9: DMA Controller DMASTPS P0 # Finish single loop DMALPEND # Flush the peripheral, in case the single transfers were in response # to a burst request DMAFLUSHP 0 DMAEND 9.4.4 Restart Channel using an Event When the INTEN register is programmed to generate an event, the DMASEV and DMAWFE instructions can be used to restart one or more DMA channels. Refer to the Interrupt Enable register in Appendix B, Register Details.
Chapter 9: 4. DMA Controller The DMAC halts execution of the channel 3 thread and the thread stalls while it waits for the next occurrence of event 6. 9.4.5 Interrupting a Processor The controller provides the seven active-High sensitive interrupts (IRQ ID #75:72 and 49:46) to the CPUs via the interrupt controller (GIC). When the INTEN register is programmed to generate an interrupt, after the DMAC executes DMASEV, the controller sets the corresponding interrupt to an active High state.
Chapter 9: Table 9-14: DMA Engine Instruction Summary (Cont’d) Instruction Mnemonic Thread Usage: M = DMA Manager C = DMA Channel Kill DMAKILL M C Load DMALD - C Load and Notify Peripheral DMALDP - C Loop DMALP - C Loop End DMALPEND - C Loop Forever DMALPFE - C Move DMAMOV - C No operation DMANOP M C Read memory Barrier DMARMB - C Send Event DMASEV M C Store DMAST - C Store and Notify Peripheral DMASTP - C Store Zero DMASTZ - C Wait For Event DMAWFE
Chapter 9: • DMA Controller Full MFIFO causes DMAC watchdog to abort a DMA channel (section, below, titled Resource sharing between DMA channels) The following sections describe these last two restrictions in detail. 9.5.
Chapter 9: • DMA Controller SARn register so that it modifies the source byte lane alignment. For example, when the bus width is 32 bits and bits [1:0] in the SARn register are changed. When a discontinuity in the source datastream occurs, the DMAC: 1. Halts execution of the DMA channel thread. 2. Completes all outstanding read operations for the channel (just as if the DMAC was executing DMARMB instruction). 3. Resumes execution of the DMA channel thread. No data is discarded from the MFIFO.
Chapter 9: DMA Controller To avoid DMAC lock-up, the total MFIFO requirement of the set of channel programs must be equal to or less than the maximum MFIFO depth. The DMAC maximum MFIFO depth is 1 words, 64 bits each. 9.6 System Functions 9.6.1 Clocks The controller is clocked by the CPU_1x clock for the APB interface and by the CPU_2x clock on the AXI interface. Programming information for the CPU_1x and CPU_2x clocks is in Chapter 25, Clocks. Example: Enable Clocks 1. Enable CPU_1x clock for APB.
Chapter 9: Table 9-16: DMA Controller DMAC Initialization Signals Name boot_manager_ns boot_irq_ns[15:0] boot_periph_ns[3:0] boot_addr[31:0] boot_from_pc Type Input Input Input Source Description SLCR register TZ_DMA_NS Controls the security state of the DMA manager, when the DMAC exits from reset: 0: Assigns DMA manager to the secure state 1: Assigns DMA manager to the non-secure state SLCR register TZ_DMA_IRQ_NS Controls the security state of an event-interrupt resource, when the DMAC exi
Chapter 9: Table 9-17: DMA Controller DMAC PL Peripheral Request Interface Signals Type Clock DMA Request I/O Name Description I DMA{3:0}_ACLK Clock for DMA request transfers I DMA{3:0}_DRVALID Indicates when the peripheral provides valid control information: 0: No control information is available 1: DMA{3:0}_DRTYPE[1:0] and DMA{3:0}_DRLAST contain valid information for the DMAC I DMA{3:0}_DRLAST Indicates that the peripheral is sending the last AXI data transaction for the current DMA tran
Chapter 10 DDR Memory Controller 10.1 Introduction The DDR memory controller supports DDR2, DDR3, DDR3L, and LPDDR2 devices and consists of three major blocks: an AXI memory port interface (DDRI), a core controller with transaction scheduler (DDRC) and a controller with digital PHY (DDRP). The DDRI block interfaces with four 64-bit synchronous AXI interfaces to serve multiple AXI masters simultaneously. Each AXI interface has its own dedicated transaction FIFO.
Chapter 10: DDR Memory Controller 10.1.
Chapter 10: DDR Memory Controller • Efficient transaction scheduling to optimize data bandwidth and latency • Advanced re-ordering engine to maximize memory access efficiency for continuous reads and writes as well as random reads and writes • Write - read address collision detection to avoid data corruption • Obeys AXI ordering rules 10.1.2 Block Diagram The block diagram for the DDR memory controller is shown in Figure 10-1.
Chapter 10: DDR Memory Controller 10.1.3 Notices 7z007s and 7z010 CLG225 Devices All devices support the 32- and 16-bit data bus width options except the 7z007s single core and 7z010 dual core CLG225 devices. These CLG225 devices only support the 16-bit data bus width, not the 32-bit bus. 10.1.4 Interconnect The four AXI_HP interfaces are multiplexed down, in pairs, and are connected to ports 2 and 3 as shown in Figure 10-2. These ports are commonly configured for high bandwidth traffic.
Chapter 10: DDR Memory Controller 10.1.5 DDR Memory Types, Densities, and Data Widths The DDR memory controller is able to connect to devices under the conditions identified in Table 10-1.
Chapter 10: • slcr.DDRIOB_DRIVE_SLEW_DATA • slcr.DDRIOB_DRIVE_SLEW_DIFF • slcr.DDRIOB_DRIVE_SLEW_CLOCK DDR Memory Controller The input Vref settings are controlled by slcr.DDRIOB_DDR_CTRL. The DDR DCI settings are controlled by slcr.DDRIOB_DCI_CTRL. Note: The 7z010 dual core and 7z007s single core CLG225 devices only support a 16-bit data bus width, not a 32-bit bus width.
Chapter 10: DDR Memory Controller 10.2 AXI Memory Port Interface (DDRI) 10.2.1 Introduction Each AXI master port has an associated slave port in the arbiter. The command FIFO located inside the port stores the address, length and ID contained in the command. The RAM in the write port stores the write data and byte enable. The RAM in the read port stores the read data coming back from the core. Because the read data coming back from the core can come out of order, the RAM is used for data re-ordering.
Chapter 10: DDR Memory Controller 10.2.2 Block Diagram The block diagram of the DDRI is shown in Figure 10-3.
Chapter 10: DDR Memory Controller 10.2.4 TrustZone The DDR memory can be configured in 64 MB sections. Each section can be configured to be either secure or non-secure. This configuration is provided via a system level control register. • A 0 on a particular bit indicates a secure memory region for that particular memory segment. • A 1 on a particular bit indicates a non-secure memory region for that particular memory segment.
Chapter 10: DDR Memory Controller 10.3.1 Row/Bank/Column Address Mapping The DDRC is responsible for mapping byte-addressable physical addresses used by the PS and PL AXI masters to DDR row, bank and column addresses. This address mapping has a limited configurability to allow user optimization. Optimizing the mapping to specific data access patterns can allow increased DDR utilization by reducing page and row change overhead.
Chapter 10: DDR Memory Controller X-Ref Target - Figure 10-5 Stage 1 Read Stage 1 Write Stage 2 Queue to DDR PHY Stage 3 Transaction Scheduler UG585_c10_05_032012 Figure 10-5: DDRC Arbitration 10.4.1 Priority, Aging Counter and Urgent Signals DDR controller arbitration is based on round robin with aging. The round robin mechanism circularly scans all requesting devices and services all outstanding requests before servicing the same device again.
Chapter 10: DDR Memory Controller The page size is defined by PAGE_MASK (32 bit register that all bits are the mask) and is always address aligned. For proper operation, the software must program the page size in the PAGE_MASK to match the size of the DDR memory. Setting this register to 0 disables the page-match step of the arbitration. 10.4.3 Aging Counter When a request is pending and not serviced, a decrementing aging counter is enabled.
Chapter 10: DDR Memory Controller X-Ref Target - Figure 10-6 Aging Counter 0 Aging Counter 1 Aging Counter 2 Aging Counter 3 T Is 0? Winner F Page Match? T Winner F Lowest Priority Winner Tie 0 3 1 Round Robin Winner 2 UG585_c10_06_050212 Figure 10-6: Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 Stage 1 – AXI Port Arbitration www.xilinx.
Chapter 10: DDR Memory Controller 10.4.5 Stage 2 – Read Versus Write The reads and the writes each have a queue in the DDR Core. The entries in these queues then vie for the next level of arbitration, shown in Figure 10-7.
Chapter 10: DDR Memory Controller X-Ref Target - Figure 10-8 DDR PHY Optimization Algorithms DDR Core Transaction Scheduler Pending DDR Transactions DDR Interface DRAM R/W State Open Bank State Sequencer Stage 3 AXI Port Arbiter Reads Read Arbiter Write Arbiter Port Priority Select HPR Read Request LPR Stage 1 Stage 2 Write Request Writes DDR DRAM Device(s) Self-Coherent and with DDR UG585_c10_08_032012 Figure 10-8: Read Queue This can be changed by setting the reg_arb_set_hpr_rd_p
Chapter 10: DDR Memory Controller X-Ref Target - Figure 10-9 Read, No Critical Write Read Mode Critical Read OR Read and No Write Critical Write OR Write and No Read Write Mode Write, No Critical Read UG585_c10_09_032012 Figure 10-9: Stage 3 – Transaction State The transaction state stays the same until the other type of transaction is critical or there is no more of that type of transaction. The state machine defaults to the read state.
Chapter 10: DDR Memory Controller Inside the controller, assertion of this signal causes the state machine to switch from one state to another. For example, if the DDRC is currently servicing reads and co_gs_go2critical_wr goes High, the controller ignores the normal state switching methods (starvation counter etc), and jumps to servicing writes.
Chapter 10: DDR Memory Controller 10.4.10 Credit Mechanism The DRAM controller employs a credit mechanism to ensure that buffers do not overflow (pending DDR transactions). The interface making the request to the controller can only request commands for which it has been granted credits or open slots in the queues to issue.
Chapter 10: DDR Memory Controller 10.6 Initialization and Calibration To start operation of the PS DRAM interface, the following sequence of operations must take place: 1. DDR clock initialization 2. DDR I/O buffers (DDR IOB) initialization and calibration 3. DDR controller (DDRC) register programming 4. DRAM reset and initialization 5. DRAM input impedance (ODT) calibration 6. DRAM output impedance (Ron) calibration 7. DRAM Training a. Write leveling b. Read DQS gate training c.
Chapter 10: DDR Memory Controller Programming the DDR clock involves the DDR_PLL_CTRL and DDR_CLK_CTRL registers in the SLCR. Please refer to section 25.10.4 PLLs in Chapter 25, for DDR PLL programming. In addition to the main DDR clock, a 10 MHz clock is used by the digitally controlled impedance (DCI) function built into the DDR IOB. This clock is configured via the SLCR DCI_CLK_CTRL register. 10.6.
Chapter 10: DDR Memory Controller 10.6.3 DDR IOB Configuration The DDR IOBs must be configured to function as I/O. Each type of DDR IOB is controlled by two different SLCR configuration registers. The configuration registers configure the IOB's input mode, output mode, DCI mode, and other functions. Configuration The DDR system supports DDR3L/DDR3/DDR2/LPDDR2 in 16 and 32 bit modes and power down modes.
Chapter 10: DDR Memory Controller 4. Set TERM_DISABLE_MODE and IBUF_DISABLE_MODE to enable power saving input modes. The TERM_DISABLE_MODE and IBUF_DISABLE_MODE fields should not be set before DDR training has completed. 5. Set INP_TYPE to VREF based differential receiver for SSTL, HSTL for single ended inputs. 6. Set INP_TYPE to Differential input receiver for differential inputs. 7. Set TERM_EN to enabled for DDR3/DDR32L and DDR2 bidirectional I/Os (Outputs and LPRDDR2 IOs are not terminated).
Chapter 10: DDR Memory Controller 10.6.5 DRAM Reset and Initialization The DDRC performs DRAM reset and initialization per the JEDEC specs, including reset, refresh, and mode registers initialization. 10.6.6 DRAM Input Impedance (ODT) Calibration The DRAM mode and extended mode set commands are controlled by the ddrc.DRAM_EMR_MR_reg and ddrc.DRAM_EMR_reg registers. The encoding for these registers can be found in DRAM device data sheets or JEDEC specifications.
Chapter 10: DDR Memory Controller 10.6.7 DRAM Output Impedance (RON) Calibration DRAM device MR/EMR registers are controlled via the ddrc.DRAM_EMR_MR_reg and ddrc.DRAM_EMR_reg registers. MR/EMR encodings can be found in DRAM device data sheets or JEDEC specifications. The output impedance control feature is available in DDR2, DDR3/DDR3L and LPDDR2 devices. • In DDR2 devices, the value is controlled via the mode register EMR, and can be set to full strength or reduced strength.
Chapter 10: DDR Memory Controller Training time is on the order of 1-2 ms at a 500 MHz DRAM clock. Note: For training to be successful, all of the data signals need to be connected to the DRAM device(s) even when ECC is used (16-bit data, 10-bit ECC). Write Leveling Goal Adjust WR DQS relative to CLK Desired Nominal DQS aligned with clock (0 phase offset) Final Ratio Equal to the DQS to CLK board delay at the DRAM Initial Ratio Final value minus 0.5 cycle. If < 0 set to 0.
Chapter 10: DDR Memory Controller The DDRC supports read DQS gate training as part of the initialization procedure. Optionally, training can be disabled and pre-determined delay values can be programmed via registers (required for DDR2, where read training is not supported). Note that when using LPDDR2, with read gate training, automatic training is not recommended. Instead, the following procedure is recommended (Xilinx tools implement this flow): 1.
Chapter 10: DDR Memory Controller across PVT is slightly less than 90 degrees, and will be automatically provided by Vivado Design Suite for inclusion into the FSBL or other user code. 10.6.10 Alternatives to Automatic DRAM Training If for some reason the automatic training is not successful, alternative calibration schemes can also be used. TIP: Training failures can be detected by performing a simple memory write-read-compare test.
Chapter 10: DDR Memory Controller As final parameters, pick the values that are in the center of the successful tests region. Note that each data byte lane (aka data slice) has its own independent parameters, and should be tested independently in the memory tests. The estimated time for a training iteration is 1-2 ms plus the duration of the memory test. Assuming a simple 1,000 word read-write test and an average access time of 30 cycles, test duration is on the order of 60,000 cycles or about 0.
Chapter 10: DDR Memory Controller Table 10-9 provides summary of register values involved in manual training. All values are in units of 1/256 of a clock cycles (256 units = 1 clock cycle, 8 units = 1/32 of a clock cycle).
Chapter 10: Table 10-10: DDRI Registers Overview Function Register Name Arbitration Misc DDR Memory Controller Description page_mask Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Sets the column address bits to 0. Sets the page and bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address.
Chapter 10: Table 10-11: Function DDRI Registers Overview (Cont’d) Hardware Register Name Dynamic Bit Fields CHE_REFRESH_TIMER01 DDR Refresh DDR Init ~ CHE_T_ZQ [16]: dis_auto_refresh Power Reduction ECC Description Reserved ZQ parameters CHE_T_ZQ_Short_Interval_Reg ~ Misc parameters DRAM_init_param ~ DRAM initialization parameters DRAM_EMR_reg ~ DRAM EMR2, EMR3 access DRAM_EMR_MR_reg ~ DRAM EMR, MR access DRAM_burst8_rdwr ~ DRAM burst 8 read/write DRAM_disable_dq Address Mapping
Chapter 10: DDR Memory Controller 10.7.3 DDRP Table 10-12 shows an overview of DDRP registers.
Chapter 10: DDR Memory Controller 10.8 Error Correction Code (ECC) There is optional ECC support in half-bus width (16-bit) data width configuration only. Externally 26 bits of a DRAM DDR device are required, 16-bits for data and 10 bits for ECC. Each data byte uses an independent 5-bit ECC field. This mode provides single error correction and dual error detection. The ECC bits are interlaced with the data bits and unused bits as shown in Table 10-13.
Chapter 10: DDR Memory Controller • Sends the corrected data to the core as part of the read data. • Sends the ECC error information to the register interface for logging. • Performs a RMW operation to correct the data present in the DRAM (only if ECC scrubbing is enabled (reg_ddrc_dis_scrub = 0). This RMW operation is invisible to the core. Only one scrub RMW command can be outstanding in the controller at any time.
Chapter 10: 5. DDR Memory Controller Program the reg_ddrc_soft_rstb to 1 (takes the controller out of reset) Monitoring ECC Status 1. CHE_CORR_ECC_ADDR_REG_OFFSET gives the bank/row/column information of the ECC error correction 2. CHE_UNCORR_ECC_ADDR_REG_OFFSET gives the bank/row/column information of the ECC unrecoverable error 3. B[0] of CHE_CORR_ECC_LOG_REG_OFFSET indicates correctable ECC status 4. B[0] of CHE_UNCORR_ECC_LOG_REG_OFFSET indicates uncorrectable ECC status 5.
Chapter 10: DDR Memory Controller 5. Assert reg_ddrc_soft_rstb to reset the controller. When the controller is taken out of reset, it re-initializes the DRAM. During initialization, the mode register values updated in step 4 are written to DRAM. Anytime after de-asserting reset, go to step 6. 6. Take the controller out of self refresh by de-asserting reg_ddrc_selfref_en. Note: This sequence can be followed in general for changing DDRC settings, in addition to just clock frequencies.
Chapter 10: DDR Memory Controller 10.9.6 DDR Power Reduction Clock Stop When this feature is enabled, the DDR PHY is allowed to stop the clocks going to the DRAM. For DDR2 and DDR3/DDR3L this feature is effective in self refresh mode only.
Chapter 11 Static Memory Controller 11.1 Introduction The static memory controller (SMC) can be used either as a NAND flash controller or a parallel port memory controller supporting the following memory types: • NAND flash • Asynchronous SRAM • NOR flash System bus masters can access the SMC controller as shown in Figure 11-1. The operational registers of the SMC are configured through an APB interface. The memory mapping for the SMC is described in Chapter 4, System Addresses.
Chapter 11: Static Memory Controller 11.1.1 Features Features of the SMC are listed for each type of memory. The controller is configured to operate in one of two interface modes. NAND Flash Interface • ONFI Specification 1.
Chapter 11: Static Memory Controller 11.1.2 Block Diagram The block diagram for the SMC is shown in Figure 11-2.
Chapter 11: Static Memory Controller 11.1.3 Notices 7z007s and 7z010 CLG225 Devices The 7z007s single core 7z010 dual core CLG225 devices do not support the NOR/SRAM interface. The NAND interface is supported in the 8-bit interface, but not the 16-bit interface. MIO Pin Options MIO Pin 1 can be programmed to be CS1 or address bit 25 for the NOR/SRAM controller. This pin can also be programmed as a GPIO. Programming is controlled by the slcr.MIO_PIN_01 register.
Chapter 11: Static Memory Controller TIP: For power management, the clock enable in the slcr register can be used to turn off the clock. The operating frequency for the reference clock is defined in the data sheet. (Clock gating is used to stop the clock to save power.) Table 11-2: SMC Clocks and Resets Clock Resets Clock Domain Description CPU_1x CPU_1x Interconnect domain This clock runs at 1/6th or 1/4th the CPU clock rate depending on the CPU clock mode.
Chapter 11: Static Memory Controller 11.2.6 PL353 Functionality The SMC is based on ARM's PL353 Primecell core and is hard-coded such that controller 0 can operate in SRAM/NOR mode and controller 1 can operate in NAND flash mode. The SRAM/NOR or NAND interface can be used in a system, but not both. The SRAM/NOR interface does not support PSRAM. The NAND flash controller does not support wear leveling.
Chapter 11: Table 11-5: MIO Pin Static Memory Controller SMC MIO Pins SRAM/NOR Interface Mode Signal Name Default I/O Value Description MIO Pin NAND Flash Interface Mode Signal Name Default I/O Value Description MIO Voltage Bank 0 0 SRAM_CE_B[0] O - SRAM/NOR chip sel 0 0 1 SRAM_CE_B[1] O - SRAM/NOR chip sel 1 1 2 - - - - 2 NAND_CE_B O - - - - NAND_ALE O - NAND address latch - NAND chip select 3 SRAM_DQ[0] IO 0 SRAM/NOR data 3 NAND_WE_B O - NAND write enable
Chapter 11: Static Memory Controller 11.4 Wiring Diagrams The SMC supports the configurations shown in Figure 11-3, Figure 11-4, and Figure 11-5. The NOR/SRAM mode of the SMC can support two devices (NOR and/or SRAM) using chip selects 0 and 1.
Chapter 11: Static Memory Controller X-Ref Target - Figure 11-5 NAND Flash NAND_CE_B0 NAND_CLE CLE MIO Multiplexer NAND_ALE SMC Controller ALE NAND_RE_B RE# NAND_WE_B WE# NAND_BUSY R/B# NAND_IO[7:0] IO[7:0] NAND_IO[15:0] (for 16-bit data) GPIO System Reset# Zynq Device Boundary CEn IO[15:8] WPn RESETn UG585_c11_05_020613 Figure 11-5: NAND Flash Device Wiring Diagram 11.5 Register Overview The SMC registers are summarized in Table 11-6.
Chapter 11: Static Memory Controller 11.6 Programming Model The programming model is described in the ARM Static Memory Controller (PL350 series) Technical Reference Manual (see Appendix A, Additional Resources). The configuration of the SMC is summarized in Table 11-3. 11.
Chapter 12 Quad-SPI Flash Controller 12.1 Introduction The Quad-SPI flash controller is part of the input/output peripherals (IOP) located within the PS. It is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode. In I/O mode, software interacts closely with the flash device protocol.
Chapter 12: Quad-SPI Flash Controller • Device densities up to 128 Mb for I/O and linear mode. Densities greater than 128 Mb are supported in I/O mode.
Chapter 12: Quad-SPI Flash Controller The 8-bit parallel I/O configuration also requires that the devices have the same capacity. The address map for the parallel I/O configuration starts at FC00_0000 and goes to the address of the combined memory capacities, up to a maximum of FDFF_FFFF (32 MB). For the 4-bit Stacked I/O configuration, the devices can have difference capacities, but must have the same protocol.
Chapter 12: Quad-SPI Flash Controller The MIO pins for the Quad-SPI controller conflict with both the NOR and NAND interfaces of the SMC controller. The NOR/SRAM and NAND interfaces cannot be used when Quad-SPI is used. More information about the MIO pins is provided in section 2.5 PS-PL MIO-EMIO Signals and Interfaces. 12.2 Functional Description The Quad-SPI flash controller can operate in either I/O mode or linear addressing mode.
Chapter 12: Quad-SPI Flash Controller content of the TxFIFO, it concurrently samples the raw serial data, performs serial-to-parallel conversion, and stores data into RxFIFO. In the case of a read command, when data is to be driven by the flash memory after the command and address bytes, the MIO switches from output to input at the appropriate time under the control of the transmit logic.
Chapter 12: Quad-SPI Flash Controller 12.2.3 I/O Mode Transmit Registers (TXD) Software writes byte sequences that are needed for the specific flash device. Refer to the Quad-SPI device vendor's specification. The controller has four write-only 32-bit TXD registers for software to issue a stream of commands to get status and read/write data from the flash memory. Quad-SPI TXD register write formats are described in Table 12-1.
Chapter 12: Quad-SPI Flash Controller 12.2.5 Linear Addressing Mode The controller has a 32-bit AXI slave interface to support linear address mapping for read operations. When a master issues an AXI read command through this port, the Quad-SPI controller generates QSPI commands to load the corresponding memory data and send it back through the AXI interface.
Chapter 12: Quad-SPI Flash Controller AXI Read Command Processing AXI read burst commands are translated into SPI flash read instructions that are sent to the Quad-SPI controller TxFIFO. The controller transmit logic is responsible for retrieving the read instructions from the FIFO and passing them along to the SPI flash memory according to the SPI protocol. A 64-deep FIFO is used to provide read data buffering to hold up to four burst-of-16 data.
Chapter 12: Quad-SPI Flash Controller Read Data Management A 63-deep RxFIFO provides read data buffering to hold a minimum of three AXI burst transfer lengths of 16 bytes each. Since the RxFIFO starts receiving data as soon as the chip-select signal is active, the linear address adapter removes incoming data that corresponds to the instruction code, if any, the address, and the dummy cycles. The read data must be aligned with the corresponding word boundary specified by the address.
Chapter 12: Quad-SPI Flash Controller 12.2.6 Unsupported Devices A number of devices implement custom 4-bit wide SPI-like interfaces for flash memory access, such as the SQI devices from SST, and the Fast4 devices from Atmel. Some other Quad-SPI devices, like some Micron/Numonyx devices, offer an option to switch operation to such a custom 4-bit interface, through a non-volatile configuration bit. These interfaces operate differently from the devices supported by the Quad-SPI controller.
Chapter 12: Quad-SPI Flash Controller 12.3 Programming Guide Example: Start-up Sequence 1. Configure Clocks. Refer to section 12.4.1 Clocks. 2. Configure Tx/Rx Signals. Refer to section 12.5.2 MIO Programming. 3. Reset the Controller. Refer to section 12.4.2 Resets. 4. Configure the Controller. Refer to section 12.3.1 Configuration. Now, either configure the controller for linear addressing mode (section 12.2.5 Linear Addressing Mode) or configure the controller for I/O mode (section 12.3.
Chapter 12: Quad-SPI Flash Controller 12.3.2 Linear Addressing Mode Example: Linear Addressing Mode (Memory Reads) The sequence of operations for data reads in linear addressing mode is as follows: 1. Set manual start enable to auto mode. Set qspi.Config_reg[Man_start_en] = 0. 2. Assert the chip select. Set qspi.Config_reg[PCS] = 0. 3. Program the configuration register for linear addressing mode. Example values are shown in Table 12-3, page 344. 4. Enable the controller. Set qspi.
Chapter 12: Quad-SPI Flash Controller Note that the TxFIFO width must be programmed to 32 bits: qspi.Config_reg[FIFO_WIDTH] = 0b11. Software needs to take care of “consecutive non word aligned” transfers. Example: I/O Mode Interrupt Service Routine 1. Configure the ISR to handle the interrupt conditions based on the Quad-SPI device type. To read from the Quad-SPI device, the simplest ISR reads data from the RxFIFO and writes content to the TxFIFO.
Chapter 12: Quad-SPI Flash Controller 12.3.5 Rx/Tx FIFO Response to I/O Command Sequences Example command and sequences: • Write Enable Command • Read Status Command • Read Data Sequence In these examples, YY can have any value. Each YY pair could have a different value. To receive data in serial legacy mode, the value is sampled from MISO/DQ1 line into RxFIFO synchronous to clock, while the command and address transactions occur on MOSI/DQ0. Example: Write Enable Command (code 0x06) 1.
Chapter 12: TxFIFO Entry MSB 1 Invalid Invalid Invalid Invalid 0 0x3 0x00 Previous Previous Quad-SPI Flash Controller LSB Example: Read Data Sequence This example returns the four bytes of data at address 0 to the calling function. 1. Send the data read instruction. Write 0xA2A1_A003 to the qspi.TXD0 register. a. 2. Instruction includes command (0x03) plus address (A0, A1 and A2). Send dummy data. Write 0xD0D1_D2D3 (dummy data) to the qspi.TXD0 register (second TxFIFO entry). a.
Chapter 12: Quad-SPI Flash Controller 12.3.6 Register Overview The register overview is provided in Table 12-5.
Chapter 12: Quad-SPI Flash Controller CPU_1x Clock Refer to section 25.2 CPU Clock, for general clock programming information. The CPU_1x clock runs asynchronous to the Quad-SPI reference clock. QSPI_REF_CLK and Quad-SPI Interface Clocks The QSPI_REF_CLK is the main controller clock. The QSPI_REF_CLK is sourced from the PS Clock Subsystem. The clock enable, PLL select, and divisor setting are programmed using the slcr.LQSPI_CLK_CTRL register. Refer to section 25.6.
Chapter 12: Quad-SPI Flash Controller When operating at a Quad-SPI clock frequency greater than FQSPICLK2, the MIO 8 pin must be programmed as the feedback output clock and the MIO 8 pin must only be connected to a pull-up/pull-down resistor on the PCB for boot strapping. 12.4.2 Resets The controller has two reset domains: the APB interface and the controller itself. They can be controlled together or independently. The effects for each reset type are summarized in Table 12-6.
Chapter 12: Quad-SPI Flash Controller Single SS, 4-bit I/O A block diagram of the 4-bit flash memory interface connected to the controller configuration is shown in Figure 12-5. X-Ref Target - Figure 12-5 Zynq Device QSPI0_SCLK Quad-SPI Controller QSPI0_IO[3:0] QSPI0_SS_B CLK IO[3:0] Quad-SPI Flash Memory S UG585_c12_06_102014 Figure 12-5: Quad-SPI Single SS 4-bit I/O Dual SS, 8-bit Parallel The controller supports up to two SPI flash memories operating in parallel, as shown in Figure 12-6.
Chapter 12: Quad-SPI Flash Controller operation) both device’s status information before writing the status data in the RXFIFO. Table 12-7 shows the data bit arrangement of a 32-bit data word for 8 bit parallel configuration. Table 12-8 shows Quad-SPI CMD behavior in Dual Quad-SPI parallel mode.
Chapter 12: Quad-SPI Flash Controller Dual SS, 4-bit Stacked I/O To reduce the I/O pin count, the controller also supports up to two SPI flash memories in a shared bus configuration, as shown in Figure 12-7. This configuration increases the maximum addressable SPI flash memory from 16 MB (24-bit addressing) to 32 MB (25-bit addressing), but the throughput remains the same as for single memory mode.
Chapter 12: Quad-SPI Flash Controller Single SS, Legacy I/O The Quad-SPI controller can be operated in legacy single-bit serial interface mode for 1x, 2x and 4x I/O modes as shown in Figure 12-8. X-Ref Target - Figure 12-8 Zynq Device (SPI Master) QSPI0_SCLK QSPI0_IO[0] QSPI0_IO[1] Quad-SPI Controller QSPI0_SS_N QSPI0_IO[2] QSPI0_IO[3] CLK MOSI MISO SPI Slave SS WP HOLD UG585_c12_09_102014 Figure 12-8: Quad-SPI Single SS, Legacy I/O 12.5.
Chapter 12: 2. Quad-SPI Flash Controller Configure MIO pins 2 through 5 for I/O. Write 0x0000_0302 to each of the slcr.MIO_PIN_{02:05} registers: a. Route Quad-SPI 0 I/O pins to pin 2 through 5. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0). c. LVCMOS18 (refer to the register definition for other voltage options). d. Slow CMOS drive edge. 3. e. Disable internal pull-up resistor. f. Disable HSTL receiver. Configure MIO pin 6 for serial clock 0 output. Write 0x0000_0302 to the slcr.
Chapter 12: Quad-SPI Flash Controller d. Slow CMOS edge (benign setting). e. Disable internal pull-up resistor. f. Disable HSTL receiver. Option: Add 4-bit Data These steps are required for the dual selects, separate 4-bit data memory interface: 6. Configure MIO pins 10 through 13 for I/O. Write 0x0000_0302 to each of the slcr.MIO_PIN_{10:13} registers: a. Route Quad-SPI 1 I/O pins to pin 9 through 13. b. 3-state controlled by Quad-SPI (TRI_ENABLE = 0). c.
Chapter 12: Quad-SPI Flash Controller 12.5.3 MIO Signals The Quad-SPI flash memory signals are routed through the MIO multiplexer to the MIO device pins. Each side of the dual controller port can be individually enabled or operate together as an 8-bit I/O interface. The Quad-SPI flash memory signals are routed to the MIO pins as shown in Table 12-9.
Chapter 13 SD/SDIO Controller 13.1 Introduction The SD/SDIO controller communicates with SDIO devices, SD memory cards, and MMC cards with up to four data lines. On the SD interface, one (DAT0) or four (DAT0-DAT3) lines can be used for data transfer. The SDIO interface can be routed through the MIO multiplexer to the MIO pins or through the EMIO to SelectIO pin in the PL. The controller can support SD and SDIO applications in a wide range of portable low-power applications such as 802.
Chapter 13: SD/SDIO Controller X-Ref Target - Figure 13-1 SDMA ADMA1 ADMA2 Command Decoder Response Generator AHB Interface AHB SD/SDIO Host Controller SD/SDIO Bus Transmitter/ Receiver CPRM Interrupts Interrupt FIFO UG585_c13_01_020613 Figure 13-1: SD/SDIO Controller Block Diagram 13.1.
Chapter 13: SD/SDIO Controller 13.1.2 System Viewpoint Figure 13-2 shows the SD/SDIO controller system viewpoint. X-Ref Target - Figure 13-2 IRQ ID# {56, 79} Interconnect AHB Device Boundary MIO – EMIO Routing SDIO Interface Controller Master port MIO Pins CPU_1x clock SDIO{0, 1} CPU_1x reset Interconnect AHB Control Registers Slave port EMIO Signals PL SDIO{0, 1} Ref Clock UG585_c13_02_031812 Figure 13-2: SD/SDIO Controller System Viewpoint Diagram 13.2 Functional Description 13.2.
Chapter 13: SD/SDIO Controller The host-AHB controller acts as bridge between the AHB bus and the host controller. The SD/SDIO controller registers are programmed by the processor through the AHB interface. Interrupts are generated based on the values set in the Interrupt Status and Interrupt Enable registers. The bus monitor checks for violations occurring on the SD bus and timeout conditions.
Chapter 13: SD/SDIO Controller 13.2.6 Stream Write and Read This functionality applies to both DMA and non-DMA modes. WRITE_DAT_UNTIL_STOP(CMD20) writes a data stream from the host, starting at the given address, until a STOP_TRANSMISSION follows. READ_DAT_UNTIL_STOP(CMD11) reads a data stream from the card, starting at the given address, until a STOP_TRANSMISSION follows.
Chapter 13: SD/SDIO Controller • In DMA mode, the host controller initiates a DMA READ from the ARM processor only if space is available to accept a block of data. • In non-DMA mode, the host controller asserts a buffer write ready interrupt only if space is available to accept a block of data. Read During the read transaction when the FIFO is full (the FIFO does not have enough space to accept a block of data from the card) the host controller stops the clk_sd to the card.
Chapter 13: SD/SDIO Controller X-Ref Target - Figure 13-3 Start (1) (5) Set Block Size Reg Set Command Reg (2) (6) Wait for Command Complete Int Set Block Count Reg (3) Command Complete Int Occur (7) Set Argument Reg Clr Command Complete Sts (4) (8) Set Transfer Mode Reg Get Response Data (9) Write Read Write or Read (10-R) (10-W) Wait for Buffer Write Ready Int Wait for Buffer Write Ready Int Buffer Write Ready Int Occur (11-W) Clr Buffer Wr Rdy Sts Clr Buffer Rd Rdy Sts (12-
Chapter 13: SD/SDIO Controller The sequence for data transfers without using DMA is as follows: 1. Set the value corresponding to the executed data byte length of one block to the Block Size register. 2. Set the value corresponding to the executed data block count to the Block Count register. 3. Set the value corresponding to the issued command to the Argument register. 4. Set the value to Multi/Single Block Select and Block Count Enable.
Chapter 13: SD/SDIO Controller (12-R). Read a block of data (according to the number of bytes specified in Step (1)) from the Buffer Data Port register. (13-R). Repeat until all blocks are received and then go to Step (14). 14. If this sequence is for a single or multiple block transfer, go to Step (15). In case of an infinite block transfer, go to Step (17). 10. Wait for a transfer complete interrupt. 11.
Chapter 13: SD/SDIO Controller Burst types such as an 8-beat incrementing burst or a 4-beat incrementing burst, or a single transfer is used to transfer or receive the data from the system memory mainly to avoid the hold of the AHB bus by the master for a longer time. The sequence for using DMA is as follows: 1. Set the system address for DMA in the System Address register. 2. Set the value corresponding to the executed data byte length of one block in the Block Size register. 3.
Chapter 13: SD/SDIO Controller 10. Wait for the transfer complete interrupt and DMA interrupt. 11. If Transfer Complete is set to 1, go to Step (14). If DMA Interrupt is set to 1 go to Step (12). Transfer Complete has a higher priority than DMA Interrupt. 12. Write a 1 to the DMA Interrupt bit in the Normal Interrupt Status register to clear this bit. 13. Set the next system address of the next data position to the System Address register and go to Step (10). 14.
Chapter 13: SD/SDIO Controller 13.3.4 Using ADMA Figure 13-5 shows data transfers using ADMA. X-Ref Target - Figure 13-5 Start (1) Create Descriptor Table (2) (11) Set ADMA System Address Reg Wait For Transfer Complete Int and ADMA Error Int (3) Set Block Size Reg (4) (12) Check Interrupt Status Set Block Count Reg (5) Set Argument Reg Transfer Complete Int. Occurs (14) (13) (6) ADMA Error Int.
Chapter 13: SD/SDIO Controller If the Block Count Enable bit in the Transfer Mode register is set to 1, the total data length can be designated by the Block Count register and the descriptor table. These two parameters shall indicate same data length. However, transfer length is limited by the 16-bit Block Count register. If the Block Count Enable bit in the Transfer Mode register is set to 0, the total data length is designated not by Block Count register, but the descriptor table.
Chapter 13: SD/SDIO Controller Synchronous Abort The following sequence performs a synchronous abort. 1. Set the Stop At Block Gap Request bit in the Block Gap Control register to 1 to stop SD transactions. 2. Wait for a transfer complete interrupt.
Chapter 13: SD/SDIO Controller 13.3.6 External Interface Usage Example Zynq-7000 devices provide two secure digital (SD) ports that support SD and SDIO devices (see Figure 13-7). X-Ref Target - Figure 13-7 SDx_CLK SDx_CMD SD/SDIO Controller SDx_DAT[3:0] CLK CMD DAT[3:0] SDIO Device Zynq Device UG595_c13_07_031812 Figure 13-7: SDIO Controller Device Wiring Diagram 13.3.
Chapter 13: SD/SDIO Controller X-Ref Target - Figure 13-8 VIO SDx_CLK CLK SDx_CMD CMD SDx_DAT[3:0] DAT[3:0] SD/SDIO Controller SD Memory Card SDx_CDn SDx_WPn SD Card Slot Zynq Device UG595_c13_08_020613 Figure 13-8: SDIO Controller SD Card Detect and Write Protect Diagram 13.3.8 Bus Voltage Translation The SDIO power pin SDx_POW can be used to control power to the SDIO slots.
Chapter 13: Table 13-1: SD/SDIO Controller SDIO Interface Signals (Cont’d) SDIO Interface Default Controller Input Value EMIO Signal(1) MIO Pin Number I/O SDIO 0 Data 1 SDIO 0 Data 2 SDIO 0 Data 3 I/O EMIOSDIO0DATAI0 I EMIOSDIO0DATAO0 O ~ EMIOSDIO0DATATN0 O 0 EMIOSDIO0DATAI1 I EMIOSDIO0DATAO1 O ~ EMIOSDIO0DATATN1 O 0 EMIOSDIO0DATAI2 I EMIOSDIO0DATAO2 O ~ EMIOSDIO0DATATN2 O 0 EMIOSDIO0DATAI3 I EMIOSDIO0DATAO3 O EMIOSDIO0DATATN3 O 0 SDIO 0 Data 0 Name ~ 18, 30, 42
Chapter 13: Table 13-1: SD/SDIO Controller SDIO Interface Signals (Cont’d) SDIO Interface Default Controller Input Value EMIO Signal(1) MIO Pin Number I/O Name I/O SDIO 1 Card Detect Any pin except 7 and 8 I EMIOSDIO1CDN I SDIO 1 Write Protect Any pin except 7 and 8 I EMIOSDIO1WP I SDIO 1 Power Control ~ Any odd pin O EMIOSDIO1BUSPOW O SDIO 1 LED Control ~ ~ ~ EMIOSDIO1LED O SDIO 1 Bus Voltage ~ ~ ~ EMIOSDIO1BUSVOLT[2:0] O Notes: 1.
Chapter 14 General Purpose I/O (GPIO) 14.1 Introduction The general purpose I/O (GPIO) peripheral provides software with observation and control of up to 54 device pins via the MIO module. It also provides access to 64 inputs from the Programmable Logic (PL) and 128 outputs to the PL through the EMIO interface. The GPIO is organized into four banks of registers that group related interface signals. Each GPIO is independently and dynamically programmed as input, output, or interrupt sensing.
Chapter 14: General Purpose I/O (GPIO) 14.1.
Chapter 14: General Purpose I/O (GPIO) 14.1.3 Notices 7z007s and 7z010 CLG225 Devices The 7z007s single core and 7z010 dual core CLG225 devices reduce the available MIO pins to 32 as shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. Thus, in these devices, the only GPIO pins that are available for MIO are 15:0, 39:28, 48, 49, 52, and 53. The other MIO pins are unconnected and should not be used. All EMIO signals are available.
Chapter 14: General Purpose I/O (GPIO) X-Ref Target - Figure 14-2 INT_MASK INT_DIS INT_EN Read INT_STAT Write-1-to-clear Clr INT_TYPE INT_POLARITY Interrupt Detection Logic D IRQ #52 to GIC Q INT State INT_ANY Input DATA_RO MIO DATA Output MASK_DATA_LSW (Banks 0 & 1) GPIO Device Pad or MASK_DATA_MSW EMIO Output Enable DIRM (Banks 2 & 3) MIO Device I/O Buffers and Pins (Banks 0 & 1) OEN UG585_c14_02_022712 Figure 14-2: GPIO Channel Software configures the GPIO as either an output or
Chapter 14: General Purpose I/O (GPIO) • DATA: This register controls the value to be output when the GPIO signal is configured as an output. All 32 bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. • MASK_DATA_LSW: This register enables more selective changes to the desired output value. Any combination of up to 16 bits can be written.
Chapter 14: General Purpose I/O (GPIO) These bits can be used as general purpose outputs since the output driver is disabled at reset. The system can start using these as outputs after the voltage mode has been read during system boot. 14.2.4 Interrupt Function The interrupt detection logic monitors the GPIO input signal. The interrupt trigger can be a positive edge, negative edge, either edge, Low-level or High-level.
Chapter 14: Table 14-1: General Purpose I/O (GPIO) GPIO Interrupt Trigger Settings Type gpio.INT_TYPE_0 gpio.INT_POLARITY_0 gpio.INT_ANY_0 Rising edge-sensitive 1 1 0 Falling edge-sensitive 1 0 0 Both rising- and falling edge-sensitive 1 X 1 Level sensitive, asserted High 0 1 X Level sensitive, asserted Low 0 0 X 14.3 Programming Guide The GPIO Controller has four banks, two each for MIO and EMIO. Each GPIO pin can be programmed individually.
Chapter 14: General Purpose I/O (GPIO) Example: Configure MIO pin 10 as an input 1. Set the direction as input: Write 0x0 to the gpio.DIRM_0 register. This sets gpio.DIRM_0[10] = 0 . 14.3.3 Writing Data to GPIO Output Pins For GPIO pins configured as outputs, there are two options to program the desired value. Option 1: Read, modify, and update the GPIO pin using the gpio.DATA_0 register. Example: Set GPIO output pin 10 using the DATA_0 register. 1. Read the gpio.DATA_0 register: Read gpio.
Chapter 14: General Purpose I/O (GPIO) 14.3.5 GPIO as Wake-up Event The GPIO can be configured as a wake-up device. IMPORTANT: The GIC must be set up correctly. 1. Enable the GPIO interrupt in the GIC. 2. Enable the GPIO interrupt for the wanted pin(s) using the gpio.INT_EN_{0..3} register. Set 1 to gpio.INT_EN_0[10] to enable the GPIO10 interrupt. 3. Do not turn off any GPIO related clocks. 14.3.6 Register Overview An overview of the GPIO registers is shown in Table 14-2 (also refer to section 14.
Chapter 14: General Purpose I/O (GPIO) 14.4.1 Clocks The controller is clocked by the CPU_1x clock from the APB interface. All outputs and input sampling is done using the CPU_1x clock. For power management, clock gating can be employed on the GPIO controller clock using slcr.APER_CLK_CTRL[GPIO_CPU_1XCLKACT]. 14.4.2 Resets The controller is reset by the slcr.GPIO_RST_CTRL [GPIO_CPU1X_RST] bit. Refer to Chapter 26, Reset System, for more information.
Chapter 15 USB Host, Device, and OTG Controller 15.1 Introduction The USB controller is capable of fulfilling a wide range of applications for USB 2.0 implementations as a host, a device, or On-the-Go. Two identical controllers are in the Zynq-7000 device. Each controller is configured and controlled independently. The USB controller I/O uses the ULPI protocol to connect external ULPI PHY via the MIO pins.
Chapter 15: USB Host, Device, and OTG Controller 15.1.1 Features The USB controller has the following key features: • USB 2.0 High Speed Host controller (480 Mb/s). ° • USB 2.0 HS and FS Device controller. ° • • • • ° Host Negotiation Protocol (HNP). ° Session Request Protocol (SRP). All USB Transaction types • • Control, Bulk, Interrupt, Isochronous Local DMA Engine. ° AHB Bus Master. ° Transfers data between system memory and controller FIFOs.
Chapter 15: USB Host, Device, and OTG Controller 15.1.2 Operating Modes The USB controller can operate in the modes shown in Figure 15-1. X-Ref Target - Figure 15-1 Host Mode Zynq OTG PHY Device or Downstream Hub HS: EHCI FS/LS: TT in EHCI Zynq PHY HNP SRP Device Mode Zynq PHY Host or Upstream Hub Another OTG Device HS, FS UG585_c15_30_030712 Figure 15-1: USB Controller Operating Modes Host mode.
Chapter 15: USB Host, Device, and OTG Controller MIO ULPI Data, flow control IRQ ID# {53, 76} Interconnect AHB Master port USB Controllers Device Boundary X-Ref Target - Figure 15-2 ULPI Pins USB {0, 1} CPU 1x clock USB {0, 1} CPU 1x reset Interconnect APB Slave port EMIO Control Registers Port Indicator, Power Control PL UG585_c15_31_030713 Figure 15-2: USB Hardware System Block Diagram The two independent USB controllers have individual control and status registers.
Chapter 15: • USB Host, Device, and OTG Controller Port Indicator and Power Pins via EMIO. The USB port indicator outputs, power select output, and power fault input signals are routed through the EMIO to the SelectIO pins in the PL and external board logic. 15.1.4 Controller Block Diagram The controller interfaces to the PS system memory on one side and an external ULPI PHY device on the USB side. A block diagram is shown in Figure 15-3. A detailed functional block is shown in section 15.1.9 Notices.
Chapter 15: USB Host, Device, and OTG Controller Port Transceiver Controller The port transceiver controller provides suspend/resume and, for device mode, chirp control functions. The port transceiver controller is fairly simple because the 8-bit data bus of the protocol engine is passed-through to the 8-bit ULPI and the entire back-end of the USB controller works synchronously to the 60 MHz USB clock from the PHY. ULPI Link Wrapper The protocol engine includes an internal bus that is similar to UTMI+.
Chapter 15: USB Host, Device, and OTG Controller Control and Status Registers The control and status registers include constants, configuration and operational/status for EHCI compatibility (Host mode) and non-EHCI functions (Device, OTG and enhanced Host mode). The registers are summarized in section 15.3.4 Register Overview. Clocks The ULPI interface and Protocol engine are clocked by the 60 MHz input on the ULPI interface (PHY clock output). The AHB interface is clocked by the CPU_1x clock.
Chapter 15: USB Host, Device, and OTG Controller X-Ref Target - Figure 15-4 Endpoint Queue Heads Queue Head List dQH Host Schedules (EHCI) Periodic Frame List Programmable number of elements Frame n Elements Endpoint 11 IN Device Responds to Host Requests Maintain Queue Head List Frame 3 Elements Aysnchronous Queue Heads Insert and Remove QH’s as needed Queue Head a Queue Head b EndPoint 1 OUT Frame 2 Elements Queue Head b EndPoint 0 IN Frame 1 Elements EndPoint 0 OUT Frame 0 Elements FRINDEX
Chapter 15: USB Host, Device, and OTG Controller Queue Head (QH). Each dTD can point to another dTD (using next dTD pointer) or terminate the linked list by setting its (T) bit = 1. The controller maintains a local, working copy of the dQH that it overlays with the one or more dTDs as the transaction request is processed. After each dTD transfer is complete, the dTD overlay is written back to the system memory with transfer results (status).
Chapter 15: USB Host, Device, and OTG Controller Documents and Specifications The reader should be familiar of USB technology and access to the following documents. These documents are mentioned in the text and are listed in Third-Party IP and Standards Documents in Appendix A. Zynq-7000 AP SoC Documents ° TRM for all Zynq-7000 series; UG585. Architecture and register-level programming. ° Data Sheet for 7z010, 7z015, and 7z020 dual core and 7z007s, 7z012s, and 7z014s single core devices; DS187.
Chapter 15: USB Host, Device, and OTG Controller 15.1.9 Notices 7z007s and 7z010 CLG225 Devices The 7z007s single core and 7z010 dual core CLG225 devices support 32 MIO pins as shown in the MIO table in section MIO-at-a-Glance Table in Chapter 2. Only one USB interface is available in these CLG225 devices. If USB and GigE are required, the GigE I/O signals must interface through the EMIO. 15.1.
Chapter 15: USB Host, Device, and OTG Controller 15.2 Functional Description This section generally applies to both device and host modes. 15.2.1 Controller Flow Diagram The controller flow diagram in Figure 15-6 shows the USB data transfer flows, the descriptor flows, and the interface to software.
Chapter 15: USB Host, Device, and OTG Controller The DMA engine is a 32-bit bus master on the AHB interface to access the PS system interconnect.
Chapter 15: USB Host, Device, and OTG Controller The protocol engine is responsible for all error checking, check field generation, formatting all the handshake, Ping and data response packets on the bus, and for generating signals that are needed based on a USB based time frame.
Chapter 15: USB Host, Device, and OTG Controller X-Ref Target - Figure 15-9 APB Control and Status Registers Slave ULPI Link Wrapper Port Controller Control Protocol Engine * Suspend/Resume Device: * Port State Machine * Chirp Control Similar to UTMI+ Host: * Port State Machine * Transceiver Logic ULPI I/O Interface UG585_c15_38_030713 Figure 15-9: USB Port Controller and ULPI Link Wrapper Block Diagram 15.2.
Chapter 15: USB Host, Device, and OTG Controller 15.3.1 Hardware/Software System The physical and virtual data flows for a USB hardware/software system are illustrated in Figure 15-10. These flows form the basis of USB. The TRM is focused on the operations of the bus interface and device layers as a foundation for writing drivers that include the functional layer.
Chapter 15: USB Host, Device, and OTG Controller X-Ref Target - Figure 15-11 Reset * PS_POR_B reset (all USB registers) * slcr.USB_RST_CTRL [USB_CPU1X_RST] (all USB registers) * usb.USBCMD [RST] (USB registers except those for OTG functionality) Idle usb.USBMODE [CM] = 10 usb.USBMODE [CM] = 11 reset Device Mode Host Mode reset UG585_c15_40_030713 Figure 15-11: USB Controller Mode Diagram 15.3.
Chapter 15: USB Host, Device, and OTG Controller • Dev register is used by the device controller driver software (DCD). • Host register is used by the host controller driver software (HCD). • EHCI register includes content from the specification. ‘x’ means partial. ‘ex’ means exclusive. Table 15-1: Offset Address USB Controller Register Overview Register Name Bit Acronym OTG/ Mode Dev Host x x EHCI Type Affected by USBCMD Reset RO no Identification: Configuration Constants.
Chapter 15: Table 15-1: Offset Address USB Host, Device, and OTG Controller USB Controller Register Overview (Cont’d) Register Name Bit Acronym OTG/ Mode Dev Host EHCI Type 0x0178 ENDPTNAK x ~ ~ R/WTC 0x017C ENDPTNAKEN x ~ ~ RW Affected by USBCMD Reset Operational: Host mode (EHCI) and Device mode. 0x0180 0x0184 CONFIGFLAG x x x x RO PORTSC1 x x x x RW, RO, R/W1C partial no [WKDS] [WKCN] [WKOC] [PIC] [PR] no others yes Operational: Mode Control.
Chapter 15: Table 15-2: USB Host, Device, and OTG Controller USB Interrupt and Status Register Bits USBSTS (status) Bit Field Type USBINTR (enable) Bit Field Description Cross Reference Dev Host [TI1] 25 Interrupt 25 Timer 1. x x [TI0] 24 Interrupt 24 Timer 0. x x [UPI] 19 Interrupt 19 Periodic qTD complete. ~ x [UAI] 18 Interrupt 18 Async qTD complete. ~ x [NAKI] 16 Interrupt 16 Device generated NAK. x ~ [AS] 15 Status-only na Async Schedule state.
Chapter 15: USB Host, Device, and OTG Controller 15.4.1 Controller State The device mode includes the active physical state of the controller, left side of Figure 15-12, and the suspend state maintained in software, right side of the figure. Power interruptions, resets and USB activity all contribute to the sequencing through these states. X-Ref Target - Figure 15-12 Active State Suspend State Powered Set the Run bit: usb.USBCMD [RS] = 1.
Chapter 15: Table 15-3: USB Host, Device, and OTG Controller USB Device State Information Bits Bit Description Register Bit Interrupt Suspend Mode usb.USBSTS [SLI] Yes USB Reset Received usb.USBSTS [URI] Yes Port Change Detect usb.USBSTS [PCI] Yes High-Speed Port usb.PORTSC1 [PSPD] No As a result of entering the address state, the device address register (usb._DEVICEADDR) must be programmed by the DCD.
Chapter 15: USB Host, Device, and OTG Controller Port Change Detect After a port change detect, the device has reached the default state and the DCD can read the PORTSC1 register to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and the DCD can respond to enumeration according to the USB Chapter 9 - Device Framework. The DCD can use the FS/HS mode information to determine the bandwidth mode of the device.
Chapter 15: USB Host, Device, and OTG Controller X-Ref Target - Figure 15-13 0x600 Queue Head List Endpoint 11 IN dTD Pointer dTD 4KB Memory ffer Buffer Bu ter in Po dTD Pointer T=0 dTD 4KB Memory Buffer ffer Bu ter n i Po dTD Pointer T=0 0x5C0 4KB Memory Buffer ffer Bu ter in Po dTD Pointer 0x0B0 Endpoint 1 OUT dTD Pointer dTD T=0 ffer Bu ter in Po 0x080 Endpoint 0 IN dTD Pointer dTD Endpoint 0 OUT ffer Bu ter in Po dTD Pointer Endpoint Queue Heads (dQH) dTD T=1 T=1 4KB Memory Bu
Chapter 15: USB Host, Device, and OTG Controller X-Ref Target - Figure 15-14 System Memory USB Controller dQH 0x600 Endpoint 11 IN 0x5C0 Queue Head List 0x0C0 dQH Read/Write dQH dTD EndPoint 1 OUT Transfer Overlay Area (7 DWords) 0x080 EndPoint 0 IN 31 Transaction Descriptor Processor 0x040 EndPoint 0 OUT 0x000 0 usb.
Chapter 15: USB Host, Device, and OTG Controller controller. The operation of an endpoint and use of queue heads are described later in this document. 15.5.3 Endpoint Registers The endpoint registers are listed in Table 15-4 USB Device Endpoint Register Summary. These registers were summarized at the end of Table 15-1, page 407. In general, there is one bit for each endpoint. The lower half of the register bits are for Rx endpoints and the upper half is for Tx endpoints.
Chapter 15: USB Host, Device, and OTG Controller Endpoint Configuration Registers Table 15-5: USB Device Endpoint Configuration Register Summary Description and Register Bit Field Register Name Tx Software can control the STALL behavior for Rx and Tx transactions to the control endpoint. Software can read the control endpoint configuration. ENDPTCTRL0 Type Rx [TXS], 16 [RXS], 0 Others: always enabled, Tx and Rx capable. (see below) Read-write. Read-only.
Chapter 15: Table 15-6: USB Host, Device, and OTG Controller USB Device Endpoint Initialization (Cont’d) Field Value Endpoint Type, usb. ENDPTCTRLx [TXT] Depends on the setup request. Endpoint Stall, usb.ENDPTCTRLx [TXS] 0 Meaning 00: 01: 10: 11: Control Isochronous Bulk Interrupt Do not force stall response. Stall There are two occasions where the device controller might need to return a STALL to the host: • Functional Stall: software initiated (non-control endpoints only).
Chapter 15: USB Host, Device, and OTG Controller Data Toggle Inhibit This feature is for test purposes only and should never be used during normal device controller operation. Setting the data toggle inhibit bit active (usb.ENTPTCTRLx [RXI] bit = 1) causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state.
Chapter 15: USB Host, Device, and OTG Controller After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint up to the maximum number of endpoints configured at device synthesis time. After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUS register.
Chapter 15: Table 15-8: USB Host, Device, and OTG Controller USB Device Variable Length Transfer Protocol Examples Bytes dTD.ZLT = 0 Max. Packet Length dTD dQH N P1 P2 511 256 2 256 256 512 256 3 256 256 512 512 2 512 0 dTD.ZLT = 1 P3 0 N P1 P2 2 256 256 2 256 256 1 512 P3 Note: The dQH.Mult field must be set to 00 for Bulk, Interrupt, and Control endpoints. The dQH.ZLT bit operates as follows on Bulk and Control transfers: dQH.
Chapter 15: USB Host, Device, and OTG Controller Rx dTD Completes • All packets described in dTD were successfully received. Total bytes in dTD equals 0 when this occurs. • A short packet (number of bytes < maximum packet length) was received. This is a successful transfer completion; the DCD must check Total Bytes in dTD to determine the number of bytes that are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes received.
Chapter 15: Table 15-9: USB Host, Device, and OTG Controller USB Device Interrupt and Bulk Endpoint Bus Response (Cont’d) Packet Identifier Stall Bit [TXS] Endpoint Not Primed Endpoint Primed Buffer Underflow Buffer Overflow Endpoint Not Enabled Invalid Ignore Ignore Ignore Ignore Ignore BTO Notes: 1. BS Error — Force Bit Stuff Error. 2. NYET/ACK — NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. 3.
Chapter 15: USB Host, Device, and OTG Controller corresponding dTD when MULT transactions occur or the device controller finds a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the iso dTD and move to the next iso dTD.
Chapter 15: USB Host, Device, and OTG Controller Isochronous Pipe Synchronization When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number (read the FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame number [N], the DCD should interrupt on SOF during frame N - 1. When the FRINDEX = N - 1, the DCD must write the prime bit.
Chapter 15: USB Host, Device, and OTG Controller Setup Packet Handling using the Tripwire Disable setup lockout by writing 1 to setup lockout mode, usb.USBMODE [SLOM] bit field; once at initialization. Setup lockout is not necessary when using the tripwire as described in the example below. Example: Setup Packet Handing using the Tripwire After receiving an interrupt and inspecting usb.ENDPTSETUPSTAT register to determine that a setup packet was received on a particular pipe (i.e.
Chapter 15: USB Host, Device, and OTG Controller Should a setup arrive after the data stage is primed, the device controller automatically clears the prime status (usb.ENDPTSTATUS) to enforce data ordering with the setup packet. Note: The dQH.Mult field must be set to 00 for bulk, interrupt, and control endpoints. Error handling of data phase packets is the same as bulk packets described previously.
Chapter 15: • USB Host, Device, and OTG Controller 15.7.3 Endpoint Transfer Overlay Area 15.7.1 Endpoint Queue Head Descriptor (dQH) The device Endpoint Queue Head (dQH) is where all device controller transfers are managed. The dQH is a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the hardware reads the dQH and the first device transfer descriptor (dTD) from system memory and overlays it onto DWords 2 through 8 of the dQH as shown in Table 15-12.
Chapter 15: Table 15-13: USB Device dQH DWords 0 to 11: Descriptor Bit Details (Cont’d) Bits 15 14:0 USB Host, Device, and OTG Controller Description Interrupt On Setup, IOS. This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. Reserved. Field reserved and should be set to 0. DWord 1: Current dTD Pointer 31:5 Current dTD Pointer. Pointer to the dTD that is represented in the transfer overlay area.
Chapter 15: USB Host, Device, and OTG Controller 15.7.3 Endpoint Transfer Overlay Area The dQH is read from memory by the controller and links to a dTD. The dTD is also read from memory and is written into the overlay area of the dQH as shown in Table 15-15. The seven DWords in the overlay area represent a transaction working space for the device controller. After an endpoint is readied, the dTD will be copied into this dQH overlay area by the device controller.
Chapter 15: Table 15-15: USB Host, Device, and OTG Controller USB Device Transfer Overlay (Cont’d) Bits Description dTD DWord dQH DWord 1 3 2 4 3 5 4 to 6 6 to 8 Total Bytes, MultO, and Status. 31 30:16 15 Reserved. Field reserved and should be set to 0. Total Bytes. Total number of bytes to be moved with this transfer descriptor. Refer to section Total Bytes to Transfer Parameter for more info. Interrupt On Complete, IOC.
Chapter 15: USB Host, Device, and OTG Controller Example 2: Send two packets • If dQH.multiplier = 3; Max packet size = 8; Total Bytes = 15; dQH.Mult = 2, then two packets are sent: Data1 (8) +Data0 (7). Buffer Pointer Pages The buffer pointers are aligned to 4KB boundaries. The total byes and buffer pointers are discussed in section Total Bytes to Transfer Parameter.
Chapter 15: USB Host, Device, and OTG Controller 15.8.1 Software Model The USB device controller API software provides a framework of routines to control the USB controller in device applications. The software should be designed to significantly simplify the software tasks required to develop a USB device application. The API software presents a high-level data transfer interface to the user's application code. All the register, interrupt and DMA interactions with the controller are managed by the API.
Chapter 15: 1. USB Host, Device, and OTG Controller Set the controller to device mode. Write 10 to the usb.USBMODE [CM] bit. ° Transitioning from host mode to device mode requires a device controller reset before modifying USBMODE. ° Set usb.OTGSC [OT] bit = 1. 2. Allocate and initialize dQH’s. ° ° ° Minimum: Initialize dQH’s for endpoint 0 for Tx and Rx. All control endpoint queue heads must be initialized before the control endpoint is enabled.
Chapter 15: USB Host, Device, and OTG Controller The dQH’s are indexed (two for each endpoint) in the 24-element Endpoint Queue Head List. To setup a transfer, software constructs the dQH and dTD(s) for an IN or OUT operation. Software must maintain a consistent set of descriptors, schedules/lists, and data buffers in system memory for the controller. When the endpoint is ready to receive or send the data, software primes the endpoint.
Chapter 15: 1. USB Host, Device, and OTG Controller Decode setup packet and prepare data phase (optional) and status phase transfer as required by the USB Chapter 9 or application specific protocol. 15.9.3 Manage Transfers with Transfer Descriptors Example: Build a Transfer Descriptor Before a transfer can be executed, a dTD must be built to describe the transfer. Use the following procedure for building dTD’s.
Chapter 15: USB Host, Device, and OTG Controller If 0 go to step 3. If 1 continue to step 6. 6. Write usb.USBCMD [ATDTW] bit = 0. 7. If status bit read in (4) is 1 DONE. 8. If status bit read in (4) is 0 then Goto Case 1: step 1. Transfer Completion After a dTD has been initialized and the associated endpoint primed the device controller will execute the transfer upon the host-initiated request.
Chapter 15: USB Host, Device, and OTG Controller flush failed: in very rare cases, a packet is in progress to the particular endpoint when commanded flush using usb.ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully. The DCD might need to repeatedly flush any endpoints that fail to flush be repeating steps 1–3 until each endpoint is successfully flushed.
Chapter 15: USB Host, Device, and OTG Controller must acknowledge a setup token in the timeliest manner possible to have the control endpoint and buffer always available for another Setup token. The SOF interrupt is next important. Table 15-17: USB Device High Frequency Interrupt Execution Order Interrupt 1a USB Interrupt ENDPTSETUPSTATUS [UI] Copy contents of setup buffer and acknowledge setup packet. Process setup packet according to USB 2.0 Chapter 9 or application specific protocol.
Chapter 15: USB Host, Device, and OTG Controller 15.10 Host Mode Data Structures The programming model follows the EHCI specification model and includes additional registers and bits to support a virtual transaction translator that is embedded into the DMA and protocol engines of the high speed host controller. The Rx and Tx data FIFOs must respond to the USB in real-time. Packet sizes can be up to 1024 bytes.
Chapter 15: USB Host, Device, and OTG Controller • Isochronous split transaction data streams are managed with split-transaction isochronous transfer descriptors (siTD). • Interrupt, Control, and Bulk data streams are managed via queue heads (QH) and queue element transfer descriptors (qTD). These data structures are optimized to reduce the total memory footprint of the schedule and to reduce (on average) the number of memory accesses needed to execute a USB transaction. 15.10.
Chapter 15: Table 15-20: USB Host, Device, and OTG Controller USB Host Periodic Frame List Element Bit Fields Bit Field Description 31:5 Pointer Frame List Link Pointer (system memory pointer, 32-byte aligned): The referenced object might be: • an isochronous transfer descriptor (iTD for HS devices), • a split-transaction isochronous transfer descriptor (siTD for FS isochronous endpoints), or • a queue head (QH for FS/LS/HS interrupts). 4:3 reserved 2:1 TYP Bits 0 T Set = 00.
Chapter 15: USB Host, Device, and OTG Controller X-Ref Target - Figure 15-16 Aysnchronous Queue Heads (Bulk and Control) Round Robin Priority. QHs are processed as Bandwidth allows. Start of List Queue Head 0 Asynchronous QH Address Pointer (32-bit system address) Queue Head 1 Queue Head 2 00000 Insert and Remove QH’s as needed usb.
Chapter 15: USB Host, Device, and OTG Controller Embedded Transaction Translator The host controller uses the DMA and protocol engines to emulate the transaction translator (TT) for FS/LS devices attached to Zynq. The embedded transaction translator (TT) affects multiple functions in the host controller: ° Discovery Mechanism, refer to section 15.11.3 EHCI Functional Changes for the TT ° FS/LS Data Structures, refer to section 15.11.
Chapter 15: USB Host, Device, and OTG Controller 15.11.2 Embedded Transaction Translator The host controller emulates one transaction translator (TT) with up to 16 periodic (Iso/Int) contexts and 2 asynchronous (bulk/ctrl) contexts. The TT allows FS/LS devices to be attached directly to the controller in host mode without the need for hardware to implement a companion controller.
Chapter 15: USB Host, Device, and OTG Controller Functional Block Diagram X-Ref Target - Figure 15-17 Embedded Transaction Translator in Host Mode Using EHCI Software Model Traditional Hardware Based Companion Controller In a Hub-based Design EHCI Shared Memory EHCI Software Stack HS USB 2.0 EHCI High Speed Controller High-speed Handler B/C Transfer Iso/Int State & Context Iso/Int Startsplit FIFO (16) Iso/Int State & Context B/C State & Context Iso/Int Compl.
Chapter 15: USB Host, Device, and OTG Controller 15.11.3 EHCI Functional Changes for the TT This section includes: • Port Reset Timer to off-load software • Port Speed detection In a standard EHCI controller design, the Host controller driver (HCD) detects a full-speed or low-speed device by noting if the port enable bit is set after the port reset operation. The port enable is set after the port reset operation when the host and device negotiate a High-Speed connection (i.e.
Chapter 15: USB Host, Device, and OTG Controller 2. Reset the device. Writes a 1 to the usb.PORTSC1 [PR] bit. assumes the 3. Optional Step to de-assert Reset. The HCD normally writes a 0 to the [PR] bit to de-assert the reset after 10 ms. This step, which is necessary in a standard EHCI design, can be omitted. Should the EHCI HCD attempt to write a 0 to the reset bit while a reset is in progress, the write is ignored and the reset continues until completion. 4. Wait for device to be operational.
Chapter 15: USB Host, Device, and OTG Controller 15.11.7 Operational Model of the TT The operational models are well defined for the behavior of the transaction translator (see USB 2.0 specification) and for the EHCI controller to move packets between system memory and a USB-HS hub. Since the transaction translator exists within the host controller there is no physical bus between EHCI HCD and the USB FS/LS bus.
Chapter 15: Table 15-22: USB Host, Device, and OTG Controller USB Handshake Emulation Conditions (Cont’d) Condition TT Response Start-Split: Start periodic transaction. No Handshake (OK) Complete-Split: Failed to find transaction in queue. Bus Time Out Complete-Split: Transaction in queue is busy. NYET Complete-Split: Transaction in queue is complete. Actual Handshake Asynchronous Transaction Scheduling and Buffer Management The following USB 2.
Chapter 15: USB Host, Device, and OTG Controller 15.12 Host Data Structures Reference These descriptor data structures are compatible with the EHCI specification with some differences as noted in section 15.11 EHCI Implementation. The data structures defined in this section are (from the host controller's perspective) a mix of read-only and read/writable fields. The host controller preserves the read-only fields. Section Content • 15.12.1 Descriptor Usage • 15.12.
Chapter 15: Table 15-24: USB Host, Device, and OTG Controller USB Host Transfer Descriptor Type (TYP) Bit Field (Cont’d) Data Structure QH FSTN iTD 00 QH 01 siTD 10 FSTN Description 11 ~ ~ X ~ Table 15-40 USB Host Queue Head (QH) Descriptor Format ~ ~ ~ X Table 15-45 USB Host Frame Span Traversal Node Descriptor (FSTN) Format 15.12.3 Isochronous (High Speed) Transfer Descriptor (iTD) The format of a high-speed isochronous transfer descriptor is illustrated in Table 15-25.
Chapter 15: Table 15-26: USB Host, Device, and OTG Controller USB Host iTD DWord 0: Next Link Pointer (Cont’d) Bits Description 2:1 Transaction Descriptor Type, TYP. Set to 00 (iTD type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. 0 Terminate transfer, T. • 0: link to the Next iTD Pointer field; the address is valid. • 1: end the transaction, the Next iTD Pointer field is not valid.
Chapter 15: Table 15-27: USB Host, Device, and OTG Controller USB Host iTD Dwords 1 to 8: Transaction Status and Control List (Cont’d) Bits Description 15 Interrupt On Complete, IOC. If this bit is set to 1, it specifies that when this transaction completes, the host controller should issue an interrupt at the next interrupt threshold. 14:12 Page Select, PG.
Chapter 15: Table 15-28: USB Host iTD DWords 9 to 15: Buffer Page Pointer List (Cont’d) Bits 1:0 USB Host, Device, and OTG Controller Description Mult. Selects the number of transactions to execute per transaction description (e.g. per microframe). • 00: Reserved.
Chapter 15: USB Host, Device, and OTG Controller 15.12.4 Split Transaction Isochronous Transfer Descriptor (siTD) This data structure is used to manage FS isochronous transfers via split transactions to USB 2.0 Hub Transaction Translator. There are additional fields used for addressing the hub and scheduling the protocol transactions (for periodic).
Chapter 15: Table 15-31: USB Host, Device, and OTG Controller USB Host siTD DWords 1 and 2:Endpoint State (Cont’d) Bits Description 15:12 Reserved. Field reserved and should be set to 0. 11:8 Endpoint Number, EndPt. 4-bit field selects the endpoint on the device serving as the data source or sink. 7 6:0 Reserved. Bit reserved and should be set to 0. Device Address. Select the specific device serving as the data source or sink. DWord 2: Microframe Schedule Control 31:16 Reserved.
Chapter 15: USB Host, Device, and OTG Controller siTD DWord 3: Transfer Status and Control DWord 3 is used to manage the state of the split data transfer. Table 15-32: USB Host siTD DWord 3: Transfer Status and Control Bits Description 31 Interrupt On Complete, IOC.
Chapter 15: USB Host, Device, and OTG Controller siTD DWords 4 and 5: Buffer Pointer List DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page cross. The most significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers. The least significant 12 bits of each DWord are used as additional transfer state. Table 15-33: USB Host siTD DWords 4 and 5: Buffer Pointers Bits Description DWord 4 31:12 Buffer Pointer (Page 0).
Chapter 15: USB Host, Device, and OTG Controller 15.12.5 Queue Element Transfer Descriptor (qTD) This data structure is only used with a queue head. This data structure is used for one or more USB transactions. This data structure is used to transfer up to 20,480 (5 times 4,096) bytes. The structure contains two structure pointers used for queue advancement, a DWord of transfer state, and a five-element array of data buffer pointers. This structure is 32 bytes (or one 32-byte cache line).
Chapter 15: USB Host, Device, and OTG Controller qTD DWord 1: Alternate Next Element Pointer The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the data stream to the next client buffer on short packet. To be more explicit the host controller will always use this pointer when the current qTD is retired due to short packet.
Chapter 15: Table 15-38: USB Host, Device, and OTG Controller USB Host qTD DWord 2: DT, Total Bytes (Cont’d) Bits Description 11:10 Error Counter, Cerr. This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD. HCD write: • 00: the controller will not count errors for this qTD and there will be no limit on the retries of this qTD.
Chapter 15: Table 15-38: USB Host, Device, and OTG Controller USB Host qTD DWord 2: DT, Total Bytes (Cont’d) Bits Description 3 Transaction Error Status. Set to a 1 by the host controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). If the controller sets this bit to a 1, then it remains a 1 for the duration of the transfer. 2 Missed Microframe Status. This bit is ignored unless the QH.
Chapter 15: USB Host, Device, and OTG Controller 15.12.6 Queue Head (QH) The first three DWords of the QH include Static State information about the endpoint. The current qTD pointer is the system memory address pointer for the current qTD and is updated by the hardware when a new qTD is written (overlaid) in the QH’s overlay area.
Chapter 15: USB Host, Device, and OTG Controller QH DWords 1 and 2: Endpoint Capabilities and Characteristics The second and third DWords of a Queue Head specifies static information about the endpoint. This information does not change over the lifetime of the endpoint. The host controller must not modify the bits in these DWords. Table 15-42: USB Host QH DWords 1 and 2: Endpoint Capabilities and Characteristics Bits Description DWord 1: Capabilities and Characteristics.
Chapter 15: Table 15-42: USB Host, Device, and OTG Controller USB Host QH DWords 1 and 2: Endpoint Capabilities and Characteristics (Cont’d) Bits Description 29:23 Port Number. This is used in the split-transaction protocol.This field is ignored by the host controller unless the QH.EPS field indicates a full- or low-speed device. The value is the port number identifier on the USB 2.
Chapter 15: USB Host, Device, and OTG Controller A 0 value in this field, in combination with existing in the periodic frame list has undefined results. This field should have only one bit set to 1 at any given time. Having more than one bit set will result in undefined results. QH DWord 3: Current qTD Pointer The DWord 3 of a Queue Head contains a pointer to the source qTD currently associated with the overlay.
Chapter 15: Table 15-44: USB Host, Device, and OTG Controller USB Host Transfer Overlay Descriptors (Cont’d) Bits qTD QH DWord DWord Description Alternate Next qTD Pointer 31:5 Alternate Next qTD Pointer. 4:1 NAK Counter, NakCnt. This field is a counter the host controller decrements whenever a transaction for the endpoint associated with this queue head results in a Nak or Nyet response.
Chapter 15: Table 15-44: USB Host, Device, and OTG Controller USB Host Transfer Overlay Descriptors (Cont’d) Bits qTD QH DWord DWord Description Buffer Pointer (pages 3 and 4) 31:12 Buffer Pointer. 4KB aligned pointer to system memory address bits [31:12]. 11:0 Reserved. 6 and 7 10 and 11 15.12.8 Periodic Frame Span Traversal Node (FSTN) This data structure is to be used only for managing Full- and Low-speed transactions that span a Host-frame boundary.
Chapter 15: Table 15-47: USB Host, Device, and OTG Controller USB Host FSTN DWord 1: Back Path Link Pointer Bits Description 31:5 Back Path Link Pointer. This field contains the address of a Queue Head. This field corresponds to memory address signals [31:5], respectively. 4:3 Reserved. Field reserved and should be set to 0. 2:1 Transaction Descriptor Type, TYP. Set to 11 (FSTN type). Refer to section 15.12.2 Transfer Descriptor Type (TYP) Field for general information. 0 Terminate bit, T.
Chapter 15: USB Host, Device, and OTG Controller 15.14.1 Hardware Assistance Features The hardware assist mechanisms provide automated response and sequencing that might not be possible using software due to significant interrupt latency response times. The use of this additional circuitry is optional and can be used to assist the three sequences below. • Auto-Reset [HAAR]: Reset after a connect event. • Data-Pulse [HADP]: Generates a 7 ms pulse on the DP signal.
Chapter 15: USB Host, Device, and OTG Controller When the HCD has enabled this hardware assist, it must not interfere during the transition and should not write any control registers until it gets an interrupt from the device controller signifying that a reset interrupt has occurred or at least first verify that the controller has entered device mode. The HCD must not activate the soft reset at any time since this action is performed by hardware.
Chapter 15: USB Host, Device, and OTG Controller 15.15 System Functions The system functions include clocks, resets, memory interfaces and system interrupts.
Chapter 15: USB Host, Device, and OTG Controller 60 MHz PHY Clock The external PHY provides a 60 MHz clock that the ULPI is sync’d to and is used by the a majority of the controller logic. 15.15.2 Reset Types To reset the controller, software writes a 1 to the usb.USBCMD [RST] bit. When the reset process is completed, the controller hardware sets this bit to 0. Once the reset is started, the controller cannot stop the process. Writing a 0 has no effect.
Chapter 15: fs Table 15-49: USB Host, Device, and OTG Controller USB Resets Summary List Reset Name Controller State Registers IRQ Reference Yes Yes no Chapter 26, Reset System. Reset values: Appendix B, Register Details. Partial no Device and Host Modes no Section 15.14.1 Hardware Assistance Features PS System Reset AMBA (APB/AHB) Interface Reset slcr.USB_RST_CTRL [USBx_CPU1X_RST] usb.USBCMD [RST] (partial controller reset) OTG mode Auto-Reset Hardware Assistance usb.
Chapter 15: USB Host, Device, and OTG Controller 15.16 I/O Interfaces The controller has multiple I/O interfaces including the main ULPI that interfaces via MIO to the external PHY and the port indicator and power signals via EMIO. The routing of the ULPI through the MIO must be programmed. The routing of the signals through the EMIO is always available to logic in the PL that can route these signals to the SelectIO pins. 15.16.
Chapter 15: USB Host, Device, and OTG Controller Example: Program I/O for Controller 1 These steps configure the USB controller 1 onto MIO pins 40 to 51. 1. Configure MIO pins 40, 44 - 47 and 49 -51 for data I/O. Write to the associated slcr registers, MIO_PIN_{40, 44-47}: a. Route USB ULPI data signal to I/O buffer. b. 3-state controlled by USB controller (TRI_ENABLE = 0). c. LVCMOS18 (refer to the register definition for other voltage options). d. Slow CMOS edge. 2. e.
Chapter 15: Table 15-50: USB Host, Device, and OTG Controller USB ULPI Signals on MIO MIO Pins USB Port Signals USB 0 USB 1 Default Input Value to Controller I/O Name USB{0,1}_ULPI_DATA4 ~ Transmit and receive data 4 28 40 IO Data bus direction control 29 41 I USB{0,1}_ULPI_DIR 0 Stop the Transfer (end/interrupt) 30 42 O USB{0,1}_ULPI_STP ~ Data flow control signal 31 43 I USB{0,1}_ULPI_NXT 0 Transmit and receive data 0 32 44 IO USB{0,1}_ULPI_DATA0 ~ Transmit and receiv
Chapter 16 Gigabit Ethernet Controller 16.1 Introduction The Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC compatible with the IEEE 802.3-2008 standard capable of operating in either half or full duplex mode at all three speeds. The PS is equipped with two Gigabit Ethernet Controllers. Each controller can be configured independently. To access pins via MIO, each controller uses an RGMII interface (to save pins).
Chapter 16: Gigabit Ethernet Controller 16.1.1 Block Diagram A block diagram of one Ethernet controller is shown in Figure 16-1.
Chapter 16: Gigabit Ethernet Controller • Address checking logic for four specific 48-bit addresses, four type ID values, promiscuous mode, hash matching of unicast and multicast destination addresses and Wake-on-LAN • 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames • Supports Ethernet loopback mode • IPv4 and IPv6 transmit and receive IP, TCP and UDP checksum offload • Recognition of 1588 rev. 2 PTP frames • Statistics counter registers for RMON/MIB 16.1.
Chapter 16: Gigabit Ethernet Controller 16.1.
Chapter 16: Gigabit Ethernet Controller 16.
Chapter 16: Gigabit Ethernet Controller The back off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error is indicated and no further attempts are made if 16 consecutive attempts cause a collision.
Chapter 16: Gigabit Ethernet Controller of the receiver descriptor word 1 is updated to indicate the FCS validity for the particular frame. This is useful for applications where individual frames with FCS errors must be identified. Received frames can be checked for length field error by setting the length field error frame discard bit of the Network Configuration register (bit [16]).
Chapter 16: Gigabit Ethernet Controller [23]) in the receive buffer descriptor status are set indicating which type ID register generated the match, if the receive checksum offload is disabled. The reset state of the type ID registers is zero, hence each is initially disabled.
Chapter 16: Gigabit Ethernet Controller hash_index[05] = da[05]°^°da[11]°^°da[17]°^°da[23]°^°da[29]°^°da[35]°^°da[41]°^°da[47] hash_index[04] = da[04]°^°da[10]°^°da[16]°^°da[22]°^°da[28]°^°da[34]°^°da[40]°^°da[46] hash_index[03] = da[03]°^°da[09]°^°da[15]°^°da[21]°^°da[27]°^°da[33]°^°da[39]°^°da[45] hash_index[02] = da[02]°^°da[08]°^°da[14]°^°da[20]°^°da[26]°^°da[32]°^°da[38]°^°da[44] hash_index[01] = da[01]°^°da[07]°^°da[13]°^°da[19]°^°da[25]°^°da[31]°^°da[37]°^°da[43] hash_index[00] = da[00]°^°da[06]°^°
Chapter 16: Gigabit Ethernet Controller The following bits in the receive buffer descriptor status word provide information about VLAN tagged frames: • Bit [21] set if receive frame is VLAN tagged (i.e. type id of 0x8100). • Bit [20] set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit [20] is set bit [21] is also set). • Bits [19], [18] and [17] set to priority if bit [21] is set. • Bit [16] set to CFI if bit [21] is set.
Chapter 16: Gigabit Ethernet Controller • The frame has an ARP operation field of 0x0001 (bytes 21 and 22) • The least significant 16 bits of the frame's ARP target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the Wake-on-LAN register The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake-on-LAN target address value does not cause an ARP request event, even if matched by the frame.
Chapter 16: Gigabit Ethernet Controller DMA Controller The DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AHB memory space. The DMA controller performs four types of operation on the AHB bus.
Chapter 16: Table 16-2: Gigabit Ethernet Controller Rx Buffer Descriptor Entry (Cont’d) Bit Function Word 1 31 Global all ones broadcast address detected. 30 Multicast hash match. 29 Unicast hash match. 28 Reserved. 27 Specific address register match found,. bit 25 and bit 26 indicate which specific address register causes the match. 26:25 Specific address register match.
Chapter 16: Table 16-2: Gigabit Ethernet Controller Rx Buffer Descriptor Entry (Cont’d) Bit Function 14 Start of frame – when set the buffer contains the start of a frame. If both bits 15 and 14 are set, the buffer contains a whole frame. 13 This bit has a different meaning depending on whether ignore FCS mode are enabled. This bit is zero if ignore FCS mode is disabled. With ignore FCS mode enabled: (bit [26] set in Network Configuration Register).
Chapter 16: Gigabit Ethernet Controller Only good received frames are written out of the DMA, so no fragments exist in the AHB buffers due to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame.
Chapter 16: Gigabit Ethernet Controller To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits [31:0] in the first word of each descriptor list entry. The second word of the transmit-buffer descriptor is initialized with control information that indicates the length of the frame, whether or not the MAC is to append CRC, and whether the buffer is the last buffer in the frame.
Chapter 16: Table 16-3: Gigabit Ethernet Controller Tx Buffer Descriptor Entry Bit Function Word 0 31:0 Byte address of buffer. Word 1 31 Used – must be zero for the controller to read data to the transmit buffer. The controller sets this to one for the first buffer of a frame once it has been successfully transmitted. Software must clear this bit before the buffer can be used again. 30 Wrap – marks last descriptor in transmit buffer descriptor list.
Chapter 16: Gigabit Ethernet Controller DMA Bursting on the AHB The DMA always uses SINGLE, or INCR type AHB accesses for buffer management operations. When performing data transfers, the AHB burst length used can be programmed using bits [4:0] of the DMA Configuration register so that either SINGLE, INCR or fixed length incrementing bursts (INCR4, INCR8 or INCR16) are used where possible. When there is enough space and enough data to be transferred, the programmed fixed length bursts are used.
Chapter 16: Gigabit Ethernet Controller X-Ref Target - Figure 16-3 MIO or EMIO Gigabit Ethernet Controller MAC Transmitter TX Packet Buffer DPSRAM TX Packet Buffer Interconnect APB TX DMA Status and Statistic Registers Register Interface Control Registers Interconnect AHB DMA AHB RX DMA MIO or EMIO MDIO TX GMII RX Packet Buffer RX Packet Buffer DPSRAM MIO or EMIO MAC Receive RX GMII Frame Filtering UG585_c16_03_101812 Figure 16-3: Zynq-7000 AP SoC Technical Reference Manual UG585 (v1
Chapter 16: Gigabit Ethernet Controller In the transmit direction, the DMA continues to fetch packet data up to a limit of 256 packets, or until the buffer is full. The size of the buffer has a maximum usable size of 4 KB. In the receive direction, if the buffer becomes full, then an overflow occur.s An overflow also occurs if the limit of 256 packets is breached. The size of the external buffer has a maximum usable size of 4 KB.
Chapter 16: Gigabit Ethernet Controller Other than underflow, the only MAC related errors that can occur are due to collisions during half duplex transmissions. When a collision occurs the frame still exists in the packet buffer memory so it can be retried directly from there. Only when the MAC transmitter has failed to transmit after sixteen attempts is the frame finally flushed from the packet buffer.
Chapter 16: Gigabit Ethernet Controller Rx Checksum Offload When receive checksum offloading is enabled, the IPv4 header checksum is checked per RFC 791, where the packet meets the following criteria: • If present, the VLAN header must be four octets long and the CFI bit must not be set • Encapsulation must be RFC 894 Ethernet Type encoding or RFC 1042 SNAP encoding • IPv4 packet • IP header is of a valid length The controller also checks the TCP checksum per RFC 793, or the UDP checksum per RFC 7
Chapter 16: Gigabit Ethernet Controller If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20] of the transmitter DMA writeback status are updated to identify the reason for the error. Note that the frame is still transmitted but without the checksum substitution, as typically the reason that the substitution did not occur was that the protocol was not recognized. 16.2.
Chapter 16: • Gigabit Ethernet Controller 1588 version 2 (Ethernet multicast) Note: Only multicast packets are supported. The TSU consists of a timer and registers to capture the time at which PTP event frames cross the message timestamp point. These are accessible through the APB interface. An interrupt is issued when a capture register is updated.
Chapter 16: Gigabit Ethernet Controller One Pulse per Second Output Because there is no hardware access to the counter value, it is not possible to provide a 1 pps signal that is commonly used for lab tests of the synchronization accuracy. Event Scheduling The MAC does not provide event scheduling capability such as generating an interrupt upon the counter reaching a specific value.
Chapter 16: Gigabit Ethernet Controller with its timestamp (for both transmit and receive), and make it available to software, for example via FIFOs or via circular buffers in main memory. Such a function can be implemented in the PL along with the timestamp unit as described above. However, implementation requires access to the packet data stream itself. In order to have access to the packet data stream, the controller needs to be pinned-out through the EMIO using GMII, instead of MIO.
Chapter 16: Gigabit Ethernet Controller Pause frames that have FCS or other errors are treated as invalid and are discarded. 802.3 Pause frames that are received after priority based flow control (PFC) has been negotiated are also discarded. Valid pause frames received increment the Pause Frames Received Statistic register. The Pause Time register decrements every 512 bit times once transmission has stopped.
Chapter 16: Gigabit Ethernet Controller Pause frames can also be transmitted by the MAC using normal frame transmission methods. MAC PFC Priority Based Pause Frame Support Note: Refer to the 802.1Qbb standard for a full description of priority based pause operation. The controller supports PFC priority based pause transmission and reception. Before PFC pause frames can be received, bit 16 of the Network Control register must be set. The start of a PFC pause frame is shown in Table 16-5.
Chapter 16: Gigabit Ethernet Controller register) which causes the Pause Time register to decrement every rx_clk cycle once transmission has stopped. The interrupt (bit [13] in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit [13] in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received.
Chapter 16: Gigabit Ethernet Controller After transmission, a pause frame transmitted interrupt is generated (bit 14 of the Interrupt Status register) and the only statistics register that is incremented is the Pause Frames Transmitted register. PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods. 16.3 Programming Guide The controller functionality is described in detail in section 16.2 Functional Description and Programming Model.
Chapter 16: Gigabit Ethernet Controller 16.3.2 Configure the Controller The following example describes a typical programming sequence for configuration of the controller. Refer to Appendix B, Register Details for further details on the Controller registers. 1. Program the Network Configuration register (gem.net_cfg). The network configuration register is used to set the mode of operation. Examples: a. Enable Full Duplex. Write a 1 to the gem.net_cfg[full_duplex] register. b. Enable Gigabit mode.
Chapter 16: Gigabit Ethernet Controller 16.3.3 I/O Configuration The block diagram in section 16.1.1 Block Diagram describes the connection details of the Gigabit Ethernet Controller to the external network. Gigabit Ethernet Controller using MIO The controller provides an RGMII interface through the MIO. Pins 16-27 are used for Controller 0 and 28-39 for Controller 1. Refer to section 16.6 Signals and I/O Connections for more information on the pin-out.
Chapter 16: Gigabit Ethernet Controller Gigabit Ethernet Controller using EMIO The EMIO interface allows for derivation of other physical MII interfaces using appropriate shim-logic in the PL. The Controller provides a GMII interface through the EMIO. Example: Configure Controllers for EMIO 1. Unlock the SLCR module. Write a value of 0xDF0D to the slcr.SLCR_UNLOCK register. 2. Enable the level shifters for PS user inputs to FPGA in FPGA tile 1. Write a value of 0b11 to bit slcr.
Chapter 16: Gigabit Ethernet Controller The MDC must not exceed 2.5 MHz as defined by the IEEE802.3 standard. The gem.net_cfg[mdc_clk_div] bits are used to set the divisor for the CPU_1x clock. Example: Consider a case with the CPU clock set to 666.667 MHz clock and the available CPU_1x clock is 111.11 MHz. The clock divisor, in this case should be set to 48 (0b011) in gem.net_cfg[mdc_clk_div] to set the maximum possible frequency of 2.314 MHz for the MDC.
Chapter 16: Gigabit Ethernet Controller X-Ref Target - Figure 16-4 Rx Descripter List Rx Buffers Rx Buffer Queue Pointer MAC Register List in Main Memory Buffer in Main Memory UG585_c16_04_022712 Figure 16-4: Rx Buffer Queue Structure To create this list of buffers: 1. Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in the DMA Configuration register.
Chapter 16: Gigabit Ethernet Controller The Transmit Buffer Queue Pointer register (gem.tx_qbar) register points to this data structure. To create this list of buffer descriptors with N entries: 1. Each buffer descriptor is 8 bytes in length. Hence allocate an area of 8N bytes for the transmit buffer descriptor list in system memory which creates N entries in this list.
Chapter 16: Gigabit Ethernet Controller 16.3.8 Transmitting Frames Example: Transmitting a Frame 1. Allocate buffers in system memory to contain the Ethernet frame. GigE supports scatter-gather functionality; hence an Ethernet frame can be split into multiple buffers with each buffer processed by a buffer descriptor. 2. Write the Ethernet frame data in the allocated buffers.
Chapter 16: Gigabit Ethernet Controller • The received frame's type/length field matches one of the four type ID registers. The available type id registers are gem.type_id_match{1:4}. This is applicable for cases where Ethernet type/length field based filtering is required. • Unicast or Multicast hash is enabled through gem.net_cfg[uni_hash_en] or gem.net_cfg[multi_hash_en] register bits, then the received frame is accepted only if the hash is matched.
Chapter 16: Table 16-6: Gigabit Ethernet Controller RX Status Errors Error Condition Necessary Action Hresp not OK This is a condition from which the controller cannot recover easily. Re-initialize the controller and buffer descriptors for receive and transmit paths after clearing the relevant register status bits: gem.rx_status[hresp_not_ok] and gem.intr_status[hresp_not_ok].
Chapter 16: Gigabit Ethernet Controller 16.4 IEEE 1588 Time Stamping 16.4.1 Overview Refer to the IEEE 1588 standard specification for more information on the protocol and section 16.2.7 IEEE 1588 Time Stamp Unit for more information on the implementation of the Timestamp Unit. The following section briefly reviews the essential terms prior to discussion of the programming model. The PTP system deals with the following different entities: • A grandmaster clock.
Chapter 16: • Gigabit Ethernet Controller Each PTP message is identified with a message Type which is a 4 bit field in the PTP message header. Message Types are identified in Table 16-8 Table 16-8: Message Types PTP Frames Message Type Sync 0x0 Delay_Req 0x1 PDelay_Req 0x2 PDelay_Resp 0x3 Follow_up 0x8 Delay_Resp 0x9 PDelay_Resp_Follow_Up 0xA Announce 0xB Management 0xC Signaling 0xD • The versionPTP field signifies which PTP version is being used – PTPv1 or PTPv2.
Chapter 16: 2. Best master clock algorithm (BMCA) 3. PTP packet handling at the master port 4. PTP packet handling at the slave port Gigabit Ethernet Controller Notes: 1. The following sections do not describe the handling of management and signaling frames because they are not integral to the implementation of the core PTP functionality. 2. The illustrations in these sections do not describe an implementation-specific mechanism to change clock attributes dynamically. 3.
Chapter 16: Gigabit Ethernet Controller Example: Master Clock Port 1. Initiate a transmission of Sync and Announce frames at pre-defined intervals. 2. Initiate a transmission of PDelay_Req frames at regular intervals. Example: Slave Clock Port 1. Initiate a transmission of PDelay_Req frames at regular intervals. 2. Wait for Sync frame for a predefined interval of time. If a Sync timeout occurs, change to become a PTP master. 3. Wait for an Announce frame for a pre-defined interval of time.
Chapter 16: Gigabit Ethernet Controller Example: BMCA 1. Compare the fields of the Announce frame received with that of the current grandmaster starting with Priority1, progressing to the next field in the event of a tie. 2. The one with a higher priority becomes the new grandmaster. 16.4.4 PTP Packet Handling at the Master Refer to IEEE 1588 Standard Specification for more information on packet formats and protocol. 1. Form and send Sync frames at regular intervals.
Chapter 16: Gigabit Ethernet Controller Note: Since the PTP message first travels through the external PHY before being time stamped at the MII interface by the hardware, for calculating the exact time stamp for the received packet, the delay introduced by the external PHY must be subtracted from the hardware reported time stamp to reach at the exact time stamp. 8. Read the time stamp for the PDelay_Req frame received at the slave (peer).
Chapter 16: Gigabit Ethernet Controller 16.4.5 PTP Packet Handling at the Slave Refer to IEEE 1588 Standard Specification for more information on packet formats and protocol. 1. Calculate the peer delay as described in steps 5-9 in section 16.4.4 PTP Packet Handling at the Master. Note: When the slave sends timestamps, the delays introduced by the external PHY at the slave clock port should be taken care of. 2. Read and store timestamp for the received Sync frame.
Chapter 16: Table 16-9: Gigabit Ethernet Controller Ethernet Control Register Overview Function Register Name Description MAC Configuration net_{cfg,ctrl,status} tx_pauseq rx_pauseq tx_pfc_pause ipg_stretch stacked_vlan Network control, configuration and status. Rx, Tx Pause clocks. IPG stretch. DMA Unit tx_status rx_status tx_qbar rx_qbar dma_cfg Control. Receive, Transmit Status. Receive, Transmit Queue Base Address Control.
Chapter 16: Table 16-10: Gigabit Ethernet Controller Ethernet Status and Statistics Register Overview Function Frame Tx Statistics Hardware Register Name Description frames_tx broadcast_frames_tx multi_frames_tx Error-free Tx frame, pause frame counts and bytes counts. frames_64b_tx frames_65to127b_tx frames_128to255b_tx frames_256to511b_tx frames_512to1023b_tx frames_1024to1518b_tx Error-free frames transmitted: totals by size. octets_tx_{top,bot} Octets transmitted.
Chapter 16: Gigabit Ethernet Controller 16.6 Signals and I/O Connections 16.6.1 MIO–EMIO Interface Routing The I/O interface is routed to the MIO for RGMII, and to the EMIO for GMII/MII connectivity. The PL can modify the GMII/MII interface from the MAC to construct other Ethernet interfaces that connect to external devices via PL pins. The routing of the Ethernet communications signals are shown in Figure 16-6.
Chapter 16: Gigabit Ethernet Controller 16.6.4 RGMII Interface via MIO An example Ethernet communications wiring connection is shown in Figure 16-7 X-Ref Target - Figure 16-7 ENET_RGMII_TX_CLK ENET_RGMII_TXD[3:0] MDI 0 P/N ENET_RGMII_TX_CTL RGMII MDI 1 P/N ENET_RGMII_RX_CLK Ethernet Controller MIO Multiplexer External PHY Device ENET_RGMII_RXD[3:0] MD RJ-45 Conn.
Chapter 16: Table 16-11: Gigabit Ethernet Controller Ethernet RGMII Interface Signals via MIO Pins (Cont’d) Controller Signal MIO Pins Default Controller Input Value GigE 0 GigE 1 Rx data 2 from PHY 0 25 37 RGMII_RX_D2 I Rx data 3 from PHY 0 26 38 RGMII_RX_D3 I Signal Description Name I/O 16.6.5 GMII/MII Interface via EMIO An example illustrating the GMII interface connections through the PL to the PL pins is shown in Figure 16-8.
Chapter 16: Table 16-12: Gigabit Ethernet Controller Ethernet GMII/MII Interface Signals via EMIO Interface (Cont’d) EMIO Interface Signals Reference Clock Default Controller Input Value Tx Enable Tx Clk ~ EMIOENET[1,0]GMIITXEN O Tx Error Tx Clk ~ EMIOENET[1,0]GMIITXER O Tx Start-of-Frame Tx Clk ~ EMIOENET[1,0]SOFTX O Tx PTP delay req frame detected Tx Clk ~ EMIOENET[1,0]PTPDELAYREQTX O Tx PTP peer delay frame detect Tx Clk ~ EMIOENET[1,0]PTPPDELAYREQTX O Tx PTP pear delay res
Chapter 16: Gigabit Ethernet Controller 16.6.7 MIO Pin Considerations LVCMOS33 is not supported for the RGMII interface. Recommendation is to use 1.8/2.5V I/O standards. 16.7 Known Issues 1. On TX, GigE needs multiple descriptors with the last descriptor in the BD ring having the used bit set. It is needed to ensure the GigE does not wrap and attempt to transmit the same frames more than once.
Chapter 16: Gigabit Ethernet Controller eventually overflows an 8-bit internal counter in the GigE Rx module used to track the number of packets in the Rx buffer needing a "read out." Once the 8-bit counter overflows, it leads to corruption of local fill level counters in the GigE, which results in a deadlock on the Rx path. The chances of running into this issue is very high if GigE is subjected to a heavy Rx traffic condition with small-sized packets. A typical example could be small-sized UDP packets.
Chapter 17 SPI Controller 17.1 Introduction The SPI bus controller enables communications with a variety of peripherals such as memories, temperature sensors, pressure sensors, analog converters, real-time clocks, displays, and any SD card with serial mode support. The SPI controller can function in master mode, slave mode or multi-master mode. The Zynq-7000 devices include two SPI controllers. The controller is based on the Cadence SPI core.
Chapter 17: SPI Controller 17.1.
Chapter 17: SPI Controller 17.1.2 System Viewpoint The system viewpoint diagram of the SPI controller is shown in Figure 17-1.
Chapter 17: SPI Controller 17.1.3 Block Diagram A functional block diagram of the SPI controller is shown in Figure 17-2.
Chapter 17: SPI Controller Tx and Rx FIFOs Each FIFO is 128 bytes. Software reads and writes these FIFOs using the register mapped data port registers. FIFO management for master mode is described in 17.3.3 Master Mode Data Transfer and for slave mode in 17.3.4 Slave Mode Data Transfer. The FIFOs bridge two clock domains; APB interface and the controller’s SPI_Ref_Clk. Software writes to the TxFIFO in the APB clock domain and the controller reads the TxFIFO in the SPI_Ref_Clk domain.
Chapter 17: SPI Controller 17.2 Functional Description • 17.2.1 Master Mode • 17.2.2 Multi-Master Capability • 17.2.3 Slave Mode • 17.2.4 FIFOs • 17.2.5 FIFO Interrupts • 17.2.6 Interrupt Register Bits, Logic Flow • 17.2.7 SPI-to-SPI Connection 17.2.1 Master Mode In master mode, the SPI I/O interface can transmit data to a slave or initiate a transfer to receive data from a slave. The controller selects one slave device at the time using one of the three slave select lines.
Chapter 17: Table 17-1: SPI Controller SPI Master Mode SS and Start Modes (Cont’d) Slave Select Control Auto SS (controller) Data Transfer Start Control Manual Manual Start Slave Enable & Select Command Operation Manual Start 0 1 Controller hardware controls the slave select, but the software must issue the start command to serialize data in the TxFIFO. This mode is applicable for specific use cases such as sending small chunks of data that fit into the SPI controller FIFO.
Chapter 17: SPI Controller Command Software starts a manual transfer by writing a 1 to the spi.Config_reg0 [Man_start_com] bit. When the software writes the 1, the controller hardware starts the data transfer and transfers all the data bytes present in the TxFIFO. The [Man_start_com] bit is self-clearing. Writing a 1 to this bit is ignored if [Man_start_en] = 0. Writing a 0 to [Man_start_com] has no effect, regardless of mode. 17.2.
Chapter 17: SPI Controller • Detection when Controller is enabled: If the controller is enabled (from a disabled state) at a time when SS is Low (active), the controller will ignore the data and wait for the SCLK to be inactive (a word boundary) before capturing data. The controller counts SCLK inactivity in the SPI_Ref_Clk domain. A new word is assumed when the SCLK idle count reaches the value programmed into the [Slave_Idle_coun] bit field.
Chapter 17: SPI Controller 17.2.5 FIFO Interrupts The Rx and Tx FIFO interrupts are illustrated in Figure 17-3. X-Ref Target - Figure 17-3 RxFIFO (128 bytes) TxFIFO (128 bytes) Overflow Interrupt Full Interrupt [RX_OVERFLOW] [TX_FIFO_full] Full Interrupt [RX_FIFO_full] Not Full = 0 (full) TxFIFO Threshold spi.TX_thres_reg0 Not Full Interrupt [TX_FIFO_not_full] Not Empty = 1 Not Full = 1 Not Empty Interrupt [RX_FIFO_not_empty] RxFIFO Threshold spi.
Chapter 17: SPI Controller 17.2.7 SPI-to-SPI Connection The I/O signals of the two SPI controller in the PC are connected together signals when the slcr.MIO_LOOPBACK [SPI_LOOP_SPI1] bit is set = 1. In this mode, the clock, slave select, MISO, and MOSI signals from one controller are connected to the other controller’s clock, slave, MISO, and MOSI signals. respectively. 17.3 Programming Guide • 17.3.1 Start-up Sequence • 17.3.2 Controller Configuration • 17.3.3 Master Mode Data Transfer • 17.3.
Chapter 17: • Set Mode fail generation, [Modefail_gen_en], for multi-master mode systems. • Set SS to 0b1111 to de-assert all the slave selects before the start of transfers. SPI Controller Example: SPI 0 Configuration for Master Mode This example uses a single chip select, a baud rate of 12.5 Mb/s, a clock phase set to inactive, and a clock polarity of quiescent High. 1. Configure the controller: Write 0x0002_FC0F to the spi.Config_reg register. a. De-assert all chip selects (for now): [CS] = 1111.
Chapter 17: 9. SPI Controller Interrupt handler: Transfer any additional data to the slave the required data to SPI slave using the interrupt handler. 10. Disable interrupts: Write 0x27 to the spi.Intrpt_dis_reg to disable RxFIFO full, RxFIFO overlflow, TxFIFO empty, and fault conditions. 11. Disable the controller: Set spi.En_reg0 [SPI_EN] = 0. 12. De-assert slave select: Set spi.Config_reg0 [CS] = 1111. Example: Master Mode – Manual SS and Auto Start 1. Enable manual SS: Write 1 to spi.
Chapter 17: SPI Controller 6. Enable the interrupts: Write 0x27 to spi.Intrpt_en_reg to enable RxFIFO full, RxFIFO overflow, TxFIFO empty, and fault conditions. 7. Start the data transfer: Set spi.Config_reg0 [Man_start_com] = 1. 8. Interrupt handler: Transfer any additional data to the slave the required data to SPI slave using the interrupt handler. 9. Disable interrupts: Write 0x27 to the spi.Intrpt_dis_reg to disable RxFIFO full, RxFIFO overlflow, TxFIFO empty, and fault conditions. 10.
Chapter 17: a. 6. SPI Controller Read data from the spi.Rx_Data_reg register. Continue to receive bytes using the data byte counter. Fill the TxFIFO: More data can be written to the TxFIFO, if needed: a. Write data to the spi.Tx_Data_reg0 register. b. Continue to fill data until FIFO depth is reached or there is no further data. c. Increment the data byte counter after each byte is pushed. 7. Check for overflow or underflow: Read the [TX_FIFO_underflow] or [RX_OVERFLOW] status bits.
Chapter 17: SPI Controller 17.4.1 Resets The controller has two reset domains: the APB interface and the controller itself. They can be controlled together or independently. The effects for each reset type are summarized in Table 17-3. Table 17-3: SPI Reset Effects APB Interface TxFIFO and RxFIFO Protocol Engine Registers ABP Interface Reset slcr.SPI_RST_CTRL [SPIx_CPU1X_RST] Yes Yes No Yes PS Reset Subsystem slcr.
Chapter 17: SPI Controller Frequency Ratio Note: The range of the baud rate divider is from a minimum of 4 to a maximum of 256 in binary steps (i.e., divide by 4, 8, 16,... 256). Example: SCLK for Master Mode This example shows how to program the SPI_Ref_Clk to 100 MHz and the SCLK to 25 MHz. The example assumes the I/O PLL is at 1,000 MHz. The CPU_1x clock frequency must be less than 100 MHz. 1. Program SPI_Ref_Clk: Select PLL source, divisors and enable: Write 0x0000_0A01 to the slcr.
Chapter 17: SPI Controller The clock phase parameter defines the state of the SS between words and the state of SCLK when the controller is not transmitting bits. The phase and polarity parameters are summarized in Table 17-4 and illustrated in Figure 17-5.
Chapter 17: SPI Controller X-Ref Target - Figure 17-5 CLK_PH = 0 SCLK SS MOSI 0 1 2 3 4 5 6 7 MISO 0 1 2 3 4 5 6 7 CLK_PH = 1 SCLK SS MOSI 0 1 2 3 4 5 MISO 0 1 2 3 4 5 6 7 6 7 UG585_c17_05_022613 Figure 17-5: SPI I/O Signal Waveforms for Clock Phase and Polarity 17.5.2 Back-to-Back Transfers (See Figure 17-6.) Slave Mode Requirements In slave mode, the controller can accept back-to-back transfers.
Chapter 17: SPI Controller X-Ref Target - Figure 17-6 CLK_PH = 0 MOSI MISO Word 0 Word 1 Word 2 Word 3 Word 0 Word 1 Word 2 Word 3 SS CLK_PH = 1 MOSI MISO SS UG585_c17_06_022613 Figure 17-6: SPI Back-to-Back Transfers 17.5.3 MIO/EMIO Routing The SPI interface signals can be routed either through the MIO pins or the EMIO interface. When the system is reset (e.g., PS_POR_B, PS_SRST_B and other methods), all of the I/O signals are routed to the EMIO interface by default.
Chapter 17: 2. SPI Controller Configure MIO pins 17 for MISO input. Write 0x0000_02A0 to each of the slcr.MIO_PIN_17 register. a. Route SPI 0 MISO to pin 17. b. Disable output. [TRI_ENABLE] = 1. c. LVCMOS18: [IO_TYPE] = 001. d. Slow CMOS drive edge. 3. e. Disable internal pull-up resistor. f. Disable HSTL receiver. Configure MIO pin 18, 19 and/or 20 for Slave Select outputs. Write 0x0000_32A0 to the slcr.MIO_PIN_18, 19 and/or 20 registers. The internal pull-up is enabled. a.
Chapter 17: SPI Controller Master Mode via MIO X-Ref Target - Figure 17-7 Zynq-7000 AP SoC External Devices MIO SCLK MOSI SPI Master Controller SCLK MOSI MISO Slave 0 MISO SS0 SS0 SS1 SS2 Slave 1 Connect up to 3 slave devices (directly). For one slave device, connect it to any of the slave selects. SS1 Slave 2 SS2 Device Boundary UG585_c17_07_102214 Figure 17-7: SPI Master Mode Wiring Diagram via MIO IMPORTANT: When using MIO pins always use SS0.
Chapter 17: SPI Controller Master Mode via EMIO X-Ref Target - Figure 17-8 I/O Select PL EMIO EMIO SPI x SCLKO SCLK EMIO SPI x SCLKTN PS IOP EMIO SPI x SCLKI EMIO SPI x MO MOSI EMIO SPI x MOTN SPI Master Controller EMIO SPI x SI EMIO SPI x MI EMIO SPI x SOTN EMIO SPI x SO MISO nc nc EMIO SPI x SSNTN EMIO SPI x SSON 0 SS 0 EMIO SPI x SSON 1 SS 1 EMIO SPI x SSON 2 SS 2 EMIO SPI x SSIN Device Boundary UG585_c17_08_022613 Figure 17-8: SPI Master Mode Wiring Diagram via EMIO IMPORTANT: When
Chapter 17: SPI Controller Slave Mode via MIO X-Ref Target - Figure 17-9 Zynq-7000 AP SoC External Master Device MIO SCLK SCLK MOSI SPI Slave Controller MOSI MISO SCLK MOSI MISO MISO SS 0 SS a SS b SS c SS d SS 0 SS 1 nc SS 2 nc Other External Slave Devices Device Boundary UG585_c17_09_022613 Figure 17-9: SPI Slave Mode Wiring Diagram via MIO 17.5.5 MIO/EMIO Signal Tables The SPI I/O interface signals routing has some options. The routing options include multiple positions in the MIO pins.
Chapter 17: Table 17-5: SPI Controller SPI MIO Pins Slave or Master Mode SPI Signals SPI Interface I/O Master Mode Clock MOSI MISO SS 0 SS 1 SS 2 Signal Type IO IO IO IO O O Controller Default Input Value 0 0 0 1 ~ ~ SPI 0, choice 1 16 21 17 18 19 20 SPI 0, choice 2 28 33 29 30 31 32 SPI 0, choice 3 40 45 41 42 43 44 SPI 1, choice 1 12 10 11 13 14 15 SPI 1, choice 2 24 22 23 25 26 27 SPI 1, choice 3 36 34 35 37 38 39 SPI 1, choice 4 48 4
Chapter 18 CAN Controller 18.1 Introduction This chapter describes the architecture and features of the CAN controllers and the functions of the various registers in the design. There are two nearly identical CAN controllers in the PS that are independently operable. Defining the CAN protocol is outside the scope of this document, and knowledge of the specifications is assumed. 18.1.1 Features CAN Controller features are summarized as follows: • Compatible with the ISO 11898 -1, CAN 2.0A, and CAN 2.
Chapter 18: CAN Controller 18.1.2 System Viewpoint The system viewpoint of the CAN controller is shown in Figure 18-1. X-Ref Target - Figure 18-1 MIO – EMIO Routing IRQ ID# {60, 83} Interconnect CAN Controllers Slave port APB Tx, Rx Tx, Rx EMIO PL Tx, Rx CAN{0, 1} CPU_1x clock CAN{0, 1} CPU_1x reset Control Registers MIO Pins Clock CAN{0, 1} REF clock External Clock Source Clocking Device Boundary UG585_c18_01_071612 Figure 18-1: CAN Controller System Viewpoint 18.1.
Chapter 18: CAN Controller Configuration Registers The CAN Controller Configuration register defines the configuration registers. This module allows for read and write access to the registers through the APB interface. An overview of the CAN controller registers are shown in section 18.3.8 Register Overview. Transmit and Receive Messages Separate storage buffers exist for transmit (TxFIFO) and receive (RxFIFO) messages through a FIFO structure. Each buffer can store up to 64 messages.
Chapter 18: CAN Controller 18.2 Functional Description Each controller is independently configured and controlled. There are two CAN controllers (CANx; where x = 0 or 1). The register name preface for the CAN registers is 'can' (e.g., can.MSR register). 18.2.
Chapter 18: CAN Controller TxHPB. When the controller exits sleep mode, can.MSR[SLEEP] is set to 0 by the hardware and an interrupt can be generated. The CAN controller enters Sleep mode from Configuration mode when the LBACK bit in MSR is 0, the SLEEP bit in MSR is 1, and the CEN bit in SRR is 1. The CAN controller enters Sleep mode only when there are no pending transmission requests from either the TX FIFO or the TX High Priority Buffer.
Chapter 18: • CAN Controller Set can.SRR[CEN] = 1 To enter sleep mode from normal mode (interrupt generated): • Set can.MSR[SLEEP] = 1 Events that cause the controller to exit sleep mode (interrupt generated): • Rx signal activity (hardware sets can.MSR[SLEEP] = 0) • TxFIFO or TxHPB activity (hardware sets can.MSR[SLEEP] = 0) • Software writes 0 to can.MSR[SLEEP] X-Ref Target - Figure 18-3 Reset: slcr.CAN_RST_CTRL[CANx_CPU1x_RST] =1 OR can.SRR[SRST] = 1 (Self-clearing) Hardware Forces can.
Chapter 18: Table 18-1: CAN Controller CAN Controller Modes of Operation (Cont’d) Software Reset Mode Select Register Status Register (SR) CAN Register (can.
Chapter 18: CAN Controller Reads Data starts at byte 0 and continues for the number of counts in DLC. Software should read both data words, but the only valid bytes are determined by DLC. Table 18-3 provides bit descriptions for the identifier word bits, the DLC word bits, and data word 1 and data word 2 bits. Table 18-3: CAN Message Word Register Bit Fields Bits Name Default Value Description 0 Standard Message ID The identifier portion for a standard frame is 11 bits.
Chapter 18: Table 18-3: CAN Controller CAN Message Word Register Bit Fields (Cont’d) Bits Name Default Value 27-0 Reserved 0 Reads from this field return 0s. Writes to this field should be 0s.
Chapter 18: CAN Controller Tx Messages The controller has a configurable TxFIFO that software can use buffer up to 64 Tx CAN messages. The controller also has a high priority transmit buffer (Tx HPB), with storage for one message. When a higher priority message needs to be sent, software writes the message to the high priority transmit buffer when it is available. The message in the TxHPB has higher priority over messages in the TxFIFO.
Chapter 18: CAN Controller 18.2.4 Interrupts Each CAN controller has a single interrupt signal to the GIC interrupt controller. CAN 0 connects to IRQ ID#60 and CAN 1 connects to ID #83. The source of an interrupt can be grouped into one of the following: • TxFIFO and TxHPB • RxFIFO • Message passing and arbitration • Sleep mode and bus off Enable and disable interrupts using the can.IER register. Check the raw status of the interrupt using can.ISR. Clear interrupts by writing a 1 to can.ICR.
Chapter 18: Table 18-4: CAN Controller List of CAN Status and Interrupts Name Bit Number Additional Method to Clear Interrupt Exit Sleep Mode 11 Write 0 to can.SRR[CEN] Bus Off 9 Write 0 to can.SRR[CEN] Usage Controller can go to normal or configuration mode. RxFIFO and TxFIFO Interrupts The FIFO watermark levels and all the FIFO interrupts are illustrated in Figure 18-4, CAN RxFIFO and TxFIFO Watermark Interrupts.
Chapter 18: 3. Clear TxFIFO watermark interrupt. Write a 1 to can.ICR[13]. 4. Read TxFIFO watermark status. Read can.ISR[13]. 5. Enable TxFIFO watermark interrupt. Write a 1 to can.IER[13]. CAN Controller Example: Program TxFIFO Empty Interrupt (14) The following steps can be used to control the TxFIFO empty interrupt: 1. Disable TxFIFO empty interrupt. Write a 1 to can.IER[14]. 2. Clear TxFIFO empty interrupt. Write a 1 to can.ICR[14]. 3. Enable TxFIFO empty interrupt. Write a 1 to can.
Chapter 18: CAN Controller If any of the enabled filters (up to four) satisfy this equation, then the Rx message is stored in the RxFIFO: If (AFMR & Message_ID) == (AFMR & AFIR) then Capture Message Each acceptance filter is independently enabled. The filters are selected by the can.AFR register. • Set can.AFR[UAF4] = 1 to enable AFMR4 and AFID4. • Set can.AFR[UAF3] = 1 to enable AFMR3 and AFID3. • Set can.AFR[UAF2] = 1 to enable AFMR2 and AFID2. • Set can.AFR[UAF1] = 1 to enable AFMR1 and AFID1.
Chapter 18: CAN Controller The user must ensure proper programming of the IDE bit for standard and extended frames. If the user sets the IDE bit in AMIR to 0, then it is considered to be a standard frame ID check only. Example: Program Acceptance Filter Each acceptance filter has its own mask, can.AFMR{1,2,3,4}, and ID register, can.AFIR{1,2,3,4}. 1. Disable acceptance filters. Write 0 to the can.AFR register. 2. Wait for filter to be not busy. Poll on can.SR[ACFBSY] for 0. 3.
Chapter 18: CAN Controller Example: Program the AFMR and AFIR for Extended Frames This example setups up the acceptance filter for extended frames. The Frame ID number is shown to be 0x5DF, but could be set to desired value for the application. 1. Configure filter mask for extended frames. Write 0xFFFF_FFFF to the can.AFMR register: a. Enable the substitute remote transmission request mask for frame, [AMSRR] = 1. b. Compare all bits in the compare for the standard message ID, [AMIDH] = 0x7FF. c.
Chapter 18: CAN Controller Rx/Tx Bit Timing Logic The primary functions of the bit timing logic (BTL) module include: • Generate the Rx sampling clock for the bitstream processor (BSP) • Synchronize the CAN controller to CAN traffic on the bus • Sample the bus and extracting the data stream from the bus during reception • Insert the transmit bit stream onto the bus during transmission The nominal length of the bit time clock period is based on the CAN_REF_CLK clock frequency, the baud rate generat
Chapter 18: CAN Controller tBIT_RATE = tSYNC_SEGMENT + tTIME_SEGMENT1 + tTIME_SEGMENT2 freqBIT_RATE = freqCAN_REF_CLK / ((can.BRPR[BRP] + 1) * (3 + can.BTR[TS1] + can.BTR[TS2])) TIP: A given bit-rate can be achieved with several bit-time configurations, but values should be selected after careful consideration of oscillator tolerances and CAN propagation delays. For more information on CAN bit-time register settings, refer to the CAN 2.0A, CAN 2.0B, and ISO 11898-1 specifications.
Chapter 18: CAN Controller All the controller registers are listed in Table 18-6 and are described in detail in Appendix B, Register Details. 18.3.2 Configuration Mode State The CAN controller enters configuration mode, irrespective of the operation mode, when any of these actions are performed: • Writing a 0 to the CEN bit in the SRR register. • Writing a 1 to the SRST bit in the SRR register. The controller enters Configuration mode immediately following the software reset.
Chapter 18: CAN Controller 18.3.3 Start-up Controller The controller can operate in Normal, Sleep, Snoop and Loop Back modes. Refer to Figure 18-3 for supported transitions. On start-up the controller clocks and configuration bits are programmed. Then the operating mode is selected and enabled. Example: Start-up Sequence 1. Configure clocks. Refer to section 18.4.1 Clocks. 2. Configure Tx/Rx signals. Refer to section 18.5.1 MIO Programming. 3. Wait for configuration mode. Read can.
Chapter 18: CAN Controller 18.3.5 Write Messages to TxFIFO With either option, can.SR[TXFLL] can be polled before writing a message. All messages written to the TxFIFO should follow the format defined in Message Structure. Example: Write Message to TxFIFO Using Polling Method 1. Poll the TxFIFO status. Read can.SR[TXFLL] for 0 and can.SR[TXFEMP] for 1 and then message can be written into the TxFIFO. 2. Write message to TxFIFO. Write to all four data registers (can.TXFIFO_ID, can.TXFIFO_DLC, can.
Chapter 18: CAN Controller Example: Read Message from RxFIFO Using Interrupt Method The can.ISR[RXOK] and/or can.ISR[RXNEMP] bit fields can generate the interrupt. 1. Program RxFIFO watermark level interrupt. Write to can.WIR[FW] to set watermark can.ISR[RXFWMFLL] interrupt. 2. Proceed to step 3 when an interrupt is received. 3. Wait until a message is received. Read can.ISR[RXOK] or can.ISR[RXFWMFLL]. 4. Read message from the RxFIFO. Read all four of the registers (can.RXFIFO_ID, can.
Chapter 18: Table 18-6: CAN Controller CAN Register Overview (Cont’d) Function Register Names (CAN registers, except where noted) Overview Receive FIFO RXFIFO_ID RXFIFO_DLC RXFIFO_DATA1 RXFIFO_DATA2 Read received message. Acceptance Filter AFR AFMR[4:1] AFIR[4:1] Configure and control the four acceptance filters. System level slcr.CAN_CLK_CTRL slcr.CAN_MIOCLK_CTRL slcr.CAN_RST_CTRL A controller reset and clock control. 18.4 System Functions 18.4.
Chapter 18: CAN Controller generator in the PS for both CAN controllers. If an MIO pins is used instead, the selected MIO_PIN Mux register is programmed as an input. Example: Configure and Route Internal Clock for Reference Clock Configure the clock and disable MIO path. Assume the PLL is operating at 1000 MHz and the required CAN reference clock is 24 MHz (23.8095 MHz). 1. Program the clock subsystem. Write 0x0030_0E03 to the slcr.CAN_CLK_CTRL register: a. Enable both CAN reference clocks. b.
Chapter 18: CAN Controller Example: Reset using Local CAN Reset 1. Write to the Local CAN reset register. Write a 1 to can.SRR[SRST] bit field. This bit is self-clearing. Example: Reset using Reset Subsystem 1. Write to the slcr reset register for CAN. Write a 1 then a 0 to the slcr.CAN_RST_CTRL[CANx_CPU1X_RST] bit field. 18.5 I/O Interface 18.5.1 MIO Programming Each set of controller Rx/Tx signals is connected to either MIO pins or the EMIO interface, refer to Table 18-8, page 582.
Chapter 18: Table 18-8: CAN Controller CAN MIO Pins and EMIO Signals Default Controller Input Value Numbers I/O Name I/O CAN 0 Rx 0 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50 I EMIOCAN0PHYRX I CAN 0 Tx ~ 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51 O EMIOCAN0PHYTX O CAN 0 CLK ~ Any MIO pin I ~ ~ CAN 1 Rx 0 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53 I EMIOCAN1PHYRX I CAN 1 Tx ~ 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52 O EMIOCAN1PHYTX O CAN 1 CLK ~ Any MIO pin I
Chapter 19 UART Controller 19.1 Introduction The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. The controller can accommodate automatic parity generation and multi-master detection mode. The UART operations are controlled by the configuration and mode registers. The state of the FIFOs, modem signals and other controller functions are read using the status, interrupt status and modem status registers.
Chapter 19: UART Controller • Loop UART 0 with UART 1 option • Modem control signals: CTS, RTS, DSR, DTR, RI and DCD are available only on the EMIO interface 19.1.2 System Viewpoint The system viewpoint diagram for the UART controllers is shown in Figure 19-1.
Chapter 19: UART Controller 19.2 Functional Description 19.2.1 Block Diagram The block diagram for the UART module is shown in Figure 19-2 X-Ref Target - Figure 19-2 PS AXI Interconnect APB Slave Interface TxFIFO Transmitter RxFIFO Receiver CTS, RTS, DSR, DCD, RI, DTR Control and Status Registers Interrupt Controller (GIC) UART Ref Clock UART TxD Mode Switch UART RxD MIO/EMIO EMIO Interrupts Optional Divide by 8 Baud Rate Generator UG585_c19_02_020613 Figure 19-2: UART Block Diagram 19.
Chapter 19: UART Controller X-Ref Target - Figure 19-3 uart.mode_reg0[0] UART Ref clock Divide by 8 uart.Baud_rate_divider_reg0[7:0] uart.Baud_rate_gen_reg0[15:0] 0 Sel Clk sel_clk 1 CD Programmable Divider BDIV Programmable Divider Rx and Tx Baud rate Baud Sample UG585_c19_03_071912 Figure 19-3: UART Board Rate Generator The baud rate generator can use either the master clock signal, uart_ref_clk, or the master clock divided by eight, uart_ref_clk/8.
Chapter 19: UART Controller values for CD and BDIV. For these examples, a system clock rate of UART_Ref_Clk = 50 MHz and Uart_ref_clk/8 = 6.25 MHz is assumed. The frequency of the UART reference clock can be changed to get a more accurate Baud rate frequency, refer to Chapter 25, Clocks for details to program the UART_Ref_Clk. Table 19-1: UART Parameter Value Examples Clock UART Ref clock Baud Rate Calculated CD Actual CD BDIV Actual Baud Rate Error (BPS) % Error 600 10416.667 10417 7 599.
Chapter 19: UART Controller The transmit module shifts out the start bit, data bits, parity bit, and stop bits as a serial data stream. Data is transmitted, least significant bit first, on the falling edge of the transmit baud clock enable (baud_tx_rate). A typical transmitted data stream is illustrated in Figure 19-4. X-Ref Target - Figure 19-4 baud_tx_rate D0 TXD D1 D2 D3 D4 D5 D6 D7 PA S STOP START UG585_c19_04_020613 Figure 19-4: Transmitted Data Stream The uart.
Chapter 19: UART Controller When a valid start bit is identified, the receiver baud rate clock enable (baud_rx_rate) is re-synchronised so that further sampling of the incoming UART RxD signal occurs around the theoretical mid-point of each bit, as illustrated in Figure 19-6.
Chapter 19: UART Controller If no start bit or reset timeout occurs for 1,023 bit periods, a timeout occurs. The Receiver timeout error bit [TIMEOUT] will be set in the interrupt status register, and the [RSTTO] bit in the Control register should be written with a 1 to restart the timeout counter, which loads the newly programmed timeout value. The upper 8 bits of the counter are reloaded from the value in the [RTO] bit field and the lower 2 bits are initialized to zero.
Chapter 19: UART Controller X-Ref Target - Figure 19-7 TxFIFO Transmit UARTx TxD Mode Switch RxFIFO TxFIFO Transmit Receive UARTx TxD UARTx RxD TxFIFO Transmit Mode Switch RxFIFO Receive UARTx RxD Normal Mode TxFIFO Transmit RxFIFO Receive UARTx TxD Receive UARTx RxD Automatic Echo Mode TxFIFO Transmit Mode Switch RxFIFO UARTx TxD Mode Switch UARTx TxD Mode Switch UARTx RxD RxFIFO Receive UARTx RxD Remote Loopback Mode Local Loopback Mode UG585_c19_13_100512 Figure 19-7:
Chapter 19: UART Controller 19.2.9 UART0-to-UART1 Connection The I/O signals of the two UART controllers in the PS can be connected together. In this mode, the RxD and CTS input signals from one controller are connected to the TxD and RTS output signals of the other UART controller by setting the slcr.LOOP [UA0_LOOP_UA1] bit = 1. The other flow control signals are not connected. This UART-to-UART connection occurs regardless of the MIO-EMIO programming. 19.2.
Chapter 19: UART Controller The interrupt registers and bit fields are summarized in Table 19-2. Table 19-2: UART Interrupt Status Bits Interrupt Register Names and Bit Assignments 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TNFUL TTRIG DMSI TIME OUT PARE FRAME ROVR TFUL TEMPTY RFUL REMPTY RTRIG TACTIVE RACTIVE X X X X X TFUL TEMPTY RFUL REMPTY RTRIG uart.Intrpt_en_reg0 uart.Intrpt_dis_reg0 uart.Intrpt_mask_reg0 uart.Chnl_int_sts_reg0 x x TOVR uart.
Chapter 19: • UART Controller DMSI: indicates a change of logic level on the DCD, DSR, RI or CTS modem flow control signals. This includes High-to-Low and Low-to-High logic transitions on any of these signals. FIFO Interrupts The status bits for the FIFO interrupts listed in Table 19-2 are illustrated in Figure 19-9. These interrupt status bits are in the Channel Status (uart.Channel_sts_reg0) and Channel Interrupt Status (uart.
Chapter 19: UART Controller In automatic flow control mode the request to send output is asserted and de-asserted based on the current fill level of the receiver FIFO, which results in the far-end transmitter pausing transmission and preventing an overflow of the UART receiver FIFO. The FDEL field in the Flow Delay register (Flow_delay_reg0) is used to setup a trigger level on the Receiver FIFO which causes the de-assertion of the request to send.
Chapter 19: UART Controller Select one of the following operating options: Example: Automatic Flow Control 1. Set RTS trigger level. Write to the uart.Flow_Delay_reg0 register. This is the trigger level to de-assert modem signal RTS. 2. Select automatic flow control. Write a 1 to uart.Modem_ctrl_reg0 [FCM]. 3. Verify the mode change to automatic. Read uart.Modem_sts_reg0 [FCMS] until it equals 1. When software writes a 1 to uart.Modem_ctrl_reg0 [FCM], the modem changes to automatic mode.
Chapter 19: UART Controller 5. Configure interrupts: Interrupts are used to manage the Rx/Tx FIFOs in all modes. Refer to section 19.2.10 Status and Interrupts and the program example in section 19.3.5 RxFIFO Trigger Level Interrupt. 6. Configure modem controls (optional): Polling and interrupt driven options. Refer to section 19.2.11 Modem Control. 7. Manage transmit and receive data: Polling and interrupt driven handlers are supportable. Refer to sections 19.3.3 Transmit Data and 19.3.
Chapter 19: c. UART Controller Enables the Tx path: [TXEN] = 1 and [TXDIS] = 0. d. Restarts the Receiver Timeout Counter: [RSTTO] = 1. 5. e. Does not start to transmit a break: [STTBRK] = 0. f. Stop Break transmitter: [STPBRK] = 1 Program the Receiver Timeout Mechanism. Write the timeout value into the uart.Rcvr_timeout_reg0 register. Refer to Receiver Timeout Mechanism, page 589. a. To enable the timeout mechanism, write a value of 1 to 255 into the [RSTTO] bit field. b.
Chapter 19: UART Controller 5. Enable the interrupt. Enable the interrupt with a write of 1 to uart.Intrpt_en_reg0 [TEMPTY]. 6. Wait until the TxFIFO is empty. Repeat from step 1 when uart.Channel_int_sts_reg0 [TEMPTY] is set to 1. 19.3.4 Receive Data Example: Receive Data using the Polling Method 1. Wait until the RxFIFO is filled up to the trigger level. Check to see if uart.Channel_sts_reg0[RTRIG] = 1 or uart.Chnl_int_sts_reg0 [TIMEOUT] = 1. 2. Read data from the RxFIFO. Read data from the uart.
Chapter 19: c. 4. UART Controller The uart.intrpt_mask_reg0[RTRIG] read back = 0 (disabled interrupt). Clear the RTRIG interrupt. Write a one to the uart.Intrpt_dis_reg0[RTRIG] bit field. When both the enable and disable bits are set for an interrupt, the interrupt is disabled. The state of the interrupt enable/disable mechamism can be determined by reading the uart.Intrpt_mask_reg0 register. If the mask bit = 1, then the interrupt is enabled. 19.3.
Chapter 19: UART Controller CPU_1x Clock Refer to section 25.2 CPU Clock, for general clock programming information. The CPU_1x clock runs asynchronous to the UART reference clock. Reference Clock The generation of the reference clock in the PS clock subsystem is controlled by the slcr.UART_CLK_CTRL register. This register can select the PLL that the clock is derived from and sets the divider frequency. This register also controls the clock enables for each UART controller.
Chapter 19: UART Controller 19.5 I/O Interface 19.5.1 MIO Programming The UART RxD and TxD signals can be routed to one of many sets of MIO pins or to the EMIO interface. All of the modem flow control signals are always routed to the EMIO interface and are not available on the MIO pins. All of the UART signals are listed in Table 19-4. The routing of the RxD and TxD signals are described in section 2.4 PS–PL Voltage Level Shifter Enables.
Chapter 19: UART Controller 19.5.2 MIO – EMIO Signals The UART I/O signals are identified in Table 19-4. The MIO pins and any restrictions based on device versions are shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table.
Chapter 20 I2C Controller 20.1 Introduction This I2C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range from DC (almost) up to 400 Kb/s. In master mode, a transfer can only be initiated by the processor writing the slave address into the I2C address register. The processor is notified of any available received data by a data interrupt or a transfer complete interrupt.
Chapter 20: I2C Controller • Slave mode ° Slave transmitter ° Slave receiver ° Fully programmable slave response address ° Supports HOLD to prevent overflow condition ° Supports TO interrupt flag to avoid stall condition • Software can poll for status or function as interrupt-driven device • Programmable interrupt generation 20.1.2 System Block Diagram The system viewpoint diagram for the I2C module is shown in Figure 20-1.
Chapter 20: I2C Controller 20.2 Functional Description 20.2.1 Block Diagram X-Ref Target - Figure 20-2 Clock Enable Generator Control Register APB APB Interface TX Data Register RX Data Register Interrupts Control FSM SCL/SDA Interface Status Register Interrupts RX Shift Register UG585_c20_02_030612 Figure 20-2: I2C Peripheral Block Diagram 20.2.
Chapter 20: I2C Controller after the data is transmitted. The host is notified of this event by a transfer complete interrupt (COMP bit set) and the TXDV bit in the status register is cleared. At this point, the host can proceed in three ways: 1. Clear the HOLD bit. This causes the I2C interface to generate a STOP condition. 2. Supply more data by writing to the I2C address register. This causes the I2C interface to continue with the transfer, writing more data to the slave.
Chapter 20: I2C Controller 20.2.3 Slave Monitor Mode This mode is meaningful only when the module is in master mode and bit SLVMON in the control register is set. The host must set the MS and SLVMON bits and clear the RW bit in the Control register. Also, it must initialize the Slave Monitor Pause register. The master attempts a transfer to a particular slave whenever the host writes to the I2C Address register.
Chapter 20: I2C Controller If the I2C master terminates the transfer before all of the data in the FIFO is sent by the slave, the host is notified, and the NACK interrupt flag is set while TXDV remains set and the Transfer Size register indicates the remaining bytes in the FIFO. The host must set the CLR_FIFO bit in the Control register to clear the FIFO and the TXDV bit.
Chapter 20: I2C Controller X-Ref Target - Figure 20-3 divisor_a divisor_b 1 to 4 divider 1 to 64 divider Clock_Enable CPU_1x Clock UG585_c20_03_022912 Figure 20-3: I2C Clock Generator The frequency of the clock_enable signal is defined by the frequency of the CPU_1x clock and the values of divisor_a and divisor_b using Equation 20-1 FreqCPU_1x FreqClock_Enable = ----------------------------------------------------------------------( divisor_a + 1 ) × ( divisor_b + 1 ) Equation 20-1 Note: As see
Chapter 20: I2C Controller 20.2.7 I2C0-to-I2C1 Connection The I/O signals of the two I2C controllers in the PS are connected together when the slcr.MIO_LOOPBACK [I2C0_LOOP_I2C1] bit is set = 1. In this mode, the serial clocks are connected together and the serial data signals are connected together. 20.2.8 Status and Interrupts The registers i2c.Interrupt_status_reg0, i2c.Intrpt_mask_reg0, i2c.Intrpt_enable_reg0 and i2c.Intrpt_disable_reg0 provide interrupt capability.
Chapter 20: I2C Controller Interrupt Status Register All the bits are sticky. • Read: Reads interrupt status. • Write: Write 1 to clear Status Register All bits present the raw status of the interface. Bits in this register dynamically change based on FIFO and other conditions. 20.3 Programmer’s Guide 20.3.1 Start-up Sequence 1. Reset controller: Programming resets is described in section 20.4.2 Reset Controller. 2.
Chapter 20: I2C Controller e. Clear the FIFOs: Set i2c.Control_reg0[CLR_FIFO] = 1. f. Program the clock divisors: - Set i2c.Control_reg0[divisor_a] = 0. - Set i2c.Control_reg0[divisor_b] = 50. These divisors generate an I2C SCL of 99 KHz using the CPU_1X clock of 111 MHz. For further details refer to section 20.2.5 I2C Speed. 2. Configure Timeout. Write 0x0000_00FF to the i2c.Time_out_reg0 register. Wait 255 SCL cycles when the SCL is held Low, before generating a timeout interrupt. 20.3.
Chapter 20: I2C Controller 2. Clear interrupts. Read and write back the read value to i2c.Interrupt_status_reg0. 3. Write read data count to transfer size register and hold bus if required. Write read data count value to i2c.Transfer_size_reg0. If read data count greater than FIFO depth, set i2c.Control_reg0 [HOLD] = 1. 4. Write the slave address. Write the address to the i2c.I2C_address_reg0 register. 5. Wait for data to be received into the FIFO. Poll on i2c.Status_reg0 [RXDV] = 1. a. If i2c.
Chapter 20: I2C Controller 5. Write the slave address. Write the address to the i2c.I2C_address_reg0 register. 6. Wait for data to be received into FIFO. a. If read data count is greater than FIFO depth, wait for i2c.Interrupt_status_reg0 [DATA] = 1. Read 14 bytes from FIFO. Decrement the read data count by 14 and if it is less than or equal to the FIFO depth, clear i2c.Control_reg0[HOLD] b. Otherwise, wait for i2c.
Chapter 20: I2C Controller 20.3.5 Register Overview An overview of the I2C registers is provided in Table 20-3. Table 20-3: I2C Register Overview Function Register Names Overview Configuration Control_reg0 Configure the operating mode Data I2C_address_reg0 I2C_data_reg0 Transfer_size_register0 Slave_mon_pause_reg0 Time_out_reg0 Staus_reg0 Transfer data and monitors status.
Chapter 20: I2C Controller 20.5 I/O Interface 20.5.1 Pin Programming The I2C SCL and SDA signals can be routed to one of many sets of MIO pins or to the EMIO interface. All of the I2C signals are listed in Table 20-2. The routing of the SCL and SDA signals are described in section 2.5 PS-PL MIO-EMIO Signals and Interfaces. Example: Route I2C 0 SCL and SDA Signals to MIO Pins 50, 51 In this example, the I2C 0 SCL and SDA signals are routed through MIO pins 50 and 51. Many other pin options are possible. 1.
Chapter 20: I2C Controller Table 20-4: I2C MIO Pins and EMIO Signals (Cont’d) I2C Interface I2C 0, Serial Data I2C 1, Serial Clock I2C 1, Serial Data Default Controller Input Value Numbers ~ 0 ~ MIO Pins 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Chapter 21 Programmable Logic Description 21.1 Introduction The Zynq®-7000 AP SoC devices integrates a feature-rich dual/single core ARM® Cortex™-A9 MPCore™ based processing system (PS) and Xilinx programmable logic (PL) in a single device. Each Zynq-7000 device contains the same PS while the PL and I/O resources vary between the devices. The PL of the six smallest devices, the 7z010/7z015/7z020 (dual core) and the 7z007s/7z012s/7z014s (single core) is based on Artix®-7 FPGA logic.
Chapter 21: • • • • • • ° Register and shift register functionality ° Cascadable adders Programmable Logic Description 36 KB block RAM ° Dual port ° Up to 72 bit-wide ° Configurable as dual 18 KB ° Programmable FIFO logic ° Built-in error correction circuitry Digital signal processing – DSP48E1 Slice ° 25 × 18 two's complement multiplier/accumulator high-resolution 48-bit multiplier/accumulator ° Power saving 25-bit pre-adder to optimize symmetrical filter applications ° Advanced
Chapter 21: Programmable Logic Description 21.1.2 PL Resources by Device Type The PL resources on a per-device type are summarized in Table 21-1.
Chapter 21: Table 21-1: Resource Programmable Logic Description PL Resources by Device Type (Cont’d) 7z007s 7z012s 7z014s 7z010 7z015 7z020 7z030 7z035 7z045 7z100 HR 100 150 200 100 150 200 100 250 250 250 HP 100 150 200 000 150 200 100 250 250 250 Notes: 1. Number of slices corresponding to the number of flip-flops and LUTRAM supported in the device. 2. The total count is limited by tools. 3.
Chapter 21: Programmable Logic Description Between 25–50% of all slices can use their LUTs as distributed 64-bit RAM, as 32-bit shift register (SRL32), or as two 16-bit shift registers (SRL16). Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. For more details on Configuration Logic Blocks, see UG474, 7 Series FPGAs Configurable Logic Block User Guide. 21.2.
Chapter 21: Programmable Logic Description The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At 1,600 MHz, the phase-shift timing increment is 11.2 ps. Clock Distribution Each Zynq-7000 AP SoC device provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.
Chapter 21: Programmable Logic Description Synchronous Operation Each memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
Chapter 21: Programmable Logic Description 21.2.4 Digital Signal Processing — DSP Slice Some highlights of the DSP functionality include: • 25 × 18 two's complement multiplier/accumulator high-resolution (48 bit) signal processor • Power saving pre-adder to optimize symmetrical filter applications • Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices.
Chapter 21: 2. e. Clocks f. Debug interfaces Programmable Logic Description Configuration interface – connected to fixed logic within the PL configuration block, providing PS control a. PCAP b. Configuration status c. SEU d. Program/Done/Init For details on PS-PL interfaces refer to Chapter 2, Signals, Interfaces, and Pins. Voltage Level Shifters All of the signals between the PS and PL pass through voltage level shifters. The programming of these level shifters is explained in section 2.
Chapter 21: Programmable Logic Description I/O Electrical Characteristics Single-ended outputs use a conventional CMOS push/pull output structure driving High towards V CCO or Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-down resistor.
Chapter 21: Programmable Logic Description 21.3.3 GTX Low-Power Serial Transceivers GTX low-power serial gigabit transceivers are available in the 7z030, 7z035, 7z045, and 7z100 devices except where noted in the Serial Transceiver Channels by Device/Package table in UG865, Zynq-7000 AP SoC Packaging Guide. The 7z030 has 0 or 4 GTX transceivers, the 7z035/7z045 has 8 or 16, and the 7z100 device has 16 GTX transceivers. Refer to the packaging guide to get the transceiver count for each package type.
Chapter 21: Programmable Logic Description Receiver The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential signal into a parallel stream of words, each 16, 20, 32, 40, 64, or 80 bits. This allows the designers to trade-off internal datapath width versus logic timing margin.
Chapter 21: Programmable Logic Description Placement Information by Device/Package This section provides position information for available device and package combinations along with the pad numbers for the signals associated with each GTX serial transceiver channel. XC7Z30-FBG484 Package Placement Diagram Figure 21-1 shows the placement diagram for the XC7Z30-FBG484 device.
Chapter 21: Programmable Logic Description XC7Z30-FBG676/FFG676 Package Placement Diagram Figure 21-2 shows the placement diagram for the XC7Z30-FBG676/FFG676 device.
Chapter 21: Programmable Logic Description XC7Z30-SBG485 Package Placement Diagram Figure 21-3 shows the placement diagram for the XC7Z30-SBG485 device.
Chapter 21: Programmable Logic Description XC7Z35-FBG676/FFG676 and XC7Z45-FBG676/FFG676 Package Placement Diagrams Figure 21-4 shows the placement diagrams for the XC7Z35-FBG676/FFG676 and XC7Z45-FBG676/FFG676 devices, MGT Bank 111.
Chapter 21: Programmable Logic Description Figure 21-5 shows the placement diagram for the XC7Z35-FBG676/FFG676 and XC7Z45-FBG676/FFG676 devices, MGT Bank 112.
Chapter 21: Programmable Logic Description XC7Z35-FFG900, XC7Z45-FFG900, and XC7Z100-FFG900 Package Placement Diagram Figure 21-6 shows the placement diagram for the XC7Z35-FFG900, XC7Z45-FFG900, and XC7Z100-FFG900 devices, MGT Bank 109.
Chapter 21: Programmable Logic Description Figure 21-7 shows the placement diagram for the XC7Z35-FFG900, XC7Z45-FFG900, and XC7Z100-FFG900 devices, MGT Bank 110.
Chapter 21: Programmable Logic Description Figure 21-8 shows the placement diagram for the XC7Z35-FFG900, XC7Z45-FFG900, and XC7Z100-FFG900 devices, MGT Bank 111.
Chapter 21: Programmable Logic Description Figure 21-9 shows the placement diagram for the XC7Z35-FFG900, XC7Z45-FFG900, and XC7Z100-FFG900 devices, MGT Bank 112.
Chapter 21: Programmable Logic Description XC7Z100-FFG1156 Package Placement Diagram Figure 21-10 shows the placement diagram for the XC7Z100-FFG1156 device, MGT Bank 109.
Chapter 21: Programmable Logic Description Figure 21-11 shows the placement diagram for the XC7Z100-FFG1156 device, MGT Bank 110.
Chapter 21: Programmable Logic Description Figure 21-12 shows the placement diagram for the XC7Z100-FFG1156 device, MGT Bank 111.
Chapter 21: Programmable Logic Description Figure 21-13 shows the placement diagram for the XC7Z100-FFG1156 device, MGT Bank 112.
Chapter 21: Programmable Logic Description 21.3.4 GTP Low-Power Serial Transceivers The 7z012s and 7z015 devices provides four GTP low-power serial transceivers that can operate up to 6.25 Mb/s per transceiver. The GTX and the GTP transceivers are similar to each other except as noted in UG482, 7 Series FPGAs GTP Transceivers User Guide.
Chapter 21: Programmable Logic Description 21.3.5 Integrated I/O Block for PCIe The integrated PCI Express I/O block is only supported in the 7z012s, 7z015, 7z030, 7z035, 7z045, and 7z100 devices. Highlights of the integrated blocks for PCI Express include: • Compatible with the PCI Express Base Specification 2.1 with Endpoint and Root Port capability • Supports Gen1 (2.
Chapter 21: Programmable Logic Description 21.4 Configuration Zynq-7000 AP SoC device stores its customized PL configuration store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 17 Mb and 140 Mb, depending on device size and user-design implementation options. The configuration storage is volatile and must be reloaded after the PL is power cycled. The PS software or the Xilinx JTAG TAP controller can reload the configuration at any time.
Chapter 22 Programmable Logic Design Guide 22.1 Introduction This chapter covers the following topics: • Programmable Logic for Software Offload is intended to introduce the user to high-level concepts of using the Programmable Logic (PL) to offload CPU functions. • PL and Memory System Performance Overview discusses various performance-related behaviors of memory paths through the PS. • Choosing a Programmable Logic Interface contrasts different PL interfaces available and shows typical uses. 22.
Chapter 22: Programmable Logic Design Guide Power An additional benefit of moving operations to the programmable logic is a reduction in power. Depending on the operations, programmable logic can reduce power per OP by 10-100x. Thus it might be useful to implement algorithms in the PL solely to reduce system power.
Chapter 22: Programmable Logic Design Guide 22.2.3 PL Acceleration Limits The achievable speedup of an accelerator can be limited by I/O, resource, and latency requirements. I/O Rate Limits A key observation is that processing cannot proceed faster than the speed of the data transfers to and from the functional unit.
Chapter 22: Programmable Logic Design Guide RAM can be used at lower energy cost than processor caches. Table 22-1 summarizes the approximate energy cost for various functions implemented on both the A9 processor and the 7 series programmable logic. Table 22-1: Estimated Energy Costs for Common Operations ARM A9 energy/OP (pico Joules or mW/GOP/sec) PL energy/OP (pico Joules op mW/GOP/sec) PL Resource ARM A9 Resource Logical Op of 2 var LUT/FF ALU 1.3 32-bit ADD LUT/FF ALU 1.
Chapter 22: Programmable Logic Design Guide PL Interrupt Servicing PS interrupts are routed to the PL and can be serviced by a MicroBlaze processor or by hardware state machines. HW State Machines When programmable response times from a MicroBlaze or PicoBlaze CPU are not sufficient, hardware state machines can be created to respond to events. These state machines are generally created in RTL, but can also be generated using MATLAB Simulink and Labview graphical design languages. 22.2.
Chapter 22: Programmable Logic Design Guide 22.3 PL and Memory System Performance Overview This section provides a comparison of various performance-related behaviors of memory paths through the PS. It is intended to familiarize the designer with the performance-related behaviors of the PL and PS memory system. 22.3.1 Theoretical Bandwidth Table 22-2 and Table 22-3 provide a basic introduction of relative performance capabilities between various programmable interfaces, DMA, and memory controllers.
Chapter 22: Table 22-4: Programmable Logic Design Guide Theoretical Bandwidth of PS Interconnect Interconnect Clock IF Width IF Clock Read BW Read BW R+W BW Domain (Bits) (MHz) (MB/S) (MB/S) (MB/s) Central Interconnect CPU_2x 64 222 1,776 1,776 3,552 Masters CPU_1x 32 111 444 444 888 Slaves CPU_1x 32 111 444 444 888 Master Interconnect CPU_2x 32 222 888 888 1,776 Slave Interconnect CPU_2x 32 222 888 888 1,776 Memory Interconnect DDR_2x 64 355 2,840 2,
Chapter 22: Programmable Logic Design Guide Table 22-6: DDR Efficiency versus AXI Burst Length (System #1, 4 HP/AFI masters, Sequential Read/Writes) Table 22-7: Burst Length DDR Efficiency (%) 4 87 8 87 16 87 Latency Example Measurement Systems System PL AXI Clock (MHz) CPU_6x4x (MHz) CPU_2x (MHz) DDR_3x (MHz) DDR_2x (MHz) DRAM DRAM (Mb/s) #1 150 675 225 525 350 DDR3 1,050 22.3.
Chapter 22: Programmable Logic Design Guide 22.4 Choosing a Programmable Logic Interface This section discusses various options to connecting Programmable Logic (PL) to the Processing System (PS). The main emphasis is on data movement tasks such as direct memory access (DMA). 22.4.1 PL Interface Comparison Summary Table 22-8 presents a qualitative overview of data transfer use cases. The estimated throughput column reflects suggested maximum throughput in a single direction (read/write).
Chapter 22: Programmable Logic Design Guide Drawbacks of using a CPU to move data is that a sophisticated CPU is spending cycles performing simple data movement instead of complex control and computation tasks, and the limited throughput available. Transfer rates less than 25 MB/s are reasonable with this method.
Chapter 22: Programmable Logic Design Guide X-Ref Target - Figure 22-2 SLCR Quad-SPI 1,2,4,8-bit Parallel 8-bit NOR/SRAM System Level Control Registers NEON NEON SP, DP FPU 128-bit Vector DSP SP, DP FPU 128-bit Vector DSP NAND 8,16-bit APB MIO Pins USB USB DMA DMA GigE GigE DMA DMA SD SD DMA DMA Register Access ARM A9 ARM A9 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache GPIO x54, x64 L2 OCM UART Cache Memory 512 KB On Chip Memory 256 KB PS_SRST_B CLK / PLL ARM, I/O,
Chapter 22: Programmable Logic Design Guide X-Ref Target - Figure 22-3 SLCR Quad-SPI 1,2,4,8-bit Parallel 8-bit NOR/SRAM System Level Control Registers NEON NEON SP, DP FPU 128-bit Vector DSP SP, DP FPU 128-bit Vector DSP NAND 8,16-bit APB MIO Pins USB USB DMA DMA GigE GigE DMA DMA SD SD DMA DMA Register Access ARM A9 ARM A9 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache SCU – Snoop Control Unit IRQ GPIO x54, x64 L2 OCM UART Cache Memory 512 KB On Chip Memory 256 KB
Chapter 22: Programmable Logic Design Guide For more information on S_ACI_ACP, see Chapter 3, Application Processing Unit. See Chapter 29, On-Chip Memory (OCM) when using ACP with OCM.
Chapter 23 Programmable Logic Test and Debug 23.1 Introduction Zynq-7000 AP SoC devices provides extensive debug capability for accessing the PS debug structure (see Chapter 28, System Test and Debug) from the PL. This allows for integrated test and debug on both PS and PL simultaneously. Xilinx provides the fabric trace monitor (FTM) for programmable logic test and debug.
Chapter 23: Programmable Logic Test and Debug 23.1.2 Block Diagram A block diagram of the FTM is shown in Figure 23-1.
Chapter 23: • - 32-bit, free-running, clocked by CPU_2x - Pre-scaled by 2^CYCOUNTPRE (range:1 to 32,768) - Reset by POR, FTMGLBCTRL[FTMENABLE]==0, CoreSight reset request through JTAG The FIFO is used to buffer packets before they are sent to the ATB. The FIFO has these properties: - 64-packets deep - When the FIFO overflows, it signals the packet formatter to generate an overflow packet. In this case, some trace data is lost.
Chapter 23: Programmable Logic Test and Debug The packet formatter generates packets and submits them to the FIFO. The packet formatter can generate the following types of packets: • Trace packets: These packets are generated when valid trace data is available from the PL. • Trigger packets: These trigger packets can only be generated by the FTMTF2PTRIG[0] signal. • Cycle count packets: These packets provide continuous timestamps that are used to reconstruct a real-time trace.
Chapter 23: Programmable Logic Test and Debug No Cycle Count Case – Trace Enabled, Cycle Count Disabled This is similar to the preceding case, except that cycle count packets are not generated.
Chapter 23: Programmable Logic Test and Debug Synchronization Case This scenario illustrates how a synchronization packet is generated amid other types of packets. The FTMSYNCRELOAD register sets the number of packets for which a synchronization packet must be generated.
Chapter 23: Table 23-2: Programmable Logic Test and Debug “Type” Byte Encoding (Cont’d) Type [7] [6:3] [2:0] FIFO overflow packet 0 1101 000 Synchronization packet 0 0000 000 Trace Packet A trace packet contains the 32-bit value from each captured FTMDTRACEINDATA[31:0] from the PL. The MSB of the last byte is determined by the presence of an immediately following cycle count packet. If a cycle count packet follows, the MSB is 1, otherwise it is 0.
Chapter 23: Table 23-5: Programmable Logic Test and Debug Cycle Count Packet Format (Cont’d) Byte [7] [6:0] 3 1 count[24:18] 4 0 count[31:25] FIFO Overflow Packet A FIFO overflow packet is generated when a FIFO overflow occurs.
Chapter 23: Table 23-8: Programmable Logic Test and Debug General-Purpose Debug Signals Group PS-PL Signal General purpose debug input IO Description FTMTF2PDEBUG[7:0] I The FTMF2PDBG0 register shows its value. FTMTF2PDEBUG[15:8] I The FTMF2PDBG1 register shows its value. FTMTF2PDEBUG[23:16] I The FTMF2PDBG2 register shows its value. FTMTF2PDEBUG[31:24] I The FTMF2PDBG3 register shows its value. 23.3.
Chapter 23: Programmable Logic Test and Debug 23.4 Register Overview Table 23-11: Register Overview Function Name Overview Control FTMGLBCTRL FTMCONTROL Status FTMSTATUS Idle status, security signal values, FIFO full/empty. General debug FTMP2FDBG FTMF2PDGB Set the values of the signals presented to the PL. Read the values of the signals from the PL.
Chapter 24 Power Management 24.1 Introduction Power optimization can start with selecting the right Zynq-7000 AP SoC device. For low-power applications, choose either the 7z010 or 7z020 dual core device or the 7z007s, 7z012s, or 7z014s single core device. Power can dramatically be reduced by shutting-down the PL side of the device. I/O voltage and termination choice also affects power consumption. The clocks to individual PS subsystems can be stopped.
Chapter 24: • DDR 16 or 32-bit data I/O • Internal and external voltage measurements using XADC Power Management 24.2 System Design Considerations The section includes these system design considerations: • 24.2.1 Device Technology Choice • 24.2.2 PL Power-down Control • 24.2.3 APU Maximum Frequency • 24.2.4 DDR Memory Clock Frequency • 24.2.5 DDR Memory Controller Modes and Configurations • 24.2.6 Boot Interface Options • 24.2.7 PS Clock Gating 24.2.
Chapter 24: Power Management 24.2.3 APU Maximum Frequency For applications which do not require the maximum amount of processing performance, the APU maximum frequency can be reduced to meet application needs. A lower clock frequency can significantly reduce the operating power when compared to operating at a higher frequency. 24.2.4 DDR Memory Clock Frequency For applications which do not require the maximum amount of DDR bandwidth, the DDR bandwidth can be reduced to meet application needs.
Chapter 24: Power Management 24.3 Programming Guides 24.3.1 System Modules The power management features of the Zynq-7000 AP SoC's system modules are described in detail in their respective chapter. Please refer to Table 24-4 for an overview and further references. Table 24-1: Power Management for System Modules System Module Clocked in Standby Mode Description APU Yes See Chapter 3, Application Processing Unit. SCU (with GIC) Yes See Chapter 3, Application Processing Unit.
Chapter 24: Table 24-2: Power Management Power Management for Peripheral Controls (Cont’d) Peripheral Wake-up Source Clock Gating Low-Power Mode Other Low-Power Modes Yes Section 10.9 Programming Model DDR Controller No Static Memory Controller No Yes 11.2.2 Clocks None Quad-SPI Controller No Yes Section 12.4 System Functions None SDIO Controller No Yes Chapter 25, Clocks None GPIO Controller Yes Section 14.4 System Functions Yes Section 14.
Chapter 24: Power Management 24.4 Sleep Mode Sleep mode is defined at the system level to include the APU in standby mode and multiple controllers being held in reset without a clock. Going into sleep mode can greatly reduce power consumption. In sleep mode, most function clock groups are turned off or powered off. The only required active devices are one CPU, the snoop control unit (SCU), and a wake-up device.
Chapter 24: Power Management The location of the currently used translation table(s) and stacks are controllable through the TTBR and SP registers, respectively. This allows switching between different structures for normal running mode and standby mode if needed. During the standby sequence interrupts are disabled in the CPUs.
Chapter 24: Power Management 5. Disable L2 cache dynamic clock gating. Set l2cpl310.reg15_power_ctrl[dynamic_clk_gating_en] = 0. 6. Disable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 0. 7. Disable Interconnect clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 0. 8. Disable Cortex-A9 dynamic clock gating. Set cp15.power_control_register[dynamic_clock_gating] = 0. 9. Enable all required peripheral devices, including DDR controller clocks. 10.
Chapter 25 Clocks 25.1 Introduction All of the clocks generated by the PS clock subsystem are derived from one of three programmable PLLs: CPU, DDR and I/O. Each of these PLLs is loosely associated with the clocks in the CPU, DDR and peripheral subsystems. 25.1.1 System Block Diagram The major components of the clock subsystem are shown in Figure 25-1.
Chapter 25: Clocks 25.1.2 Clock Generation During normal operation, the PLLs are enabled, driven by the PS_CLK clock pin. In bypass mode, the clock signal on the PS_CLK pin provides the source for the various clock generators instead of the PLLs. (Refer to the applicable Zynq-7000 AP SoC data sheet for PS_CLK characteristics.) When the PS_POR reset signal deasserts, the PLL bypass boot mode pin is sampled and selects between PLL bypass and PLL enabled for all three PLLs.
Chapter 25: Clocks 25.1.3 System Viewpoint Figure 25-1 shows the clock network and related domains from a system viewpoint.
Chapter 25: Clocks A version of the CPU clock is used for most of the internal clocking. The asynchronous DMA peripheral request interfaces between the DMAC and the PL are not shown in Figure 25-2. In addition, PL AXI channels (AXI_HP, AXI_ACP and AXI_GP) have asynchronous interfaces between the PS and PL. The synchronization, where the clock domain crossing occurs, is located inside the PS. Therefore, the PL provides the interface clock to the PS.
Chapter 25: Clocks 25.2 CPU Clock Figure 25-3 shows the clock generation network in the CPU clock domains.
Chapter 25: Clocks Clock Usage During normal usage, most system clocks will be derived by taking the input clock PS_CLK, sending it through the PLL, and finally dividing it down to be used within the PS. While the PS generates many different clocks, as shown in Figure 25-1, there are three clock domains that have the largest interaction and importance in the system: These are the DDR_3x domain, the DDR_2x domain, and the CPU clock domain. The DDR_3x clock domain includes the DDR memory controller.
Chapter 25: Table 25-2: Clocks PS Peripheral Clock Control AMBA Bus Peripheral Base Clock Control Bits in APER_CLK_CTRL 0: Disable 1: Enable DMAC CPU_2x DMA_CPU_2XCLKACT [0] USB 0 CPU_1x USB0_CPU_1XCLKACT [2] USB 1 CPU_1x USB1_CPU_1XCLKACT [3] GigE 0 CPU_1x GEM0_CPU_1XCLKACT [6] GigE 1 CPU_1x GEM1_CPU_1XCLKACT [7] SDIO 0 CPU_1x SDI0_CPU_1XCLKACT [10] SDIO 1 CPU_1x SDI1_CPU_1XCLKACT [11] SPI 0 CPU_1x SPI0_CPU_1XCLKACT [14] SPI 1 CPU_1x SPI1_CPU_1XCLKACT [15] CAN 0
Chapter 25: Clocks The PLL output frequency is determined by the frequency of the input clock PS_CLK multiplied by the PLL feedback divider value (M value). The example below assumes the ARM PLL feedback divider value is 40, which generates an ARM PLL output frequency of 33.33 MHz * 40 = 1.33 GHz. For each of the clocks listed in the lower half of the table, the clock frequency equals the sourced PLL frequency divided by the divisor value.
Chapter 25: Clocks 25.4 Clock Generator Design There are several different components to each clock generation circuit. This section describes a generic template that is used to explain the pieces used for all of the following I/O peripheral clocks. The most basic types include: • 2-to-1 multiplexers for selecting a clock source • Programmable divider(s) • Glitch-free clock activation gate These features are shown in Figure 25-4.
Chapter 25: Clocks Glitch-Free Clock Gate The glitch-free clock gate is used when a dynamic gating is required to enable and disable a clock source. The gate ensures that the clock is terminated and re-enabled cleanly on its low phase. Clock Select Multiplexers The clock source multiplexers select between the local clock generated by a clock generator and another source that is external to the clock generator. The clock source multiplexer is not glitch free. 25.
Chapter 25: Clocks 25.6 IOP Module Clocks The IOP module clock (used for the internal controller logic) can be generated by the clock subsystem or, in some cases, the IOP's external interface. In all cases, the IOP's control and status registers are clocked by its AMBA interface clock (CPU_1x). Sometimes the CPU_1x clock is the only clock used by the IOP. Each clock is discussed in more detail in the following sections and in the system functions section of each chapter.
Chapter 25: Clocks 25.6.2 Ethernet Clocks The Ethernet Clocks generation network is shown in Figure 25-7.
Chapter 25: Clocks interface. They are also used to provide a stable reference clock to the Ethernet receive paths when internal loopback mode is selected. These clocks can also be sourced from the EMIO. In this case, the associated RGMII interface is disabled and the MAC connects to the PL through an MII or GMII interface. In this case, the Ethernet reference clock must be provided by the PL. This is regardless of MII or GMII, where normally tx_clk is an input in MII and an output in GMII.
Chapter 25: Clocks 25.6.4 CAN Clocks There are two controller area network (CAN) reference clocks: CAN0_REF_CLK and CAN1_REF_CLK. Both clocks share the same PLL source selection and dividers as shown in Figure 25-9. Each clock has independent alternate source selection (MIO pin or the clock generator), and independent clock gates. These clocks are used for the I/O interface side of the CAN peripherals.
Chapter 25: Clocks X-Ref Target - Figure 25-10 IO PLL 0 ARM PLL GlitchFree 0 GlitchFree DDR PLL 6-bit Programmable Divisor 0 6-bit Programmable Divisor 1 Glitch-Free Glitch-Free 1 1 Four Independent PL Clocks PL FCLK Clock Control Register Mux Ctrl Field Mux Ctrl Field Divider 0 Ctrl Field Divider 1 Ctrl Field PL FCLK 0 FPGA0_CLK_CTRL SRCSEL, 4 SRCSEL, 5 DIVISOR 0, 13:8 DIVISOR 1, 25:20 FCLKCLK0 PL FCLK 1 FPGA1_CLK_CTRL SRCSEL, 4 SRCSEL, 5 DIVISOR 0, 13:8 DIVISOR 1, 25:20
Chapter 25: Clocks Clock Controller States The clock controller states are illustrated in Figure 25-11. X-Ref Target - Figure 25-11 Software: Rising edge of [CPU_START] Software RUN decrement [CURR_VAL] Hardware: [CURR_VAL] =0 PL signal driven 0 to 1: FCLKCLKTRIGxN Software: Rising edge of CPU_[START] HALT Clock stopped & halt [CURR_VAL] UG585_c25_11_102912 Figure 25-11: PL Clock Throttle States 25.7.
Chapter 25: Clocks Example: Run the PL Clock for 592 Pulses and Stop In this example, there will be 592 clock pulses and stops. The slcr.FPGAx_THR_CTRL [CPU_START] bit is positive edge triggered to start the clock. 1. 2. 3. Prime the Start Clock bit: write 0x0000_0004 to the control register, slcr.FPGAx_THR_CTRL. ° [CPU_START] = 0 ° [CNT_RST] = 0 ° [Reserved] = 0x001 Program a count of 592: write 0x0000_0250 to the count register, slcr.FPGAx_THR_CNT.
Chapter 25: Clocks 25.8 Trace Port Clock The trace port clock is used to clock the TPIU and trace buffer when the MIO interface is chosen and must be twice the frequency of the desired TPIU clock. The TPIU clock frequency must be chosen to be fast enough to allow the trace port to keep up with the amount of data being traced, but slow enough to meet the dynamic characteristics of the data output buffers of the TPIU. To allow some flexibility, the trace clock is generated from a divided PLL output for MIO.
Chapter 25: Table 25-5: Clocks Clock Generation Register Overview (Cont’d) Register Description CLK_621_TRUE Select CPU clock frequency ratio DDR_CLK_CTRL DDR clock control APER_CLK_CTRL AMBA peripheral clock control TOPSW_CLK_CTRL Top-level switch clock control Comments 6:2:1 or 4:2:1 PL Clocks FPGA{3:0}_CLK_CTRL PS to PL output clock control FPGA{3:0}_THR_{CTRL, CNT, STA} PS to PL output clock throttle control, count and status I/O Peripheral Clocks GEM{1, 0}_RCLK_CTRL Gigabit Ethernet
Chapter 25: 3. Clocks Update the DIVISOR to the desired value. 6-bit Programmable Divider The 6-bit divider provides a divide range of 1 to 63, supports both even and odd divide values while producing a close to 50% duty cycle, and is glitchless (divide values can be modified dynamically). The only two exceptions to this rule are that the DDR_3X divider can only be programmed to divide by an even divisor and the ARM_CLK_CTRL[DIVISOR] can not be programmed with a 1 or 3 when the PLL is being used.
Chapter 25: Clocks 2. Force the PLL into bypass mode by writing a 1 to ARM_PLL_CTRL [PLL_BYPASS_FORCE, 4] and setting the ARM_PLL_CTRL [PLL_BYPASS_QUAL, 3] bit to a 0. This de-asserts the reset to the ARM PLL. 3. Assert and de-assert the PLL reset by writing a 1 and then a 0 to ARM_PLL_CTRL [PLL_RESET, 0]. 4. Verify that the PLL is locked by reading PLL_STATUS [ARM_PLL_LOCK, 3]. 5. Disable the PLL bypass mode by writing a 0 to ARM_PLL_CTRL [4].
Chapter 25: Table 25-6: Clocks PLL Frequency Control Settings (Cont’d) Required PLL Control and Configuration Bit Fields Desired PLL Multiplier PLL_FDIV PLL CP PLL RES LOCK CNT 31 ~ 33 31 ~ 33 2 2 300 34 ~ 36 34 ~ 36 2 2 275 37 ~ 40 37 ~ 40 2 2 250 41 ~ 47 41 ~ 47 3 12 250 48 ~ 66 48 ~ 66 2 4 250 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Chapter 26 Reset System 26.1 Introduction The reset system includes resets generated by hardware, watchdog timers, the JTAG controller, and software. Every module and system in Zynq-7000 AP SoC devices includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B). There are three watchdog timers in the PS that can generate resets.
Chapter 26: Reset System X-Ref Target - Figure 26-1 MODE_PINS MIO Pin Boot Mode Register PS_POR_B Dedicated Pin POR Reset Signal Filter PS Clock Generator Clear Security Lockdown Reset PLL Locked Bypass Detect & Hold Reset Persistent Registers Reset Deassertion Delay SoC Debug Domain Debug Reset CPU Processors Internal Registers Watchdog Timer SLCR & Dev Config Registers System Watchdog Timer Resets PS_SRST_B Dedicated Pin Peripheral Resets SLCR Soft Reset Peripheral Reset Control Regi
Chapter 26: Reset System X-Ref Target - Figure 26-2 Power-on Reset Legend Control Logic Debug Reset Security Lock Down External System Reset System Software Reset Watchdog Timer Resets Debug System Reset SCU SoC Debug L-2 Cache CPU 0 Software Reset AWDT 0 Reset CPU 1 Software Reset AWDT 1 Reset IOP Software Resets PL Software Resets SLCR Interconnect CPU 0 w/ NEON CPU 1 w/ NEON I/O Peripherals Programmable Logic UG585_c26_02_101812 Figure 26-2: Reset Hierarchy Diagram 26.1.
Chapter 26: Reset System X-Ref Target - Figure 26-3 Stable Voltage User Visible Stable PS_CLK clock User Visible Release PS_POR_B User Visible Sample Bootstrap Pins User Config Apply eFUSE bits PLL BYPASS? Yes (BOOT_MODE) No Wait for PLLs to Lock Power-on Reset Sequence De-assert DBGRESET System Resets Software SRST_B Watchdog Timers Security Reset RAM Memory Clear De-assert all Resets for CPUs and peripherals BootROM starts to execute Process Boot Image Header User Code UG585_c26_03_12
Chapter 26: Reset System It does not filter Low-going glitches when the signal is intended to be held high. Any Low-going glitch that is detected causes an immediate reset of the device. The PS_POR_B signal is often connected to the power-good signal from the power supply. When PS_POR_B is de-asserted, the system samples the boot strap mode pins and begins its internal initialization process. 26.2.2 External System Reset (PS_SRST_B) Power-on reset erases all debug configurations.
Chapter 26: Reset System Debug system reset is a command from the ARM DAP which is controlled by JTAG. This causes the system to reset, just like the external system reset. Debug reset resets certain portions of the SoC debug block including the JTAG logic. The PS does not support the external TRST, although it does support assertion of a reset sequence using TMS. The JTAG logic is only reset at power-on reset or assertion of CDBGRSTREQ from the ARM debug access port (DAP) Controller (JTAG).
Chapter 26: Reset System 26.4 PL Resets 26.4.1 PL General Purpose User Resets There are four separate reset signals, FCLKRESETN[3:0], routed to the PL which could be used as general purpose reset signals for PL logic. These reset signals are not removed until the PS is out of its boot sequence and user code de-asserts them. They are controllable by the slcr.FPGA_RST_CTRL register. SLCR.FPGA_RST_CTRL.
Chapter 26: Table 26-2: Reset System Persistent Register and Register Bits Type Name Registers devcfg.LOCK devcfg.MULTIBOOT_ADDR(1) devcfg.UNLOCK scu.Watchdog_Reset_Status_Register slcr.REBOOT_STATUS Register bits devcfg.CTRL [PCFG_AES_EN] devcfg.CTRL [PCFG_AES_FUSE] devcfg.CTRL [SEC_EN] devcfg.CTRL [SEU_EN] devcfg.STATUS [ILLEGAL_APB_ACCESS] devcfg.STATUS [SECURE_RST] slcr.APU_CTRL [CFGSDISABLE] slcr.APU_CTRL [CP15SDISABLE] slcr.ARM_CLK_CTRL [SRCSEL] Notes: 1. The upper 16 bits of the devcfg.
Chapter 26: Table 26-4: Reset System Peripheral Reset Control Registers Overview (Cont’d) Peripheral Name Description HW Register DDR DDR PHY/controller/control registers slcr.DDR_RST_CTRL DMA DMA interface slcr.DMAC_RST_CTRL Ethernet Ref, Rx and CPU 1x slcr.GEM_RST_CTRL PS–PL General purpose PL resets slcr.FPGA_RST_CTRL GPIO CPU 1x slcr.GPIO_RST_CTRL I2C CPU 1x slcr.I2C_RST_CTRL Quad-SPI Ref and CPU 1x slcr.LQSPI_RST_CTRL SDIO Ref and CPU 1x slcr.
Chapter 27 JTAG and DAP Subsystem 27.1 Introduction The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. Internally, the AP SoC device implements both an ARM debug access port (DAP) inside the Processing System (PS) as well as a standard JTAG test access port (TAP) controller inside the Programmable Logic (PL). The ARM DAP as part of ARM CoreSight debug architecture allows the user to leverage industry standard third-party debug tools.
Chapter 27: JTAG and DAP Subsystem accidental debug enablement under the security environment due to a single event upset (SEU). Zynq-7000 AP SoC devices also provide JTAG disable lock-down to prevent debug enablement due to software errors. The Zynq-7000 AP SoC provides for permanently disabling JTAG, by using one eFuse bit to record. Care should be used when selecting this option because the eFuse JTAG disable is not reversible. Figure 27-2 shows the debug trace architecture.
Chapter 27: JTAG and DAP Subsystem X-Ref Target - Figure 27-2 PTM ITM FTM Debug APB Trace ATB Funnel (CSTF) PS 4K ETB TPIU EMIO Soft IP Trace Port MIO Trace Port UG585_c27_02_050212 Figure 27-2: Debug Trace Port 27.1.2 Features Key features of the JTAG debug interface are: • JTAG 1149.1 boundary scan support • Two 1149.
Chapter 27: JTAG and DAP Subsystem 27.2 Functional Description Figure 27-3 shows the ARM DAP and JTAG TAP controllers connected in daisy-chain order with the ARM DAP at the front of chain. The two JTAG controllers belong to two different power domains. The ARM DAP is in the PS power domain while the TAP is in the PL power domain. JTAG I/O pads are located in the PL power domain to take advantage of existing JTAG I/O pads in the PL.
Chapter 27: JTAG and DAP Subsystem The PL Xilinx TAP controller serves four key purposes: boundary scan test, eFuse programming, BBRAM programming, and PL debug chipscope.
Chapter 27: JTAG and DAP Subsystem most CPU power. Based on that, the user could decide to either perform software optimization or offload the process to the PL. 27.3 I/O Signals In cascaded JTAG mode, only PL_TDO/TMS/TCK/TDI at the PL side are meaningful to users. Through them, users can access both the ARM DAP and Xilinx TAP. In independent JTAG mode, users can only access the Xilinx TAP, through PL_TDO/TMS/TCK/TDI. To access the ARM DAP, users must use PJTAG signals, as shown in Table 27-1.
Chapter 27: JTAG and DAP Subsystem 27.4 Programming Model 27.4.1 Use Case I: Software Debug with Trace Port Enabled This is the normal debug case for most applications. Figure 27-4 shows ARM tool chain solution. It is also possible to replace ARM Real View ICE with a Xilinx or Lauterbach debug tool. In this case, there is no PL programming required and the user is able to start on software debug as soon as chip power is on.
Chapter 27: JTAG and DAP Subsystem PL must be configured to route the trace signal from the EMIO at the PS/PL boundary to the PL SelectIO. X-Ref Target - Figure 27-5 PL PS JTAG DAP SS TAP Xilinx Platform Cable ARM Review ICE Soft Core JTAG Soft Core TPIU SS SS ARM DStream SRST UG585_c27_05_031812 Figure 27-5: User Case II: PS and PL Debug with Trace Port Enabled 27.
Chapter 27: JTAG and DAP Subsystem Table 27-2: ARM DAP IR Instruction IR Instruction Binary Code[3:0] DR Width Description ABORT 1000 35 JTAG-DP abort register DPACC 1010 35 JTAG DP access register APACC 1011 35 JTAG-AP access Register ARM_IDCODE 1110 32 IDCODE for ARM DAP IP BYPASS 1111 1 The ARM DAP is composed of one debug port (DP) and up to three access ports (APs).
Chapter 27: JTAG and DAP Subsystem 27.6 Trace Port Interface Unit (TPIU) Table 27-5 shows all registers within the TPIU.
Chapter 27: JTAG and DAP Subsystem Table 27-6: JTAG Commands (Cont’d) Boundary Scan Command Binary Code[5:0] Description ISC_PROGRAM 010001 Enables in-system programming ISC_PROGRAM_SECURITY 010010 Change security status from secure to non-secure mode and vice versa ISC_NOOP 010100 No operation ISC_READ 101011 Used to read back BBR ISC_DISABLE 010111 Completes ISC configuration. Startup sequence is executed BYPASS 111111 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.
Chapter 28 System Test and Debug 28.1 Introduction The PS and PL can be debugged together as a complete system using intrusive and non-intrusive debug techniques. In addition to software code debug, there are key hardware points in the PS and user-selected key hardware points in the PL that can capture system activity to help with the debug process. The test and debug capability is based on the ARM CoreSight v1.
Chapter 28: • Standard programmer's models for standard tools support • Automatic discovery of topology • Open interfaces for third party soft cores • Low pin count options System Test and Debug 28.1.2 Notices 7z007s and 7z010 CLG225 Devices The 7z007s single core and 7z010 dual core CLG225 devices support 32 MIO pins as shown in the MIO table in section 2.5.4 MIO-at-a-Glance Table. The width of the TPIU in these CLG225 devices is restricted to 1, 2 or 4-bits via the MIO pins.
Chapter 28: System Test and Debug Figure 28-1 shows the four classes of CoreSight components: • Access and control: DAP, ECT • Trace source: PTM, FTM, ITM • Trace link: Funnel, Replicator • Trace sink: ETB, TPIU The components are connected by three types of buses/signals: • Programming • Trigger • Trace The CoreSight system interacts with: • CPUs through PTM for debug and trace • CPUs through ITM for trace • PL through FTM for debug and trace • CPUs through ETB for dumping trace
Chapter 28: System Test and Debug The DAP block is an ARM-supplied IP with the following configuration: • JTAG is the only external interface on chip pinout. Serial wire interface (SW-DP) is not present. • APB slave and AHB master are the two internal interfaces. JTAG at the DAP's internal side (JTAG-AP) is present, but only the nSRSTOUT[0] output is connected to the system reset controller. • Power-down is not supported.
Chapter 28: Table 28-1: System Test and Debug CTI Trigger Inputs and Outputs (Cont’d) CTI Trigger Port Signal Trigger input 1 FTM trigger Trigger input 2 FTM trigger Trigger input 3 FTM trigger Trigger output 0 FTM trigger Trigger output 1 FTM trigger Trigger output 2 FTM trigger Trigger output 3 FTM trigger CTI (connected to CPU0) Trigger input 0 CPU0 DBGACK Trigger input 1 CPU0 PMU IRQ Trigger input 2 PTM0 EXT Trigger input 3 PTM0 EXT Trigger input 4 CPU0 COMMTX Trigger input
Chapter 28: System Test and Debug Note: For details on the two CTIs connected to CPU0 and CPU1, refer to the CoreSight PTM-A9 Technical Reference Manual, r1p0, DDI0401C, section 1.3.6. 28.2.3 Program Trace Macrocell (PTM) The PTM is the block for tracing processor execution flow. It is based on the ARM program flow trace (PFT) architecture, and is a CoreSight component of the trace source class.
Chapter 28: Table 28-2: System Test and Debug Funnel Input Port List (Cont’d) Port 3 Trace Source ITM 4-7 unused 28.2.6 Embedded Trace Buffer (ETB) The ETB is the on-chip storage of trace data. It is a CoreSight component of the trace sink class. The ETB provides real-time full-speed storing capability, but is limited in size. Triggering is supported for events such as buffer full and acquisition complete.
Chapter 28: System Test and Debug changing the active interface to EMIO, ensure that EMIOTRACELCK is running. Changing the clock input source to a non-running clock results in an APB access hang.
Chapter 28: Table 28-4: System Test and Debug TPIU Signals List (Cont’d) TPIU Signal Trace data Default Input Value Number ~ MIO Pins EMIO Signals I/O Pin Name 1-bit 14 or 26 2-bit 15, 14 or 27, 26 4-bit 11, 10, 15, 14 or 23, 22, 27, 26 8-bit 19-16, 11, 10, 15, 14 16-bit 9-2,19-16,11,10,15,14 O TRACE_DATA[15:0] Signal Name EMIOTRACEDATA[31:0] I/O O 28.4 Register Overview 28.4.1 Memory Map Per the CoreSight specification, each CoreSight component has 4 kB address space.
Chapter 28: System Test and Debug Note: CPU0 debug logic and CPU1 debug logic can also be accessed through CP14 coprocessor instructions. See the Cortex-A9 Technical Reference Manual for details. 28.4.2 Functionality Table 28-6 summarizes the registers in each CoreSight component.
Chapter 28: Table 28-6: System Test and Debug CoreSight Component Register Summary (Cont’d) Function CoreSight management Name Overview Peripheral ID Component ID Device ID, type Claim, lock, authentication Integration test These registers provide: • Identification information • Authentication and access control • Integration test TPIU Supported feature Show maximum and current values of supported port size, test patterns, etc.
Chapter 28: Table 28-6: System Test and Debug CoreSight Component Register Summary (Cont’d) Function Name Overview Control DBGDSCCR Controls cache behavior while the CPU is in debug state Breakpoints BVR BCR Set breakpoint values, and control breakpoints. A breakpoint can be set on an Instruction Virtual Address (IVA) or/and a Context ID Watchpoints WVR WCR Set watchpoint values, and control watchpoints.
Chapter 28: Table 28-6: System Test and Debug CoreSight Component Register Summary (Cont’d) Function Name Overview Misc.
Chapter 28: Table 28-7: System Test and Debug CoreSight Authentication Requirements by Component (Cont’d) DBGEN NIDEN SPIDEN SPNIDEN Enable trigger input 5 x 1 x x Enable trigger input 6 x 1 x x Trigger output 0 1 x x x Trigger output 1 x x x x Trigger output 2 x x x x Trigger output 3 x x x x Trigger output 4 x x x x Trigger output 6 1 x x x Trigger output 7 x x x x x x x x Disable stimulus registers 0-15 0 0 0 0 Disable stimulus registers 16-31
Chapter 29 On-Chip Memory (OCM) 29.1 Introduction The on-chip memory (OCM) module contains 256 KB of RAM and 128 KB of ROM (BootROM). It supports two 64-bit AXI slave interface ports, one dedicated for CPU/ACP access via the APU snoop control unit (SCU), and the other shared by all other bus masters within the processing system (PS) and programmable logic (PL). The BootROM memory is used exclusively by the boot process and is not visible to the user.
Chapter 29: On-Chip Memory (OCM) 29.1.1 Block Diagram X-Ref Target - Figure 29-1 4-port Mem Controller SCU AXI64 RdData SCU AXI64 RdCmd SCU AXI64 WrCmd 256 KB RAM SCU AXI64 Bresp SCU AXI64 WrData Parity Generation & Checking OCM Switch AXI64 RdCmd OCM Switch AXI64 WrCmd OCM Switch AXI64 RdData OCM Switch AXI64 WrData OCM Switch AXI64 Bresp Arbiter APB I/F Registers IRQ UG585_c29_01_042512 Figure 29-1: OCM Block Diagram 29.1.
Chapter 29: • TrustZone support for on-chip RAM with 4 KB page granularity • Flexible address mapping capability • RAM byte-wise parity generation, checking, and interrupt support • Support for the following non-AXI features on the CPU (SCU) port: ° Zero line fill ° Pre-fetch hint ° Early BRESP ° Speculative line pre-fetch On-Chip Memory (OCM) 29.1.3 System Viewpoint A system viewpoint of the OCM is illustrated in Figure 29-2.
Chapter 29: On-Chip Memory (OCM) 29.2 Functional Description 29.2.1 Overview The OCM module is mainly composed of a RAM memory block. The OCM module also contains arbitration, framing, parity, and interrupt logic in addition to the RAM array. 29.2.2 Optimal Transfer Alignment The RAM is implemented as a single-ported, double-width (128-bit) module that can emulate a dual-ported memory under specific conditions.
Chapter 29: On-Chip Memory (OCM) Arbitration is implemented as shown in Figure 29-3.
Chapter 29: On-Chip Memory (OCM) • The RAM array is 128-bits wide. • The OCM switch port has separate read and write channels that can be simultaneously active. • The SCU (CPU/ACP) port has separate read and write channels that can be simultaneously active. • The SCU (CPU/ACP) port channels have a fixed arbitration priority higher than the OCM switch port by default.
Chapter 29: On-Chip Memory (OCM) • All other masters that do not pass through the SCU are always unable to access the lower 512 KB of DDR in the OCM's low address range (0x0000_0000 to 0x0007_FFFF). • Accesses to addresses which the RAM array is not currently mapped to are given an error response. Initial View Upon entering user mode, the BootROM is no longer accessible, and the RAM space is split.
Chapter 29: On-Chip Memory (OCM) OCM Relocation For a contiguous RAM address range, RAM located at address 0x0000_0000 to 0x0002_FFFF can be relocated to base address 0xFFFC_0000 by programming the SLCR registers. Each bit of slcr.OCM_CFG[RAM_HI] corresponds to a 64 KB range, with the MSB corresponding to the highest address offset range. For more register programming details, refer to the SLCR information in the system level control registers section of Appendix B, Register Details.
Chapter 29: On-Chip Memory (OCM) These other bus masters always see the OCM with accesses (from address 0x0000_0000 to 0x0007_FFFF and address 0xFFFC_0000 to 0xFFFF_FFFF) going to OCM space. Depending on how the SLCR OCM registers are configured, these accesses either terminate at the RAM array or to a default reserved address, resulting in an AXI SLVERR error. These other masters potentially see gaps in the RAM address maps. The CPU/ACP view, however, can be different using the SCU address filtering.
Chapter 29: On-Chip Memory (OCM) SLVERR response can also be issued to the requesting master for devices that are unable to or prefer not to handle interrupts. 29.3 Register Overview A partial list of registers related to the OCM is listed in Table 29-7. (See Appendix B, Register Details for the complete list.
Chapter 29: On-Chip Memory (OCM) 5. Unlock the SLCR by writing the unlock key value to the slcr.SLCR_unlock register. 6. Modify the slcr.OCM_CFG register to change the address ranges that the RAM responds to. 7. Re-lock the SLCR by writing the lock key value to the slcr.SLCR_lock register, if desired. 8. Modify the mpcore.Filtering_Start_Address_Register to the desired start address of transactions that should be filtered away from the OCM for SCU masters.
Chapter 30 XADC Interface 30.1 Introduction The Xilinx analog mixed signal module, referred to as the XADC, is a hard macro. It has JTAG and DRP interfaces for accessing the XADC’s status and control registers in the 7-series FPGAs. Zynq-7000 AP SoC devices add a third interface, the PS-XADC interface for the PS software to control the XADC.
Chapter 30: XADC Interface these interfaces is controlled by the devcfg.XADCIF_CFG[ENABLE] bit. However, the XADC arbitrates between the selected interface (PL-JTAG or PS-XADC) and the DRP interface. System Considerations For high-performance ADC applications managed by the PS, use the IP core Core Logic connected to an M_AXI_GP interface. This is a parallel data path.
Chapter 30: • Uses the JTAG TAP controller to access the XADC registers • Enables JTAG access to all XADC registers including ADC measurements XADC Interface 30.1.2 System Viewpoint The XADC is a implemented in hard logic and resides in the PL power domain. The PS-XADC interface is part of the PS and can be accessed by the PS APU without the PL being programmed. The PL must be powered up to configure the PS-XADC interface, use the PL-JTAG or DRP interfaces, and to operate the XADC.
Chapter 30: XADC Interface processor to control the XADC. The IP core receives 16 bits of data with each AXI4-Lite read/write transaction. The interface is described in DS790, Product Specification. The PL-AXI interface provides the highest performance. This interface uses the PL-AXI interface protocol and provides flexibility of integrating additional signal processing IPs in the data path of XADC’s samples.
Chapter 30: XADC Interface X-Ref Target - Figure 30-2 PS Interconnect APB 3.0 Interface 32 32 32 15-deep Command FIFO Configuration, Control, and Status Registers 15-deep Read Data FIFO 32 32 Serial-to-parallel Converter 1 XADC_PS_TDO XADC_PS_TDI XADC_PS_TCK XADC_PS_RESET XADC_PS_EN 1 XADC_PS_ALARM[6:0] XADC_PS_OT Parallel-to-serial Converter Word in XADC UG585_c31_01_021913 Figure 30-2: XADC PS-XADC Interface Block Diagram 30.1.
Chapter 30: XADC Interface Notices 7z007s and 7z010 CLG225 Devices The 7z007s single core and 7z010 dual core CLG225 devices provide four external ADC signal pairs (differential inputs). All other Zynq-7000 devices provide 12 external ADC signal pairs. The hardware pin information is provided in UG865, Zynq-7000 All Programmable SoC Packaging and Pinout product Specification. 30.2 Functional Description The system level block diagram is shown in Figure 30-2, page 749.
Chapter 30: XADC Interface 30.2.2 Serial Communication Channel (PL-JTAG and PS-XADC) The serial communication channel connects the XADC to the PS-XADC or PL-JTAG interface, depending on the devcfg.XADCIF_CFG [ENABLE] bit setting. The channel is a full duplex synchronous bit-serial link with dedicated control signals using a JTAG protocol. By default, after reset, the connection between the PS and XADC (PS-XADC interface) is disabled. PS software can write a 1 to the devcfg.
Chapter 30: XADC Interface DRP Interface The alarms and OT signals are available on the DRP interface. They are actively connected to and used by the LogiCORE AXI_XADC bridge, refer to PG019, LogiCORE IP AXI XADC Product Guide. Functional Description When the measured value on a voltage sensor is greater than the maximum thresholds or less than the minimum threshold values, then the output alarm signal goes active.
Chapter 30: XADC Interface The XADC serial clock drives the DCLK that is described in the LogiCORE User Guide. 30.3.2 Command and Data Packets The PS-XADC interface buffers the 32-bit reads and writes to minimize the effects of the slow serial transfer process on PS system throughput. The PS-XADC interface buffers up to 15 commands. Each command is serialized and communicated to the XADC. For every command that is written to the PS-XADC interface, a data word is received in the Read Data FIFO.
Chapter 30: XADC Interface Note: Reading from an empty Read Data FIFO causes an APB slave bus error. One packet remains in the XADC when the Command FIFO is emptied. To retrieve the packet, write a dummy command. 30.3.3 Command Format Figure 30-4 shows the data format of the PS-XADC interface commands. The first 16 LSBs of the XADCIF_CMD_FIFO contain the DRP register data. For both read and write operations, the address bits, XADCIF_CMD_FIFO [25:16], hold the DRP target register address.
Chapter 30: XADC Interface 30.3.5 Min/Max Voltage Thresholds The XADC tracks the minimum and maximum values recorded for the internal supply sensors since the last power-up or the last reset of the XADC control logic. The maximum and minimum values recorded are stored in the DRP Status registers. On power-up or after reset, all Minimum registers are set to FFFFh and all Maximum registers are set to 0000h.
Chapter 30: XADC Interface 1. Reset the serial communication channel. Write a 1 and then a 0 to devcfg.XADCIF_MCTL [RESET]. 2. Reset the XADC. Write any 16-bit value to DRP address 0x03 (reset register). Write 08030000h to the devcfg.XADCIF_CMDFIFO register. 3. Flush the FIFOs. There is no reset signal, instead write 15 NOOPs to the FIFO: a. Wait for the Command FIFO to empty. The last command should be a NOOP (dummy write). b. Read the Read Data FIFO until empty.
Chapter 30: 3. XADC Interface Wait until the Command FIFO becomes empty. Wait until devcfg.XADCIF_MSTS [CFIFOE] = 1. Note: For every write to the devcfg.XADCIF_CMDFIFO register, data is shifted into the devcfg.XADCIF_RDFIFO register (Read Data FIFO). Example: Read the VCCPAUX value from the XADC This example reads the current VCCPAUX value from the XADC VCCPAUX status register. 1. Prepare command. Prepare the command as described in section 30.4.
Chapter 30: XADC Interface 30.4.3 Command Preparation Example: Prepare Data for Writing to the XADC Register This example formats data for writing to XADC Configuration Register 1 to set the XADC in Independent mode. Refer to Table 30-2, page 754. 1. DRP data. Data to set the XADC in independent mode is 8000h. Refer to the XADC Register Interface section of UG480. 2. DRP address. The address of the XADC Configuration Register 1 is 0x41. 3. Write command. The command for a write operation is 0010b.
Chapter 30: Table 30-3: XADC Interface Register Overview (Cont’d) Function Mnemonic Command and Read Data FIFOs Description Type devcfg.XADCIF_CMDFIFO XADC Interface Command FIFO Write devcfg.XADCIF_RDFIFO XADC Interface Read Data FIFO Read 30.5 Programming Guide for the DRP Interface The XADC can also be accessed by instantiating a LogiCORE AXI XADC bridge in the PL.
Chapter 30: XADC Interface DRP Interface Clocks The PL-AXI interface is a soft core instantiated within the PL and uses a clock from one of the PL’s PLLs. PL-JTAG Interface Clocks PL-JTAG uses the JTAG port to interface with the XADC and uses the JTAG clock, TCK. 30.7.2 Resets There are several resets in the XADC module. PS-XADC Interface Reset The PS-XADC interface and its serial communication channel to the XADC are reset using devcfg.XADCIF_MCTL [RESET].
Chapter 31 PCI Express 31.1 Introduction The Zynq-7000 7z012s, 7z015, 7z030, 7z035, Zynq-7z045, and Zynq-7z100 AP SoC devices include the Xilinx 7 series Integrated block for PCI Express core which is a reliable, high-bandwidth, third-generation I/O solution. The PCI Express solution for these Zynq AP SoC devices supports x1, x2, x4, and x8 lane Root Port and Endpoint configurations at both Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) speeds.
Chapter 31: PCI Express 31.
Chapter 31: PCI Express • Supports Endpoint and Root Port configurations • 8B/10B encode and decode • Supports lane reversal and lane polarity inversion per PCI Express specification requirements • Standardized user interface ° Supports AXI4-stream interface ° Easy-to-use packet-based protocol ° Full-duplex communication ° Back-to-back transactions enable greater link bandwidth utilization ° Supports flow control of data and discontinuation of an in-process transaction in transmit directio
Chapter 31: PCI Express X-Ref Target - Figure 31-2 PS PL ext_reset_in FCLK_RESET0_N interconnect_reset Proc_sys_reset_0 FCLK_0 slow_sync_clk ACLK peripheral_aresetn pcie_a_perst_n ARESETN Axi_interconnect_0 S_AXI_HP0 M S REFCLK 100 / 250MHz M_AXI S_AXI AXI PCIe bridge ARESETN M_AXI_GP0 S M0 pci_exp_rxn/p S_AXI_CTRL pci_exp_txn/p Axi_interconnect_1 ACLK M1 UG585_c31_02_052413 Figure 31-2: Example Zynq PCIe Root Complex Note: The AXI PCIe bridge master and slave ports are conne
Chapter 32 Device Secure Boot 32.1 Introduction Zynq-7000 AP SoC devices support the ability to perform a secure boot to load authenticated and encrypted PS images and PL bitstreams. 32.1.1 Block Diagram Figure 32-1 is a block diagram showing the different systems involved in a secure boot. 32.1.
Chapter 32: Device Secure Boot X-Ref Target - Figure 32-1 Mode_Mode MIO pins Zynq-7000 AP SoC ROM Processing System CPU0 CPU1 Step 1 On-Chip RAM DAP AXI Top Switch MDDR Configuration File 1 NAND NOR QSPI Secure FSBL IOP DDR Memory Controller Step 3 RSA authenticated, AES encrypted with SHA-256 HMAC) Step 4 AXI Secure Vault Common Boot Path PS Boot Path PL Configuration Path FIFO FIFO eFuse/BBRAM Security Secure Boot Process Device Configuration Block PCAP Step 1: Power applied, Boot
Chapter 32: Device Secure Boot 32.2 Functional Description 32.2.1 Master Secure Boot Master secure boot is the only secure boot mode supported in Zynq-7000 AP SoC devices. It uses the hardened AES decryption engine and the hardened HMAC authentication engine within the PL to decrypt PS images and PL bitstreams. If RSA authentication is enabled, the BootROM authenticates the encrypted FSBL using the public key prior to decryption (see Table 32-3).
Chapter 32: Device Secure Boot authentication status of the FSBL and if an authentication error occurs, the BootROM puts the PS into a secure lockdown state. Handoff to FSBL Once the FSBL has been successfully loaded and authenticated, control is turned over to the decrypted FSBL which now resides in the OCM. Based on the user application, the FSBL could then start processing, configure the PL, load additional software, or wait for further instruction from an external source.
Chapter 32: Device Secure Boot 32.2.2 External Boot Devices Secure boot mode is restricted to NOR, NAND, SDIO, or Quad-SPI flash as the external boot device. A secure boot from JTAG or any other external interface is not allowed. 32.2.
Chapter 32: Device Secure Boot X-Ref Target - Figure 32-3 Boot Image Header AES Encrypted Image HMAC Authenticated Image Encrypted FSBL (AES & HMAC) FSBL HMAC Signature FSBL RSA authentication certificate (optional) Partition Partition RSA authentication certificate (optional) AES Encrypted Image HMAC Authenticated Image Partition PS Image or PL Bitstream HMAC Signature Partition RSA authentication certificate (optional) Expansion Space Partition Partition RSA authentication certificate (opti
Chapter 32: Device Secure Boot X-Ref Target - Figure 32-4 Authentication Header Authentication Header Padding PPK 32 bits Padding to 512-bit boundary Modulus (n) 2,048 bits Modulus Extension 2,048 bits Public Exponent 32 bits, padded to 512-bit boundary Modulus (n) 2,048 bits Modulus Extension 2,048 bits SPK Public Exponent 32 bits, padded to 512-bit boundary SPK Signature 2,048 bits FSBL Signature 2,048 bits UG585_c33_04_022513 Figure 32-4: RSA Authentication Certificate Format Not
Chapter 32: Table 32-2: Device Secure Boot PL eFuse Settings Summary (Cont’d) eFuse Description XSK_EFUSEPL_BBRAM_KEY_DISABLE BBRAM Key Disable. If the AP SoC device is booted in secure mode, then the eFuse key must be selected. Non-secure boot of the device is allowed. If the boot image header does not match this setting, a security lockdown occurs. XSK_EFUSEPL_DISABLE_JTAG_CHAIN JTAG Chain Disable. The ARM DAP and PL TAP are permanently disabled.
Chapter 32: Device Secure Boot Once the SPK has been authenticated, the BootROM calculates the SHA-256 hash value for the FSBL stored in OCM. The FSBL is authenticated using the SPK. If the authentication passes, a secure FSBL is then decrypted using the AES or a non-secure FSBL will start execution. 32.2.6 Boot Image and Bitstream Encryption Boot images are assembled and encrypted using software provided by Xilinx, bootgen.
Chapter 32: Device Secure Boot 32.3 Secure Boot Features 32.3.1 Non-Secure Boot State The non-secure state is entered when the BootROM detects that the FSBL is not encrypted. In this state the AES decryption and HMAC authentication engines are disabled and locked requiring a power-on reset (POR) to re-enable. RSA authentication is still available in non-secure boots. All subsequent PS images, PL configuration bitstreams, and PL partial re-configuration bitstreams must be non-encrypted.
Chapter 32: Device Secure Boot 32.3.4 Boot Partition Search The BootROM supports the capability to fall-back and reload a different FSBL if there is a problem with the initial FSBL. In a secure boot, this feature is only supported if the RSA authentication fails, regardless of the encryption status of the FSBL. The new FSBL being loaded must also be signed. If the decryption or HMAC authentication of the FSBL fails, then the device enters secure lockdown. See section 6.3.
Chapter 32: Table 32-4: RSA Authentication Options in Non-secure Mode BootROM RSA User SW RSA AES / HMAC FSBL Yes No No PL Bitstream No User Option No u-Boot No User Option No Linux No User Option No Applications No User Option No Table 32-5: Secure Boot Options without RSA Authentication Enabled BootROM RSA User SW RSA AES / HMAC FSBL No No Yes PL Bitstream No User Option User Option u-Boot No User Option User Option Linux No User Option User Option Applications
Appendix A Additional Resources A.1 Xilinx Resources Product Support and Documentation • For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website. • For continual updates, add the Answer Record to your myAlerts. Device User Guides http://www.xilinx.com/support/index.htm Zynq-7000 AP SoC Product Page http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm Xilinx Design Tools: Release Notes, Installation, and Licensing http://www.xilinx.
Appendix A: Additional Resources A.2 Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips. A.3 References A.3.
Appendix A: Additional Resources These user guides and additional relevant information can be found on the Xilinx 7 Series product page: http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/n um-7-series.html A.3.3 Advanced eXtensible Interface (AXI) Documents Refer to UG761, AXI Reference Guide for further reference on the AXI protocol. A.3.
Appendix A: Additional Resources Xilinx Embedded Development Kit (EDK) http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/embedd ed_development_kit__edk.html ChipScope Pro Documentation http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/chipscop e_pro.html A.3.7 Xilinx Problem Solvers http://www.xilinx.com/support/troubleshoot.htm A.3.
Appendix A: Additional Resources ° ARM PrimeCell DMA Controller (PL330) Technical Reference Manual ° ARM Application Note 239: Example programs for CoreLink DMA Controller DMA-330 ° ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual, Revision r2p1, 12 October 2007 (ARM DDI 0380G) • BOSCH, CAN Specification Version 2.0 PART A and PART B, 1991 • Cadence, Watchdog Timer (SWDT) Specification • IEEE 802.
Appendix B Register Details B.1 Overview This appendix provides details of all the memory-mapped registers in the Zynq®-7000 AP SoC. Throughout this manual, the names of registers and register bit fields used match those given in the hardware. They are called the hardware names. C header files are delivered with this product which define register and bit field names for easy use in software code. In some cases, the software names are different from the hardware names.
Appendix B: Register Details B.2 Acronyms The following acronyms are used for many of the registers.
Appendix B: Register Details B.
Appendix B: Module Name Module Type Base Address gem1 GEM 0xE000C000 Gigabit Ethernet Controller gpio gpio 0xE000A000 General Purpose Input / Output gpv_qos301_c pu qos301 0xF8946000 AMBA Network Interconnect Advanced Quality of Service (QoS-301), CPU-to-DDR gpv_qos301_d mac qos301 0xF8947000 AMBA Network Interconnect Advanced Quality of Service (QoS-301), DMAC gpv_qos301_io qos301 u 0xF8948000 AMBA Network Interconnect Advanced Quality of Service (QoS-301), IOU Register Details Desc
Appendix B: Register Details B.
Appendix B: Reset Value 0x00000000 Description Read Channel Control Register Register Details Register AFI_RDCHAN_CTRL Details Control fields for Read Channel operation. The associated "FPGA_RST_CTRL.
Appendix B: Absolute Address Register Details axi_hp0: 0xF8008004 axi_hp1: 0xF8009004 axi_hp2: 0xF800A004 axi_hp3: 0xF800B004 Width 32 bits Access Type mixed Reset Value 0x00000007 Description Read Issuing Capability Register Register AFI_RDCHAN_ISSUINGCAP Details Sets the maximum number of Outstanding Read Commands allowed (Issuing Capability). Refers to the commands that can be outstanding from the AXI_HP to the SAM switch and back. Fields are selected by the 'axds_rdissuecap1_en' input.
Appendix B: Register Details Register AFI_RDQOS Details Sets the static Qos value to be used for the read channel. If APB register field, 'FabricQosEn' is 0 or ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 1), this static Qos value will be applied to all read commands enqueued into the RdCmdQ. If ('FabricQosEn' is 1 and 'QosHeadOfCmdQEn' is 0), this static Qos field will be ignored. The associated "FPGA_RST_CTRL.
Appendix B: Register Details Register (axi_hp) AFI_RDDEBUG Name AFI_RDDEBUG Relative Address 0x00000010 Absolute Address axi_hp0: 0xF8008010 axi_hp1: 0xF8009010 axi_hp2: 0xF800A010 axi_hp3: 0xF800B010 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Read Channel Debug Register Register AFI_RDDEBUG Details Miscellaneous debug fields for the Read channel. Not to be used for functional purposes. The associated "FPGA_RST_CTRL.
Appendix B: Register Details Register AFI_WRCHAN_CTRL Details Control fields for Write Channel operation. The associated "FPGA_RST_CTRL.FPGA_AXDSN_RST" register field must be written with "0" before accessing this register Field Name Bits Type Reset Value Description reserved 31:12 raz 0x0 Return 0 when read WrDataThreshold 11:8 rw 0xF Sets the threshold at which to send the write command. Note that this is measured in data beats, and is therefore dependent on the '32bitEn' field.
Appendix B: Field Name FabricOutCmdEn Bits 2 Type rw Reset Value 0x0 Register Details Description Enable control of outstanding write commands from the fabric 0: The maximum number of outstanding write commands is always taken from APB register field, 'wrIssueCap0'1: The maximum outstanding number of write commands is selected from the fabric input, 'axds_wrissuecap1_en', as follows: Max Outstanding Write Commands = axds_wrissuecap1_en ? wrIssueCap1 : wrIssueCap0 FabricQosEn 1 rw 0x0 Enable contr
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:7 raz 0x0 Return 0 when read wrIssueCap1 6:4 rw 0x0 Max number of outstanding write commands (Write Issuing Capability) field 1: 3'b000: 1 command 3'b001: 2 commands' ' '3'b111: 8 commands reserved 3 raz 0x0 Return 0 when read wrIssueCap0 2:0 rw 0x7 Max number of outstanding write commands (Write Issuing Capability) field 0: 3'b000: 1 command 3'b001: 2 commands' ' '3'b111: 8 commands Register (ax
Appendix B: Register Details Register (axi_hp) AFI_WRDATAFIFO_LEVEL Name AFI_WRDATAFIFO_LEVEL Relative Address 0x00000020 Absolute Address axi_hp0: 0xF8008020 axi_hp1: 0xF8009020 axi_hp2: 0xF800A020 axi_hp3: 0xF800B020 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Write Data FIFO Level Register Register AFI_WRDATAFIFO_LEVEL Details Returns the Level of the Write Data FIFO in Dwords. Note that this register should only be read if a valid HP port clock is actively running.
Appendix B: Register Details must be written with "0" before accessing this register Field Name Bits Type Reset Value Description reserved 31:5 raz 0x0 Return 0 when read OutWrCmds 4:1 ro 0x0 Returns the number of write commands in flight between the AXI_HP and the SAM switch 4'h0: 0 4'h1: 1 etc WrDataFifoOverflow 0 ro 0x0 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 Bit is set if the WrDataFIFO overflows www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description TXHPB_DATA1 0x00000048 32 rw 0x00000000 transmit high priority buffer data word 1 TXHPB_DATA2 0x0000004C 32 rw 0x00000000 transmit high priority buffer data word 2 RXFIFO_ID 0x00000050 32 ro x receive message fifo message identifier RXFIFO_DLC 0x00000054 32 rw x receive message fifo data length code RXFIFO_DATA1 0x00000058 32 rw x receive message fifo data word 1 RXFIFO_DATA2 0x000000
Appendix B: Register Details The Transfer Layer Configuration Registers can be changed only when CEN bit in the SRR Register is '0.' If the CEN bit is changed during core operation, it is recommended to reset the core so that operations start afresh. Field Name Bits Type Reset Value Description reserved 31:2 rw 0x0 Reserved. CEN 1 rw 0x0 Can Enable The Enable bit for the CAN controller.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:3 rw 0x0 Reserved. SNOOP 2 rw 0x0 Snoop Mode Select The Snoop Mode Select bit. 1: CAN controller is in Snoop mode. 0: CAN controller is in Normal, Loop Back, Configuration, or Sleep mode. This bit can be written to only when CEN bit in SRR is 0. LBACK 1 rw 0x0 Loop Back Mode Select The Loop Back Mode Select bit. 1: CAN controller is in Loop Back mode.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:8 rw 0x0 Reserved BRP 7:0 rw 0x0 Baud Rate Prescaler These bits indicate the prescaler value. The actual value ranges from 1 to 256.
Appendix B: Register Details Register (can) ECR Name ECR Relative Address 0x00000010 Absolute Address can0: 0xE0008010 can1: 0xE0009010 Width 32 bits Access Type ro Reset Value 0x00000000 Description Error Counter Register Register ECR Details The ECR is a read-only register. Writes to the ECR have no effect. The value of the error counters in the register reflect the values of the transmit and receive error counters in the CAN Protocol Engine Module (see Figure 1).
Appendix B: Reset Value 0x00000000 Description Error Status Register Register Details Register ESR Details The Error Status Register (ESR) indicates the type of error that has occurred on the bus. If more than one error occurs, all relevant error flag bits are set in this register. The ESR is a write-to-clear register. Writes to this register will not set any bits, but will clear the bits that are set.
Appendix B: Field Name FMER Bits 1 Type wtc Reset Value 0x0 Register Details Description Form Error Indicates an error in one of the fixed form fields in the message frame. 1: Indicates a form error has occurred. 0: Indicates a form error has not occurred on the bus since the last write to this register. If this bit is set, writing a 1 clears it. CRCER 0 wtc 0x0 CRC Error Indicates a CRC error has occurred. 1: Indicates a CRC error has occurred.
Appendix B: Field Name ACFBSY Bits 11 Type ro Reset Value 0x0 Register Details Description Acceptance Filter Busy indicator. Indicates write-ablity of the Mask and ID registers, read-only: 0: writable 1: not writable. This bit reads 1 when a 0 is written to any of the valid UAF bits in an Acceptance Filter Register. TXFLL 10 ro 0x0 Transmit FIFO Full Indicates that the TX FIFO is full. 1: Indicates the TX FIFO is full. 0: Indicates the TX FIFO is not full.
Appendix B: Field Name NORMAL Bits 3 Type ro Reset Value 0x0 Register Details Description Normal Mode Indicates the CAN controller is in Normal Mode. 1: Indicates the CAN controller is in Normal Mode. 0: Indicates the CAN controller is not in Normal mode. SLEEP 2 ro 0x0 Sleep Mode Indicates the CAN controller is in Sleep mode. 1: Indicates the CAN controller is in Sleep mode. 0: Indicates the CAN controller is not in Sleep mode.
Appendix B: Field Name Bits Type Reset Value Description reserved 31:15 rw 0x0 reserved TXFEMP 14 ro 0x1 Transmit FIFO EmptyInterrupt (IXR_TXFEMP) Register Details A 1 indicates that the Transmit FIFO is empty. The interrupt continues to assert as long as the TX FIFO is empty. This bit can be cleared only by writing to the ICR. TXFWMEMP 13 ro 0x1 (IXR_TXFWMEMP) Transmit FIFO Watermark Empty Interrupt A 1 indicates that the TX FIFO is empty based on watermark programming.
Appendix B: Field Name ERROR Bits 8 Type ro Reset Value 0x0 (IXR_ERROR) Register Details Description Error Interrupt A 1 indicates that an error occurred during message transmission or reception. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. RXNEMP 7 ro 0x0 (IXR_RXNEMP) Receive FIFO Not Empty Interrupt A 1 indicates that the Receive FIFO is not empty. This bit can be cleared only by writing to the ICR.
Appendix B: Field Name TXOK Bits 1 Type ro Reset Value 0x0 Register Details Description Transmission Successful Interrupt (IXR_TXOK) A 1 indicates that a message was transmitted successfully. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. In Loop Back mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.
Appendix B: Field Name ETXFWMEMP Bits 13 Type rw Reset Value 0x0 (IXR_TXFWMEMP) Register Details Description Enable TXFIFO watermark Empty Interrupt Writes to this bit enable or disable interrupts when the TXFWMEMP bit in the ISR is set. 1: Enable interrupt generation if TXFWMEMP bit in ISR is set. 0: Disable interrupt generation if TXFWMEMP bit in ISR is set.
Appendix B: Field Name ERXNEMP Bits 7 Type rw Reset Value 0x0 (IXR_RXNEMP) Register Details Description Enable Receive FIFO Not Empty Interrupt Writes to this bit enable or disable interrupts when the RXNEMP bit in the ISR is set. 1: Enable interrupt generation if RXNEMP bit in ISR is set. 0: Disable interrupt generation if RXNEMP bit in ISR is set.
Appendix B: Field Name Bits ETXOK 1 Type rw Reset Value 0x0 Register Details Description Enable Transmission Successful Interrupt (IXR_TXOK) Writes to this bit enable or disable interrupts when the TXOK bit in the ISR is set. 1: Enable interrupt generation if TXOK bit in ISR is set. 0: Disable interrupt generation if TXOK bit in ISR is set. EARBLST 0 rw 0x0 Enable Arbitration Lost Interrupt (IXR_ARBLST) Writes to this bit enable or disable interrupts when the ARBLST bit in the ISR is set.
Appendix B: Field Name CWKUP Bits 11 Type wo Reset Value 0x0 (IXR_WKUP) CSLP 10 wo 0x0 9 wo 0x0 8 wo 0x0 7 wo 0x0 6 wo 0x0 5 wo 0x0 4 wo 0x0 3 wo 0x0 2 wo 0x0 Clear High Priority Transmit Buffer Full Interrupt Clear Transmit FIFO Full Interrupt Writing a 1 to this bit clears the TXFLL bit in the ISR. 1 wo 0x0 (IXR_TXOK) CARBLST Clear New Message Received Interrupt Writing a 1 to this bit clears the TXBFLL bit in the ISR.
Appendix B: Absolute Address Register Details can0: 0xE0008028 can1: 0xE0009028 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Timestamp Control Register Register TCR Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 reserved CTS 0 wo 0x0 Clear Timestamp Internal free running counter is cleared to 0 when CTS=1. This bit only needs to be written once with a 1 to clear the counter. The bit will automatically return to 0.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:16 rw 0x0 reserved EW 15:8 rw 0x3F TXFIFO Empty watermark TXFIFO generates an EMPTY interrupt based on the value programmed in this field. The valid range is (1-63). No protection is given for illegal programming in this field. This field can be written to only when CEN bit in SRR is 0. FW 7:0 rw 0x3F RXFIFO Full watermark RXFIFO generates FULL interrupt based on the value programmed in this field.
Appendix B: Field Name IDE Bits 19 Type wo Reset Value 0x0 Register Details Description Identifier Extension (IDR_IDE) This bit differentiates between frames using the Standard Identifier and those using the Extended Identifier. Valid for both Standard and Extended Frames. 1: Indicates the use of an Extended Message Identifier. 0: Indicates the use of a Standard Message Identifier. IDL 18:1 wo 0x0 Extended Message ID (IDR_ID2) RTR This field indicates the Extended Identifier.
Appendix B: Register Details Register (can) TXFIFO_DATA1 Name TXFIFO_DATA1 Software Name TXFIFO_DW1 Relative Address 0x00000038 Absolute Address can0: 0xE0008038 can1: 0xE0009038 Width 32 bits Access Type rw Reset Value 0x00000000 Description transmit message fifo data word 1 Register TXFIFO_DATA1 Details Field Name DB0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 0 (DW1R_DB0) DB1 Reads from this field return invalid data if the message has no data.
Appendix B: Register Details Register TXFIFO_DATA2 Details Field Name DB0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 4 (DW2R_DB4) DB1 Reads from this field return invalid data if the message has only 4 byte of data or fewer 23:16 rw 0x0 Data Byte 5 (DW2R_DB5) DB2 Reads from this field return invalid data if the message has only 5 byte of data or fewer 15:8 rw 0x0 Data Byte 6 (DW2R_DB6) DB3 Description Reads from this field return invalid data if the message has only 6 byte of data or fe
Appendix B: Field Name IDE Bits 19 Type wo Reset Value 0x0 Register Details Description Identifier Extension (IDR_IDE) This bit differentiates between frames using the Standard Identifier and those using the Extended Identifier. Valid for both Standard and Extended Frames. 1: Indicates the use of an Extended Message Identifier. 0: Indicates the use of a Standard Message Identifier. IDL 18:1 wo 0x0 Extended Message ID (IDR_ID2) RTR This field indicates the Extended Identifier.
Appendix B: Register Details Register (can) TXHPB_DATA1 Name TXHPB_DATA1 Software Name TXHPB_DW1 Relative Address 0x00000048 Absolute Address can0: 0xE0008048 can1: 0xE0009048 Width 32 bits Access Type rw Reset Value 0x00000000 Description transmit high priority buffer data word 1 Register TXHPB_DATA1 Details Field Name DB0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 0 (DW1R_DB0) DB1 Reads from this field return invalid data if the message has no data.
Appendix B: Register Details Register TXHPB_DATA2 Details Field Name DB0 Bits 31:24 Type rw Reset Value 0x0 Data Byte 4 (DW2R_DB4) DB1 Reads from this field return invalid data if the message has only 4 byte of data or fewer 23:16 rw 0x0 Data Byte 5 (DW2R_DB5) DB2 Reads from this field return invalid data if the message has only 5 byte of data or fewer 15:8 rw 0x0 Data Byte 6 (DW2R_DB6) DB3 Description Reads from this field return invalid data if the message has only 6 byte of data or few
Appendix B: Register Details Register RXFIFO_ID Details Field Name IDH Bits 31:21 Type ro Reset Value x Description Standard Message ID (IDR_ID1) The Identifier portion for a Standard Frame is 11 bits. These bits indicate the Standard Frame ID. This field is valid for both Standard and Extended Frames. SRRRTR 20 ro x Substitute Remote Transmission Request (IDR_SRR) This bit differentiates between data frames and remote frames. Valid only for Standard Frames. For Extended frames this bit is 1.
Appendix B: Relative Address 0x00000054 Absolute Address can0: 0xE0008054 Register Details can1: 0xE0009054 Width 32 bits Access Type rw Reset Value x Description receive message fifo data length code Register RXFIFO_DLC Details Field Name DLC Bits 31:28 Type rw Reset Value x Description Data Length Code (DLCR_DLC) This is the data length portion of the control field of the CAN frame. This indicates the number valid data bytes in Data Word 1 and Data Word 2 registers.
Appendix B: Field Name DB2 Bits 15:8 Type rw Reset Value x Description Data Byte 2 (DW1R_DB2) DB3 Register Details Reads from this field return invalid data if the message has only 2 byte of data or fewer 7:0 rw x Data Byte 3 (DW1R_DB3) Reads from this field return invalid data if the message has only 3 byte of data or fewer Register (can) RXFIFO_DATA2 Name RXFIFO_DATA2 Software Name RXFIFO_DW2 Relative Address 0x0000005C Absolute Address can0: 0xE000805C can1: 0xE000905C Width 32 bit
Appendix B: Absolute Address Register Details can0: 0xE0008060 can1: 0xE0009060 Width 32 bits Access Type rw Reset Value 0x00000000 Description Acceptance Filter Register Register AFR Details The Acceptance Filter Register (AFR) defines which acceptance filters to use. Each Acceptance Filter ID Register (AFIR) and Acceptance Filter Mask Register (AFMR) pair is associated with a UAF bit. When the UAF bit is '1,' the corresponding acceptance filter pair is used for acceptance filtering.
Appendix B: Field Name UAF2 Bits 1 Type rw Reset Value 0x0 Register Details Description Use Acceptance Filter Number 2 Enables the use of acceptance filter pair 2. 1: Indicates Acceptance Filter Mask Register 2 and Acceptance Filter ID Register 2 are used for acceptance filtering. 0: Indicates Acceptance Filter Mask Register 2 and Acceptance Filter ID Register 2 are not used for acceptance filtering. UAF1 0 rw 0x0 Use Acceptance Filter Number 1. Enables the use of acceptance filter pair 1.
Appendix B: Register Details Register AFMR1 Details Field Name AMIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Mask These bits are used for masking the Identifier in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.
Appendix B: Field Name AMIDL Bits 18:1 Type rw Reset Value x Register Details Description Extended Message ID Mask These bits are used for masking the Identifier in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMRTR 0 rw x Remote Transmission Request Mask.
Appendix B: Field Name Bits Type Reset Value Register Details Description AIIDL 18:1 rw x Extended Message ID Mask Extended Identifier AIRTR 0 rw x Remote Transmission Request Mask RTR bit for Extended frames.
Appendix B: Field Name AMIDE Bits 19 Type rw Reset Value x Register Details Description Identifier Extension Mask Used for masking the IDE bit in CAN frames. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.
Appendix B: Description Register Details Acceptance Filter ID Register 2 Register AFIR2 Details Field Name AIIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Standard Identifier AISRR 20 rw x Substitute Remote Transmission Request Indicates the Remote Transmission Request bit for Standard frames AIIDE 19 rw x Identifier Extension Differentiates between Standard and Extended frames AIIDL 18:1 rw x Extended Message ID Mask Extended Identifier AIRTR 0 rw x Remote
Appendix B: Register Details Register AFMR3 Details Field Name AMIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Mask These bits are used for masking the Identifier in a Standard Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.
Appendix B: Field Name AMIDL Bits 18:1 Type rw Reset Value x Register Details Description Extended Message ID Mask These bits are used for masking the Identifier in an Extended Frame. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier. AMRTR 0 rw x Remote Transmission Request Mask.
Appendix B: Field Name Bits Type Reset Value Register Details Description AIIDL 18:1 rw x Extended Message ID Mask Extended Identifier AIRTR 0 rw x Remote Transmission Request Mask RTR bit for Extended frames.
Appendix B: Field Name AMIDE Bits 19 Type rw Reset Value x Register Details Description Identifier Extension Mask Used for masking the IDE bit in CAN frames. 1: Indicates the corresponding bit in Acceptance Mask ID Register is used when comparing the incoming message identifier. 0: Indicates the corresponding bit in Acceptance Mask ID Register is not used when comparing the incoming message identifier.
Appendix B: Description Register Details Acceptance Filter ID Register 4 Register AFIR4 Details Field Name AIIDH Bits 31:21 Type rw Reset Value x Description Standard Message ID Standard Identifier AISRR 20 rw x Substitute Remote Transmission Request Indicates the Remote Transmission Request bit for Standard frames AIIDE 19 rw x Identifier Extension Differentiates between Standard and Extended frames AIIDL 18:1 rw x Extended Message ID Mask Extended Identifier AIRTR 0 rw x Remote
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description DLL_calib 0x00000058 17 rw 0x00000101 DLL calibration ODT_delay_hold 0x0000005C 16 rw 0x00000023 ODT delay and ODT hold ctrl_reg1 0x00000060 13 mixed 0x0000003E Controller 1 ctrl_reg2 0x00000064 18 mixed 0x00020000 Controller 2 ctrl_reg3 0x00000068 26 rw 0x00284027 Controller 3 ctrl_reg4 0x0000006C 16 rw 0x00001610 Controller 4 ctrl_reg5 0x00000078 32 mixed 0x00455111 Contro
Appendix B: Register Name Address Width Type Reset Value Register Details Description CHE_UNCORR_ECC_ DATA_63_32_REG_OF FSET 0x000000E8 32 ro 0x00000000 ECC unrecoverable error data middle CHE_UNCORR_ECC_ DATA_71_64_REG_OF FSET 0x000000EC 8 ro 0x00000000 ECC unrecoverable error data high CHE_ECC_STATS_RE G_OFFSET 0x000000F0 16 clron wr 0x00000000 ECC error count ECC_scrub 0x000000F4 4 rw 0x00000008 ECC mode/scrub CHE_ECC_CORR_BIT _MASK_31_0_REG_OF FSET 0x000000F8 32 ro 0x
Appendix B: Register Name Address Width Type Reset Value Register Details Description phy_wr_dqs_cfg1 0x00000158 20 rw 0x00000000 PHY write DQS configuration register for data slice 1. phy_wr_dqs_cfg2 0x0000015C 20 rw 0x00000000 PHY write DQS configuration register for data slice 2. phy_wr_dqs_cfg3 0x00000160 20 rw 0x00000000 PHY write DQS configuration register for data slice 3. phy_we_cfg0 0x00000168 21 rw 0x00000040 PHY FIFO write enable configuration for data slice 0.
Appendix B: Register Name Address Width Type Reset Value Register Details Description phy_dll_sts2 0x000001D4 27 ro 0x00000000 Slave DLL results for data slice 2. phy_dll_sts3 0x000001D8 27 ro 0x00000000 Slave DLL results for data slice 3.
Appendix B: Register Details Register (ddrc) ddrc_ctrl Name ddrc_ctrl Relative Address 0x00000000 Absolute Address 0xF8006000 Width 32 bits Access Type rw Reset Value 0x00000200 Description DDRC Control Register ddrc_ctrl Details Field Name reserved Bits 31:17 reg_ddrc_dis_auto_refr 16 esh Type Reset Value Description rw 0x0 reserved rw 0x0 Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field.
Appendix B: Field Name Bits reg_ddrc_burst8_refres h 6:4 Type rw Reset Value 0x0 Register Details Description Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
Appendix B: Reset Value 0x000C1076 Description Two Rank Configuration Register Details Register Two_rank_cfg Details Most of this register only applies to a dual rank DRAM system Field Name Bits Type Reset Value Description reserved 28 rw 0x0 Reserved. Do not modify. reserved 27 rw 0x0 Reserved. Do not modify. reserved 26:22 rw 0x0 Reserved. Do not modify. reserved 21 rw 0x0 Reserved. Do not modify. reserved 20:19 rw 0x1 Reserved. Do not modify.
Appendix B: Register Details Register (ddrc) LPR_reg Name LPR_reg Relative Address 0x0000000C Absolute Address 0xF800600C Width 26 bits Access Type rw Reset Value 0x03C0780F Description LPR Queue control Register LPR_reg Details Field Name Bits Type Reset Value Description reg_ddrc_lpr_xact_run _length 25:22 rw 0xF Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available reg_ddrc_lpr_max_sta
Appendix B: Register Details Register (ddrc) DRAM_param_reg0 Name DRAM_param_reg0 Relative Address 0x00000014 Absolute Address 0xF8006014 Width 21 bits Access Type rw Reset Value 0x00041016 Description DRAM Parameters 0 Register DRAM_param_reg0 Details Field Name Bits Type Reset Value Description reg_ddrc_post_selfref_ gap_x32 20:14 rw 0x10 Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist.
Appendix B: Register Details Register DRAM_param_reg1 Details Field Name Bits reg_ddrc_t_cke 31:28 Type rw Reset Value 0x3 Description Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. reg_ddrc_t_ras_min 26:22 rw 0x14 tRAS(min) - Minimum time between activate and precharge to the same bank. Unit: clocks DRAM related. Default value is set for DDR3.
Appendix B: Width 32 bits Access Type rw Reset Value 0x83015904 Description DRAM Parameters 2 Register Details Register DRAM_param_reg2 Details Field Name Bits Type Reset Value Description reg_ddrc_t_rcd 31:28 rw 0x8 tRCD - AL Minimum time from activate to read or write command to same bank. Min value for this is 1. AL = Additive Latency. DRAM Related.
Appendix B: Field Name Bits reg_ddrc_rd2wr 9:5 Type rw Reset Value 0x8 Register Details Description Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
Appendix B: Field Name Bits Type Reset Value Description reg_phy_mode_ddr1_d 29 dr2 rw 0x1 unused reg_ddrc_read_latency rw 0x5 Non-LPDDR2: not used. 28:24 Register Details DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. reg_ddrc_en_dfi_dram _clk_disable 23 rw 0x0 Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh.
Appendix B: Field Name Bits reg_ddrc_t_rrd 7:5 Type rw Reset Value 0x6 Register Details Description tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED reg_ddrc_t_ccd 4:2 rw 0x4 tCCD - Minimum time between two reads or two writes (from bank a to bank b). DRAM related.
Appendix B: Field Name Bits reg_ddrc_mr_data 24:9 Type rw Reset Value 0x0 Register Details Description DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addr[7:0], MR Data[7:0]. reg_ddrc_mr_addr 8:7 rw 0x0 DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 reg_ddrc_mr_wr 6 wo 0x0 A low to high signal on this signal will do a mode register write or read.
Appendix B: Field Name Bits reg_ddrc_pre_ocd_x32 10:7 reg_ddrc_final_wait_x3 6:0 2 Type Reset Value Register Details Description rw 0x0 Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. rw 0x7 Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler.
Appendix B: Width 32 bits Access Type rw Reset Value 0x00000940 Description DRAM EMR, MR access Register Details Register DRAM_EMR_MR_reg Details Field Name Bits reg_ddrc_emr 31:16 Type rw Reset Value 0x0 Description DDR2: Value loaded into EMR1 register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0.
Appendix B: Field Name Bits reg_ddrc_post_cke_x10 25:16 24 Type rw Reset Value 0x2 Register Details Description Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 6 rw 0x0 Reserved. Do not modify. reserved 5:2 ro 0x0 Reserved reg_ddrc_dis_dq 1 rw 0x0 When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. reg_ddrc_force_low_pr i_n 0 rw 0x0 Read Transaction Priority disable.
Appendix B: Field Name Bits reg_ddrc_addrmap_col _b6 19:16 Type rw Reset Value 0x0 Register Details Description Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
Appendix B: Field Name reg_ddrc_addrmap_col _b11 Bits 31:28 Type rw Reset Value 0xF Register Details Description Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field.
Appendix B: Field Name reg_ddrc_addrmap_col _b9 Bits 23:20 Type rw Reset Value 0xF Register Details Description Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field.
Appendix B: Field Name Bits reg_ddrc_addrmap_col _b4 11:8 Type rw Reset Value 0x0 Register Details Description Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bit 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
Appendix B: Register Details Register DRAM_addr_map_row Details Field Name Bits Type Reset Value Description reg_ddrc_addrmap_ro w_b15 27:24 rw 0xF Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
Appendix B: Absolute Address 0xF8006048 Width 30 bits Access Type rw Reset Value 0x00000249 Description DRAM ODT control Register Details Register DRAM_ODT_reg Details Parts of this register are unused. Field Name Bits Type Reset Value Description reserved 29:27 rw 0x0 Reserved. Do not modify. reserved 26:24 rw 0x0 Reserved. Do not modify. reserved 23:21 rw 0x0 Reserved. Do not modify. reserved 20:18 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits reg_ddrc_rank0_wr_od 5:3 t Type rw Reset Value 0x1 Register Details Description [1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.
Appendix B: Field Name Bits Type Reset Value Register Details Description phy_reg_bc_fifo_we2 14 ro 0x0 Debug read capture FIFO write enable, for data slice 2. phy_reg_bc_dqs_oe2 13 ro 0x0 Debug DQS output enable for data slice 2. phy_reg_bc_dq_oe2 12 ro 0x0 Debug DQ output enable for data slice 2. phy_reg_bc_fifo_re1 11 ro 0x0 Debug read capture FIFO read enable for data slice 1. phy_reg_bc_fifo_we1 10 ro 0x0 Debug read capture FIFO write enable, for data slice 1.
Appendix B: Register Details Register phy_cmd_timeout_rddata_cpt Details Field Name reg_phy_wrlvl_num_o f_dq0 Bits 31:28 Type rw Reset Value 0x0 Description This register value determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 +1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
Appendix B: Field Name Bits reg_phy_rdc_we_to_re _delay 11:8 Type rw Reset Value 0x2 Register Details Description This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
Appendix B: Register Details Register (ddrc) DLL_calib Name DLL_calib Relative Address 0x00000058 Absolute Address 0xF8006058 Width 17 bits Access Type rw Reset Value 0x00000101 Description DLL calibration Register DLL_calib Details Field Name Bits reg_ddrc_dis_dll_calib 16 Type rw Reset Value 0x0 Description When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly.
Appendix B: Field Name Bits reg_ddrc_wr_odt_dela y 7:4 Type rw Reset Value 0x2 Register Details Description The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
Appendix B: Field Name Bits reg_ddrc_refresh_upda 8 te_level Type rw Reset Value 0x0 Register Details Description Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. reg_ddrc_auto_pre_en 7 rw 0x0 When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.
Appendix B: Field Name Bits Type Reset Value Register Details Description reg_ddrc_go2critical_h ysteresis 12:5 rw 0x0 Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
Appendix B: Register Details Register (ddrc) ctrl_reg4 Name ctrl_reg4 Relative Address 0x0000006C Absolute Address 0xF800606C Width 16 bits Access Type rw Reset Value 0x00001610 Description Controller 4 Register ctrl_reg4 Details Field Name Bits Type Reset Value Description dfi_t_ctrlupd_interval_ max_x1024 15:8 rw 0x16 This is the maximum amount of time between Controller initiated DFI update requests.
Appendix B: Register Details Register ctrl_reg5 Details Field Name Bits Type Reset Value Description reserved 31:26 ro 0x0 Reserved reg_ddrc_t_ckesr 25:20 rw 0x4 Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 reg_ddrc_t_cksrx 19:16 rw 0x5 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX.
Appendix B: Register Details Register (ddrc) ctrl_reg6 Name ctrl_reg6 Relative Address 0x0000007C Absolute Address 0xF800607C Width 32 bits Access Type mixed Reset Value 0x00032222 Description Controller register 6 Register ctrl_reg6 Details Field Name Bits Type Reset Value Description reserved 31:20 ro 0x0 Reserved reg_ddrc_t_ckcsx 19:16 rw 0x3 This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX.
Appendix B: Access Type rw Reset Value 0x00008000 Description CHE_REFRESH_TIMER01 Register Details Register CHE_REFRESH_TIMER01 Details Field Name Bits Type Reset Value Description reserved 23:12 rw 0x8 Reserved. Do not modify. reserved 11:0 rw 0x0 Reserved. Do not modify.
Appendix B: Register Details Register (ddrc) CHE_T_ZQ_Short_Interval_Reg Name CHE_T_ZQ_Short_Interval_Reg Relative Address 0x000000A8 Absolute Address 0xF80060A8 Width 28 bits Access Type rw Reset Value 0x0020003A Description Misc parameters Register CHE_T_ZQ_Short_Interval_Reg Details Field Name Bits Type Reset Value Description dram_rstn_x1024 27:20 rw 0x2 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
Appendix B: Register Details Register deep_pwrdwn_reg Details Field Name Bits deeppowerdown_to_x 1024 8:1 Type rw Reset Value 0x0 Description DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. deeppowerdown_en 0 rw 0x0 DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode.
Appendix B: Field Name Bits ddrc_reg_trdlvl_max_e rror 25 Type ro Reset Value 0x0 Register Details Description DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
Appendix B: Register Details Register reg_2d Details Field Name Bits Type Reset Value Description reserved 10 rw 0x0 Reserved. Do not modify. reg_ddrc_skip_ocd 9 rw 0x1 This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. reserved 8:0 rw 0x0 Reserved. Do not modify.
Appendix B: Width 2 bits Access Type rw Reset Value 0x00000000 Description ECC error clear Register Details Register CHE_ECC_CONTROL_REG_OFFSET Details Field Name Bits Clear_Correctable_DR AM_ECC_error 1 Type rw Reset Value 0x0 Description Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. Write 0 to this bit will start capturing incoming correctable error count.
Appendix B: Register Details Register CHE_CORR_ECC_LOG_REG_OFFSET Details Field Name Bits ECC_CORRECTED_BI T_NUM 7:1 Type clron wr Reset Value 0x0 Description Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC).
Appendix B: Field Name Bits Type Reset Value Register Details Description CORR_ECC_LOG_RO W 27:12 ro 0x0 Row [15:0] CORR_ECC_LOG_CO L 11:0 ro 0x0 Column [11:0] Register (ddrc) CHE_CORR_ECC_DATA_31_0_REG_OFFSET Name CHE_CORR_ECC_DATA_31_0_REG_OFFSET Relative Address 0x000000D0 Absolute Address 0xF80060D0 Width 32 bits Access Type ro Reset Value 0x00000000 Description ECC error correction data log low Register CHE_CORR_ECC_DATA_31_0_REG_OFFSET Details Field Name Bits CORR_ECC_
Appendix B: Register Details Register CHE_CORR_ECC_DATA_63_32_REG_OFFSET Details Field Name Bits CORR_ECC_LOG_DA T_63_32 31:0 Type ro Reset Value 0x0 Description Bits [63:32] of the data that caused the captured correctable ECC error. (Data associated with the first ECC error if multiple errors occurred since CORR_ECC_LOG_VALID was cleared) Since each ECC engine handles 8-bits of data and that is logged in register 0x34, all the 32-bits of this register will always be 0.
Appendix B: Register Details Register CHE_UNCORR_ECC_LOG_REG_OFFSET Details Field Name Bits UNCORR_ECC_LOG_ VALID 0 Type clron wr Reset Value 0x0 Description Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
Appendix B: Register Details Register CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET Details Field Name Bits UNCORR_ECC_LOG_ DAT_31_0 31:0 Type ro Reset Value 0x0 Description bits [31:0] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since UNCORR_ECC_LOG_VALID was cleared). Since each ECC engine handles 8-bits of data, only the lower 8-bits of this register have valid data. The upper 24-bits will always be 0.
Appendix B: Register Details Register CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET Details Field Name Bits UNCORR_ECC_LOG_ DAT_71_64 7:0 Type ro Reset Value 0x0 Description bits [71:64] of the data that caused the captured uncorrectable ECC error. (Data associated with the first ECC error if multiple errors occurred since UNCORR_ECC_LOG_VALID was cleared) 5-bits of ECC are calculated over 8-bits of data. Bits[68:64] carries these 5-bits. Bits[71:69] are always 0.
Appendix B: Register Details Register ECC_scrub Details Field Name Bits reg_ddrc_dis_scrub 3 Type rw Reset Value 0x1 Description 0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs reg_ddrc_ecc_mode 2:0 rw 0x0 DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100.
Appendix B: Register Details Register CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET Details Field Name Bits ddrc_reg_ecc_corr_bit_ mask 31:0 Type ro Reset Value 0x0 Description Bits [31:0] of ddrc_reg_ecc_corr_bit_mask register. Indicates the mask of the corrected data. 1 - on any bit indicates that the bit has been corrected by the DRAM ECC logic 0 - on any bit indicates that the bit has NOT been corrected by the DRAM ECC logic. Valid when any bit of 'ddrc_reg_ecc_corrected_err' is high.
Appendix B: Relative Address 0x00000114 Absolute Address 0xF8006114 Width 8 bits Access Type rw Reset Value 0x00000000 Description Phy receiver enable register Register Details Register phy_rcvr_enable Details Field Name reg_phy_dif_off Bits 7:4 Type rw Reset Value 0x0 Description Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off.
Appendix B: Name Register Details Address PHY_Config0 0xf8006118 PHY_Config1 0xf800611c PHY_Config2 0xf8006120 PHY_Config3 0xf8006124 Register PHY_Config0 to PHY_Config3 Details Field Name Bits reg_phy_dq_offset 30:24 Type rw Reset Value 0x40 Description Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits.
Appendix B: Reset Value 0x00000000 Description PHY init ratio register for data slice 0. Register Details Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Register phy_rd_dqs_cfg0 to phy_rd_dqs_cfg3 Details Field Name Bits Type Reset Value Description reg_phy_rd_dqs_slave _delay 19:11 rw 0x0 If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. reg_phy_rd_dqs_slave _force 10 rw 0x0 0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
Appendix B: Register Details Register phy_wr_dqs_cfg0 to phy_wr_dqs_cfg3 Details Field Name Bits Type Reset Value Description reg_phy_wr_dqs_slave _delay 19:11 rw 0x0 If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. reg_phy_wr_dqs_slave _force 10 rw 0x0 0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
Appendix B: Register Details Register phy_we_cfg0 to phy_we_cfg3 Details Field Name Bits reg_phy_fifo_we_in_de 20:12 lay Type rw Reset Value 0x0 Description Delay value to be used when reg_phy_fifo_we_in_force is set to 1. reg_phy_fifo_we_in_fo rce 11 rw 0x0 0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e.
Appendix B: Register Details Register wr_data_slv0 to wr_data_slv3 Details Field Name Bits Type Reset Value Description reg_phy_wr_data_slav e_delay 19:11 rw 0x0 If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. reg_phy_wr_data_slav e_force 10 rw 0x0 0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
Appendix B: Field Name Bits reg_phy_ctrl_slave_for ce 20 Type rw Reset Value 0x0 Register Details Description 0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. reg_phy_ctrl_slave_rati 19:10 o rw 0x80 Ratio value for address/command launch timing in phy_ctrl macro.
Appendix B: Reset Value 0x00000000 Description Training control 3 Register Details Register reg_65 Details Field Name Bits Type Reset Value Description reg_phy_ctrl_slave_del ay 19:18 rw 0x0 If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value reg_phy_dis_calib_rst 17 rw 0x0 Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data.
Appendix B: Field Name Bits reg_phy_rd_rl_delay 9:5 Type rw Reset Value 0x0 Register Details Description This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency 3) with a minimum value of 1.
Appendix B: Relative Address 0x000001A8 Absolute Address 0xF80061A8 Width 29 bits Access Type ro Reset Value 0x00060200 Description Training results for data slice 1. Register Details Register reg69_6a1 Details Field Name Bits Type Reset Value Description phy_reg_status_fifo_w e_slave_dll_value 27:19 ro 0x0 Delay value applied to FIFO WE slave DLL. phy_reg_rdlvl_fifowei n_ratio 18:9 ro 0x301 Ratio value generated by Read Gate training FSM. reserved 8:0 ro 0x0 Reserved.
Appendix B: Register Details Register (ddrc) reg6c_6d3 Name reg6c_6d3 Relative Address 0x000001B4 Absolute Address 0xF80061B4 Width 28 bits Access Type ro Reset Value 0x00000E00 Description Training results for data slice 3. Register reg6c_6d3 Details Field Name Bits Type Reset Value Description phy_reg_status_fifo_w e_slave_dll_value 27:19 ro 0x0 Delay value applied to FIFO WE slave DLL. phy_reg_rdlvl_fifowei n_ratio 18:9 ro 0x7 Ratio value generated by Read Gate training FSM.
Appendix B: Register Details Register reg6e_710 to reg6e_713 Details Field Name Bits Type Reset Value Description phy_reg_rdlvl_dqs_rati 29:20 o ro x Ratio value generated by Read Data Eye training FSM. phy_reg_wrlvl_dq_rati o 19:10 ro x Ratio value generated by the write leveling FSM for Write Data. phy_reg_wrlvl_dqs_rat io 9:0 ro x Ratio value generated by the write leveling FSM for Write DQS.
Appendix B: Relative Address 0x000001E0 Absolute Address 0xF80061E0 Width 24 bits Access Type ro Reset Value 0x00F00000 Description DLL Lock Status, read Register Details Register dll_lock_sts Details Field Name Bits phy_reg_rdlvl_fifowei n_ratio_slice3_msb 23:20 Type ro Reset Value 0xF Description Used as 4-msbits of slice3's ratio value generated by Read Gate training FSM.
Appendix B: Register Details Register phy_ctrl_sts Details Field Name Bits phy_reg_status_phy_ct rl_of_in_lock_state 29:28 Type ro Reset Value 0x0 Description Lock status from Master DLL Output Filter. 0: not locked, 1: locked. Bit 28: Fine delay line. Bit 29: Coarse delay line.
Appendix B: Register Details Register (ddrc) axi_id Name axi_id Relative Address 0x00000200 Absolute Address 0xF8006200 Width 26 bits Access Type ro Reset Value 0x00153042 Description ID and revision information Register axi_id Details Field Name Bits Type Reset Value Description reg_arb_rev_num 25:20 ro 0x1 Revision Number reg_arb_prov_num 19:12 ro 0x53 Prov number reg_arb_part_num 11:0 ro 0x42 Part Number Register (ddrc) page_mask Name page_mask Relative Address 0x00
Appendix B: Register Details Register (ddrc) axi_priority_wr_port0 Name axi_priority_wr_port0 Relative Address 0x00000208 Absolute Address 0xF8006208 Width 20 bits Access Type mixed Reset Value 0x000803FF Description AXI Priority control for write port 0. Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Register (ddrc) axi_priority_rd_port0 Name axi_priority_rd_port0 Relative Address 0x00000218 Absolute Address 0xF8006218 Width 20 bits Access Type mixed Reset Value 0x000003FF Description AXI Priority control for read port 0. Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Register (ddrc) excl_access_cfg0 Name excl_access_cfg0 Relative Address 0x00000294 Absolute Address 0xF8006294 Width 18 bits Access Type rw Reset Value 0x00000000 Description Exclusive access configuration for port 0. Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Field Name Bits ddrc_reg_rd_mrr_data 31:0 Type ro Reset Value 0x0 Register Details Description Mode register read Data. Valid when ddrc_co_rd_mrr_data_valid is high. Bits[7:0] carry the 8-bit MRR value. Valid for LPDDR2 only.
Appendix B: Width 32 bits Access Type rw Reset Value 0x00000000 Description LPDDR2 Control 1 Register Details Register lpddr_ctrl1 Details Field Name Bits reg_ddrc_mr4_read_int 31:0 erval Type rw Reset Value 0x0 Description Interval between two MR4 reads, USED to derate the timing parameters.
Appendix B: Reset Value 0x00000601 Description LPDDR2 Control 3 Register Details Register lpddr_ctrl3 Details Field Name Bits reg_ddrc_dev_zqinit_x 32 17:8 reg_ddrc_max_auto_in it_x1024 7:0 Type rw Reset Value 0x6 Description ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. rw 0x1 Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description CTIOUTEN1 0x000000A4 4 rw 0x00000000 CTI Channel to Trigger Enable 1 Register CTIOUTEN2 0x000000A8 4 rw 0x00000000 CTI Channel to Trigger Enable 2 Register CTIOUTEN3 0x000000AC 4 rw 0x00000000 CTI Channel to Trigger Enable 3 Register CTIOUTEN4 0x000000B0 4 rw 0x00000000 CTI Channel to Trigger Enable 4 Register CTIOUTEN5 0x000000B4 4 rw 0x00000000 CTI Channel to Trigger Enable 5 Register
Appendix B: Register Name Address Width Type Reset Value Register Details Description DTIR 0x00000FCC 8 ro 0x00000014 Device Type Identifier Register PERIPHID4 0x00000FD0 8 ro 0x00000004 Peripheral ID4 PERIPHID5 0x00000FD4 8 ro 0x00000000 Peripheral ID5 PERIPHID6 0x00000FD8 8 ro 0x00000000 Peripheral ID6 PERIPHID7 0x00000FDC 8 ro 0x00000000 Peripheral ID7 PERIPHID0 0x00000FE0 8 ro 0x00000006 Peripheral ID0 PERIPHID1 0x00000FE4 8 ro 0x000000B9 Peripheral ID1
Appendix B: Relative Address 0x00000010 Absolute Address debug_cpu_cti0: 0xF8898010 Register Details debug_cpu_cti1: 0xF8899010 debug_cti_etb_tpiu: 0xF8802010 debug_cti_ftm: 0xF8809010 Width 8 bits Access Type wo Reset Value 0x00000000 Description CTI Interrupt Acknowledge Register Register CTIINTACK Details Field Name INTACK Bits 7:0 Type wo Reset Value 0x0 Description Acknowledges the corresponding CTITRIGOUT output: 1 = CTITRIGOUT is acknowledged and is cleared when MAPTRIGOUT is LOW.
Appendix B: Register Details Register CTIAPPSET Details Field Name APPSET Bits 3:0 Type rw Reset Value 0x0 Description Setting a bit HIGH generates a channel event for the selected channel. Read: 0 = application trigger inactive (reset) 1 = application trigger active. Write: 0 = no effect 1 = generate channel event. There is one bit of the register for each channel.
Appendix B: Absolute Address Register Details debug_cpu_cti0: 0xF889801C debug_cpu_cti1: 0xF889901C debug_cti_etb_tpiu: 0xF880201C debug_cti_ftm: 0xF880901C Width 4 bits Access Type wo Reset Value 0x00000000 Description CTI Application Pulse Register Register CTIAPPPULSE Details Field Name APPULSE Bits 3:0 Type wo Reset Value 0x0 Description Setting a bit HIGH generates a channel event pulse for the selected channel.
Appendix B: Register Details Register CTIINEN0 Details Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
Appendix B: Register Details Register (cti) CTIINEN2 Name CTIINEN2 Relative Address 0x00000028 Absolute Address debug_cpu_cti0: 0xF8898028 debug_cpu_cti1: 0xF8899028 debug_cti_etb_tpiu: 0xF8802028 debug_cti_ftm: 0xF8809028 Width 4 bits Access Type rw Reset Value 0x00000000 Description CTI Trigger to Channel Enable 2 Register Register CTIINEN2 Details Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIG
Appendix B: Register Details Register CTIINEN3 Details Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
Appendix B: Register Details Register (cti) CTIINEN5 Name CTIINEN5 Relative Address 0x00000034 Absolute Address debug_cpu_cti0: 0xF8898034 debug_cpu_cti1: 0xF8899034 debug_cti_etb_tpiu: 0xF8802034 debug_cti_ftm: 0xF8809034 Width 4 bits Access Type rw Reset Value 0x00000000 Description CTI Trigger to Channel Enable 5 Register Register CTIINEN5 Details Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIG
Appendix B: Register Details Register CTIINEN6 Details Field Name TRIGINEN Bits 3:0 Type rw Reset Value 0x0 Description Enables a cross trigger event to the corresponding channel when an CTITRIGIN is activated. 1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM. There is one bit of the register for each of the four channels. For example in register CTIINEN0, TRIGINEN[0] set to 1 enables CTITRIGIN onto channel 0.
Appendix B: Register Details Register (cti) CTIOUTEN0 Name CTIOUTEN0 Relative Address 0x000000A0 Absolute Address debug_cpu_cti0: 0xF88980A0 debug_cpu_cti1: 0xF88990A0 debug_cti_etb_tpiu: 0xF88020A0 debug_cti_ftm: 0xF88090A0 Width 4 bits Access Type rw Reset Value 0x00000000 Description CTI Channel to Trigger Enable 0 Register Register CTIOUTEN0 Details Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event
Appendix B: Register Details Register CTIOUTEN1 Details Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels.
Appendix B: Register Details Register (cti) CTIOUTEN3 Name CTIOUTEN3 Relative Address 0x000000AC Absolute Address debug_cpu_cti0: 0xF88980AC debug_cpu_cti1: 0xF88990AC debug_cti_etb_tpiu: 0xF88020AC debug_cti_ftm: 0xF88090AC Width 4 bits Access Type rw Reset Value 0x00000000 Description CTI Channel to Trigger Enable 3 Register Register CTIOUTEN3 Details Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event
Appendix B: Register Details Register CTIOUTEN4 Details Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels.
Appendix B: Register Details Register (cti) CTIOUTEN6 Name CTIOUTEN6 Relative Address 0x000000B8 Absolute Address debug_cpu_cti0: 0xF88980B8 debug_cpu_cti1: 0xF88990B8 debug_cti_etb_tpiu: 0xF88020B8 debug_cti_ftm: 0xF88090B8 Width 4 bits Access Type rw Reset Value 0x00000000 Description CTI Channel to Trigger Enable 6 Register Register CTIOUTEN6 Details Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event
Appendix B: Register Details Register CTIOUTEN7 Details Field Name TRIGOUTEN Bits 3:0 Type rw Reset Value 0x0 Description Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate an CTITRIGOUT output: 0 = the channel input (CTICHIN) from the CTM is not routed to the CTITRIGOUT output 1 = the channel input (CTICHIN) from the CTM is routed to the CTITRIGOUT output. There is one bit for each of the four channels.
Appendix B: Absolute Address Register Details debug_cpu_cti0: 0xF8898134 debug_cpu_cti1: 0xF8899134 debug_cti_etb_tpiu: 0xF8802134 debug_cti_ftm: 0xF8809134 Width 8 bits Access Type ro Reset Value 0x00000000 Description CTI Trigger Out Status Register Register CTITRIGOUTSTATUS Details Field Name Bits TRIGOUTSTATUS 7:0 Type ro Reset Value 0x0 Description Shows the status of the CTITRIGOUT outputs. 1 = CTITRIGOUT is active 0 = CTITRIGOUT is inactive (reset).
Appendix B: Register Details Register (cti) CTICHOUTSTATUS Name CTICHOUTSTATUS Relative Address 0x0000013C Absolute Address debug_cpu_cti0: 0xF889813C debug_cpu_cti1: 0xF889913C debug_cti_etb_tpiu: 0xF880213C debug_cti_ftm: 0xF880913C Width 4 bits Access Type ro Reset Value 0x00000000 Description CTI Channel Out Status Register Register CTICHOUTSTATUS Details Field Name Bits CTCHOUTSTATUS 3:0 Type ro Reset Value 0x0 Description Shows the status of the CTICHOUT outputs.
Appendix B: Field Name Bits Type Reset Value Register Details Description CTIGATEEN1 1 rw 0x1 Enable CTICHOUT1. CTIGATEEN0 0 rw 0x1 Enable CTICHOUT0.
Appendix B: Register Details Register (cti) ITTRIGINACK Name ITTRIGINACK Relative Address 0x00000EE0 Absolute Address debug_cpu_cti0: 0xF8898EE0 debug_cpu_cti1: 0xF8899EE0 debug_cti_etb_tpiu: 0xF8802EE0 debug_cti_ftm: 0xF8809EE0 Width 8 bits Access Type wo Reset Value 0x00000000 Description ITTRIGINACK Register Register ITTRIGINACK Details Field Name CTTRIGINACK Bits 7:0 Type wo Reset Value 0x0 Description Set the value of the CTTRIGINACK outputs Register (cti) ITCHOUT Name ITCHOUT Re
Appendix B: Absolute Address Register Details debug_cpu_cti0: 0xF8898EE8 debug_cpu_cti1: 0xF8899EE8 debug_cti_etb_tpiu: 0xF8802EE8 debug_cti_ftm: 0xF8809EE8 Width 8 bits Access Type wo Reset Value 0x00000000 Description ITTRIGOUT Register Register ITTRIGOUT Details Field Name CTTRIGOUT Bits 7:0 Type wo Reset Value 0x0 Description Set the value of the CTTRIGOUT outputs Register (cti) ITCHOUTACK Name ITCHOUTACK Relative Address 0x00000EEC Absolute Address debug_cpu_cti0: 0xF8898EEC debug
Appendix B: Width 8 bits Access Type ro Reset Value 0x00000000 Description ITTRIGOUTACK Register Register Details Register ITTRIGOUTACK Details Field Name CTTRIGOUTACK Bits 7:0 Type ro Reset Value 0x0 Description Read the values of the CTTRIGOUTACK inputs Register (cti) ITCHIN Name ITCHIN Relative Address 0x00000EF4 Absolute Address debug_cpu_cti0: 0xF8898EF4 debug_cpu_cti1: 0xF8899EF4 debug_cti_etb_tpiu: 0xF8802EF4 debug_cti_ftm: 0xF8809EF4 Width 4 bits Access Type ro Reset Value
Appendix B: Description Register Details ITTRIGIN Register Register ITTRIGIN Details Field Name CTTRIGIN Bits 7:0 Type ro Reset Value 0x0 Description Read the values of the CTTRIGIN inputs Register (cti) ITCTRL Name ITCTRL Relative Address 0x00000F00 Absolute Address debug_cpu_cti0: 0xF8898F00 debug_cpu_cti1: 0xF8899F00 debug_cti_etb_tpiu: 0xF8802F00 debug_cti_ftm: 0xF8809F00 Width 1 bits Access Type rw Reset Value 0x00000000 Description IT Control Register Register ITCTRL Details Fie
Appendix B: Register Details Register CTSR Details Field Name SET Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Appendix B: Width 32 bits Access Type wo Reset Value 0x00000000 Description Lock Access Register Register Details Register LAR Details Field Name KEY Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register.
Appendix B: Register Details Register LSR Details Field Name Bits Type Reset Value Description 8BIT 2 ro 0x0 Set to 0 since CTI implements a 32-bit lock access register STATUS 1 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether CTI is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0.
Appendix B: Register Details Register (cti) DEVID Name DEVID Relative Address 0x00000FC8 Absolute Address debug_cpu_cti0: 0xF8898FC8 debug_cpu_cti1: 0xF8899FC8 debug_cti_etb_tpiu: 0xF8802FC8 debug_cti_ftm: 0xF8809FC8 Width 20 bits Access Type ro Reset Value 0x00040800 Description Device ID Register DEVID Details Field Name Bits Type Reset Value Description NumChan 19:16 ro 0x4 Number of channels available NumTrig 15:8 ro 0x8 Number of triggers available res 7:5 ro 0x0 rese
Appendix B: Register Details Register (cti) PERIPHID4 Name PERIPHID4 Relative Address 0x00000FD0 Absolute Address debug_cpu_cti0: 0xF8898FD0 debug_cpu_cti1: 0xF8899FD0 debug_cti_etb_tpiu: 0xF8802FD0 debug_cti_ftm: 0xF8809FD0 Width 8 bits Access Type ro Reset Value 0x00000004 Description Peripheral ID4 Register PERIPHID4 Details Field Name Bits Type Reset Value Description 4KB_count 7:4 ro 0x0 4KB Count, set to 0 JEP106ID 3:0 ro 0x4 JEP106 continuation code Register (cti) PERIP
Appendix B: Relative Address 0x00000FD8 Absolute Address debug_cpu_cti0: 0xF8898FD8 Register Details debug_cpu_cti1: 0xF8899FD8 debug_cti_etb_tpiu: 0xF8802FD8 debug_cti_ftm: 0xF8809FD8 Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID6 Register PERIPHID6 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (cti) PERIPHID7 Name PERIPHID7 Relative Address 0x00000FDC Absolute Address debug_cpu_cti0: 0xF8898FDC debug_cpu_cti1: 0xF88
Appendix B: Absolute Address Register Details debug_cpu_cti0: 0xF8898FE0 debug_cpu_cti1: 0xF8899FE0 debug_cti_etb_tpiu: 0xF8802FE0 debug_cti_ftm: 0xF8809FE0 Width 8 bits Access Type ro Reset Value 0x00000006 Description Peripheral ID0 Register PERIPHID0 Details Field Name Bits 7:0 Type ro Reset Value 0x6 Description PartNumber0 Register (cti) PERIPHID1 Name PERIPHID1 Relative Address 0x00000FE4 Absolute Address debug_cpu_cti0: 0xF8898FE4 debug_cpu_cti1: 0xF8899FE4 debug_cti_etb_tpiu: 0
Appendix B: Absolute Address Register Details debug_cpu_cti0: 0xF8898FE8 debug_cpu_cti1: 0xF8899FE8 debug_cti_etb_tpiu: 0xF8802FE8 debug_cti_ftm: 0xF8809FE8 Width 8 bits Access Type ro Reset Value 0x0000002B Description Peripheral ID2 Register PERIPHID2 Details Field Name Bits Type Reset Value Description RevNum 7:4 ro 0x2 Revision number of Peripheral JEDEC 3 ro 0x1 Indicates that a JEDEC assigned value is used JEP106ID 2:0 ro 0x3 JEP106 Identity Code [6:4] Register (cti) PE
Appendix B: Absolute Address Register Details debug_cpu_cti0: 0xF8898FF0 debug_cpu_cti1: 0xF8899FF0 debug_cti_etb_tpiu: 0xF8802FF0 debug_cti_ftm: 0xF8809FF0 Width 8 bits Access Type ro Reset Value 0x0000000D Description Component ID0 Register COMPID0 Details Field Name Bits 7:0 Type ro Reset Value 0xD Description Preamble Register (cti) COMPID1 Name COMPID1 Relative Address 0x00000FF4 Absolute Address debug_cpu_cti0: 0xF8898FF4 debug_cpu_cti1: 0xF8899FF4 debug_cti_etb_tpiu: 0xF8802FF4
Appendix B: Width 8 bits Access Type ro Reset Value 0x00000005 Description Component ID2 Register Details Register COMPID2 Details Field Name Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (cti) COMPID3 Name COMPID3 Relative Address 0x00000FFC Absolute Address debug_cpu_cti0: 0xF8898FFC debug_cpu_cti1: 0xF8899FFC debug_cti_etb_tpiu: 0xF8802FFC debug_cti_ftm: 0xF8809FFC Width 8 bits Access Type ro Reset Value 0x000000B1 Description Component ID3 Register COMPID3 D
Appendix B: Register Details B.
Appendix B: Register Details Register (cortexa9_pmu) PMXEVCNTR0 Name PMXEVCNTR0 Relative Address 0x00000000 Absolute Address debug_cpu_pmu0: 0xF8891000 debug_cpu_pmu1: 0xF8893000 Width 32 bits Access Type rw Reset Value x Description PMU event counter 0 Register PMXEVCNTR0 Details Field Name PMXEVCNTR0 Bits 31:0 Type rw Reset Value x Description PMU event counter 0 Register (cortexa9_pmu) PMXEVCNTR1 Name PMXEVCNTR1 Relative Address 0x00000004 Absolute Address debug_cpu_pmu0: 0xF889
Appendix B: Access Type rw Reset Value x Description PMU event counter 2 Register Details Register PMXEVCNTR2 Details Field Name PMXEVCNTR2 Bits 31:0 Type rw Reset Value x Description PMU event counter 2 Register (cortexa9_pmu) PMXEVCNTR3 Name PMXEVCNTR3 Relative Address 0x0000000C Absolute Address debug_cpu_pmu0: 0xF889100C debug_cpu_pmu1: 0xF889300C Width 32 bits Access Type rw Reset Value x Description PMU event counter 3 Register PMXEVCNTR3 Details Field Name PMXEVCNTR3 Bits
Appendix B: Register Details Register (cortexa9_pmu) PMXEVCNTR5 Name PMXEVCNTR5 Relative Address 0x00000014 Absolute Address debug_cpu_pmu0: 0xF8891014 debug_cpu_pmu1: 0xF8893014 Width 32 bits Access Type rw Reset Value x Description PMU event counter 5 Register PMXEVCNTR5 Details Field Name PMXEVCNTR5 Bits 31:0 Type rw Reset Value x Description PMU event counter 5 Register (cortexa9_pmu) PMCCNTR Name PMCCNTR Relative Address 0x0000007C Absolute Address debug_cpu_pmu0: 0xF889107C d
Appendix B: Access Type rw Reset Value x Description pmevtyper0 Register Details Register PMXEVTYPER0 Details Field Name PMXEVTYPER0 Bits 31:0 Type rw Reset Value x Description pmevtyper0 Register (cortexa9_pmu) PMXEVTYPER1 Name PMXEVTYPER1 Relative Address 0x00000404 Absolute Address debug_cpu_pmu0: 0xF8891404 debug_cpu_pmu1: 0xF8893404 Width 32 bits Access Type rw Reset Value x Description pmevtyper1 Register PMXEVTYPER1 Details Field Name PMXEVTYPER1 Bits 31:0 Type rw Reset
Appendix B: Register Details Register (cortexa9_pmu) PMXEVTYPER3 Name PMXEVTYPER3 Relative Address 0x0000040C Absolute Address debug_cpu_pmu0: 0xF889140C debug_cpu_pmu1: 0xF889340C Width 32 bits Access Type rw Reset Value x Description pmevtyper3 Register PMXEVTYPER3 Details Field Name PMXEVTYPER3 Bits 31:0 Type rw Reset Value x Description pmevtyper3 Register (cortexa9_pmu) PMXEVTYPER4 Name PMXEVTYPER4 Relative Address 0x00000410 Absolute Address debug_cpu_pmu0: 0xF8891410 debug_c
Appendix B: Access Type rw Reset Value x Description pmevtyper5 Register Details Register PMXEVTYPER5 Details Field Name PMXEVTYPER5 Bits 31:0 Type rw Reset Value x Description pmevtyper5 Register (cortexa9_pmu) PMCNTENSET Name PMCNTENSET Relative Address 0x00000C00 Absolute Address debug_cpu_pmu0: 0xF8891C00 debug_cpu_pmu1: 0xF8893C00 Width 32 bits Access Type rw Reset Value 0x00000000 Description pmcntenset Register PMCNTENSET Details Field Name PMCNTENSET Bits 31:0 Type rw R
Appendix B: Register Details Register (cortexa9_pmu) PMINTENSET Name PMINTENSET Relative Address 0x00000C40 Absolute Address debug_cpu_pmu0: 0xF8891C40 debug_cpu_pmu1: 0xF8893C40 Width 32 bits Access Type rw Reset Value 0x00000000 Description pmintenset Register PMINTENSET Details Field Name PMINTENSET Bits 31:0 Type rw Reset Value 0x0 Description pmintenset Register (cortexa9_pmu) PMINTENCLR Name PMINTENCLR Relative Address 0x00000C60 Absolute Address debug_cpu_pmu0: 0xF8891C60 de
Appendix B: Access Type rw Reset Value x Description pmovsr Register Details Register PMOVSR Details Field Name PMOVSR Bits 31:0 Type rw Reset Value x Description pmovsr Register (cortexa9_pmu) PMSWINC Name PMSWINC Relative Address 0x00000CA0 Absolute Address debug_cpu_pmu0: 0xF8891CA0 debug_cpu_pmu1: 0xF8893CA0 Width 32 bits Access Type wo Reset Value x Description pmswinc Register PMSWINC Details Field Name PMSWINC Bits 31:0 Type wo Reset Value x Description pmswinc Registe
Appendix B: Register Details Register (cortexa9_pmu) PMUSERENR Name PMUSERENR Relative Address 0x00000E08 Absolute Address debug_cpu_pmu0: 0xF8891E08 debug_cpu_pmu1: 0xF8893E08 Width 32 bits Access Type rw Reset Value 0x00000000 Description pmuserenr Register PMUSERENR Details Field Name PMUSERENR Bits 31:0 Type rw Reset Value 0x0 Description pmuserenr This register is read-only in user mode. Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description ETMACTR3 0x00000088 12 mixed 0x00000001 Address Comparator Access Type Register 3 ETMACTR4 0x0000008C 12 mixed 0x00000001 Address Comparator Access Type Register 4 ETMACTR5 0x00000090 12 mixed 0x00000001 Address Comparator Access Type Register 5 ETMACTR6 0x00000094 12 mixed 0x00000001 Address Comparator Access Type Register 6 ETMACTR7 0x00000098 12 mixed 0x00000001 Address Comparator Ac
Appendix B: Register Name Address Width Type Reset Value Register Details Description ETMCIDCMR 0x000001BC 32 rw 0x00000000 Context ID Comparator Mask Register ETMSYNCFR 0x000001E0 12 mixed 0x00000400 Synchronization Frequency Register ETMIDR 0x000001E4 32 ro 0x411CF301 ID Register ETMCCER 0x000001E8 26 ro 0x000008EA Configuration Code Extension Register ETMEXTINSELR 0x000001EC 14 rw 0x00000000 Extended External Input Selection Register ETMAUXCR 0x000001FC 4 rw 0x00
Appendix B: Register Name Address Width Type Reset Value Register Details Description PERIPHID2 0x00000FE8 8 ro 0x0000001B Peripheral ID2 PERIPHID3 0x00000FEC 8 ro 0x00000000 Peripheral ID3 COMPID0 0x00000FF0 8 ro 0x0000000D Component ID0 COMPID1 0x00000FF4 8 ro 0x00000090 Component ID1 COMPID2 0x00000FF8 8 ro 0x00000005 Component ID2 COMPID3 0x00000FFC 8 ro 0x000000B1 Component ID3 Register (ptm) ETMCR Name ETMCR Relative Address 0x00000000 Absolute Address
Appendix B: Field Name Bits DebugReqCtrl 9 Type rw Reset Value 0x0 Register Details Description Debug Request Control When set to b1 and the trigger event occurs, the PTMDBGRQ output is asserted until PTMDBGACK is observed. This enables a debugger to force the processor into Debug state. BranchOutput 8 rw 0x0 When this bit is set to b1, addresses are output for all executed branches, both direct and indirect.
Appendix B: Field Name Bits Type Reset Value Register Details Description NumExtIn 19:17 ro 0x4 Specifies the number of external inputs, four. Sequencer 16 ro 0x1 Indicates that the sequencer is present. NumCounters 15:13 ro 0x2 Specifies the number of counters, two. reserved 12:4 ro 0x0 Reserved NumAddrComp 3:0 ro 0x4 Specifies the number of address comparator pairs, four.
Appendix B: Description Register Details Status Register Register ETMSR Details Field Name Bits Type Reset Value Description TrigFlag 3 rw 0x0 Trigger bit. Set when the trigger occurs and prevents the trigger from being output until the PTM is next programmed. TSSRStat 2 rw 0x0 Holds the current status of the trace start/stop resource. If set to 1, indicates that a trace start address has been matched, without a corresponding trace stop address match.
Appendix B: Absolute Address Register Details debug_cpu_ptm0: 0xF889C018 debug_cpu_ptm1: 0xF889D018 Width 24 bits Access Type rw Reset Value 0x00000000 Description TraceEnable Start/Stop Control Register Register ETMTSSCR Details Field Name StopAddrSel Bits 23:16 Type rw Reset Value 0x0 Description When a bit is set to 1, it selects a single address comparator (8-1) as a stop address for the TraceEnable Start/Stop block.
Appendix B: Register Details Register ETMTECR1 Details Field Name TraceSSEn Bits 25 Type rw Reset Value 0x0 Description Trace start/stop control enable. The possible values of this bit are: 0 Tracing is unaffected by the trace start/stop logic. 1 Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. The trace start/stop resource is not affected by the value of this bit. ExcIncFlag 24 rw 0x0 Exclude/include flag.
Appendix B: Register Details Register (ptm) ETMACVR2 Name ETMACVR2 Relative Address 0x00000044 Absolute Address debug_cpu_ptm0: 0xF889C044 debug_cpu_ptm1: 0xF889D044 Width 32 bits Access Type rw Reset Value 0x00000000 Description Address Comparator Value Register 2 Register ETMACVR2 Details Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison Register (ptm) ETMACVR3 Name ETMACVR3 Relative Address 0x00000048 Absolute Address debug_cpu_ptm0: 0xF889C
Appendix B: Access Type rw Reset Value 0x00000000 Description Address Comparator Value Register 4 Register Details Register ETMACVR4 Details Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison Register (ptm) ETMACVR5 Name ETMACVR5 Relative Address 0x00000050 Absolute Address debug_cpu_ptm0: 0xF889C050 debug_cpu_ptm1: 0xF889D050 Width 32 bits Access Type rw Reset Value 0x00000000 Description Address Comparator Value Register 5 Register ETMACVR5 D
Appendix B: Register Details Register (ptm) ETMACVR7 Name ETMACVR7 Relative Address 0x00000058 Absolute Address debug_cpu_ptm0: 0xF889C058 debug_cpu_ptm1: 0xF889D058 Width 32 bits Access Type rw Reset Value 0x00000000 Description Address Comparator Value Register 7 Register ETMACVR7 Details Field Name Address Bits 31:0 Type rw Reset Value 0x0 Description Address for comparison Register (ptm) ETMACVR8 Name ETMACVR8 Relative Address 0x0000005C Absolute Address debug_cpu_ptm0: 0xF889C
Appendix B: Access Type mixed Reset Value 0x00000001 Description Address Comparator Access Type Register 1 Register Details Register ETMACTR1 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type.
Appendix B: Register Details Register ETMACTR2 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Register Details Register ETMACTR3 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Register Details Register ETMACTR4 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Register Details Register ETMACTR5 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Register Details Register ETMACTR6 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Register Details Register ETMACTR7 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Register Details Register ETMACTR8 Details Field Name Bits SecLevelCtrl 11:10 Type rw Reset Value 0x0 Description Security level control Enumerated Value List: IGNORE=0. NONSEC=1. SECURE=2. ContextIDCompCtrl 9:8 rw 0x0 Context ID comparator control. Enumerated Value List: IGNORE=0. MATCH1=1. MATCH2=2. MATCH3=3. reserved 7:3 rw 0x0 Reserved AccessType 2:0 ro 0x1 Access type. Returns the value: Instruction execute.
Appendix B: Width 16 bits Access Type rw Reset Value 0x00000000 Description Counter Reload Value Register 2 Register Details Register ETMCNTRLDVR2 Details Field Name InitValue Bits 15:0 Type rw Reset Value 0x0 Description Counter initial value Register (ptm) ETMCNTENR1 Name ETMCNTENR1 Relative Address 0x00000150 Absolute Address debug_cpu_ptm0: 0xF889C150 debug_cpu_ptm1: 0xF889D150 Width 18 bits Access Type mixed Reset Value 0x00020000 Description Counter Enable Event Register 1
Appendix B: Width 18 bits Access Type mixed Reset Value 0x00020000 Description Counter Enable Event Register 2 Register Details Register ETMCNTENR2 Details Field Name Bits Type Reset Value Description Reserved_1 17 ro 0x1 Reserved, RAO/WI ExtOutEvent 16:0 rw 0x0 Count enable event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event.
Appendix B: Register Details Register (ptm) ETMCNTRLDEVR2 Name ETMCNTRLDEVR2 Relative Address 0x00000164 Absolute Address debug_cpu_ptm0: 0xF889C164 debug_cpu_ptm1: 0xF889D164 Width 17 bits Access Type rw Reset Value 0x00000000 Description Counter Reload Event Register 2 Register ETMCNTRLDEVR2 Details Field Name CntReloadEvent Bits 16:0 Type rw Reset Value 0x0 Description Count reload event.
Appendix B: Register Details Register (ptm) ETMCNTVR2 Name ETMCNTVR2 Relative Address 0x00000174 Absolute Address debug_cpu_ptm0: 0xF889C174 debug_cpu_ptm1: 0xF889D174 Width 16 bits Access Type rw Reset Value 0x00000000 Description Counter Value Register 2 Register ETMCNTVR2 Details Field Name CurrCount Bits 15:0 Type rw Reset Value 0x0 Description Current counter value.
Appendix B: Register Details Register (ptm) ETMSQ21EVR Name ETMSQ21EVR Relative Address 0x00000184 Absolute Address debug_cpu_ptm0: 0xF889C184 debug_cpu_ptm1: 0xF889D184 Width 17 bits Access Type rw Reset Value 0x00000000 Description Sequencer State Transition Event Register 21 Register ETMSQ21EVR Details Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition
Appendix B: Register Details Register ETMSQ23EVR Details Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event.
Appendix B: Relative Address 0x00000190 Absolute Address debug_cpu_ptm0: 0xF889C190 Register Details debug_cpu_ptm1: 0xF889D190 Width 17 bits Access Type rw Reset Value 0x00000000 Description Sequencer State Transition Event Register 32 Register ETMSQ32EVR Details Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n.
Appendix B: Register Details Register ETMSQ13EVR Details Field Name TransEvent Bits 16:0 Type rw Reset Value 0x0 Description A Sequencer State Transition Event Register, ETMSQmnEVR, defines the evnet that causes the sequencer state transition from state m to state n. The format is subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event.
Appendix B: Register Details Register ETMEXTOUTEVR1 Details Field Name ExtOutputEvent Bits 16:0 Type rw Reset Value 0x0 Description External output event. Subdivided as: Function, bits [16:14] Specifies the function that combines the two resources that define the event. Resource B, bits [13:7] and Resource A, bits [6:0] Specify the two resources that are combined by the logical operation specified by the Function field.
Appendix B: Access Type rw Reset Value 0x00000000 Description Context ID Comparator Value Register Register Details Register ETMCIDCVR1 Details Field Name ContextID Bits 31:0 Type rw Reset Value 0x0 Description Holds a 32-bit Context ID value Register (ptm) ETMCIDCMR Name ETMCIDCMR Relative Address 0x000001BC Absolute Address debug_cpu_ptm0: 0xF889C1BC debug_cpu_ptm1: 0xF889D1BC Width 32 bits Access Type rw Reset Value 0x00000000 Description Context ID Comparator Mask Register Reg
Appendix B: Register Details Register ETMSYNCFR Details Field Name Bits Type Reset Value Description SyncFreq 11:2 rw 0x100 Synchronization frequency reserved 1:0 ro 0x0 Reserved Register (ptm) ETMIDR Name ETMIDR Relative Address 0x000001E4 Absolute Address debug_cpu_ptm0: 0xF889C1E4 debug_cpu_ptm1: 0xF889D1E4 Width 32 bits Access Type ro Reset Value 0x411CF301 Description ID Register Register ETMIDR Details Field Name Bits Type Reset Value Description ImplCode 31:24 ro
Appendix B: Access Type ro Reset Value 0x000008EA Description Configuration Code Extension Register Register Details Register ETMCCER Details Field Name Bits Type Reset Value Description BarrTS 25 ro 0x0 Timestamps are not generated for DMB/DSB BarrWP 24 ro 0x0 DMB/DSB instructions are not treated as waypoints. RetStack 23 ro 0x0 Return stack implemented. Timestamp 22 ro 0x0 Timestamping implemented.
Appendix B: Register Details Register (ptm) ETMAUXCR Name ETMAUXCR Relative Address 0x000001FC Absolute Address debug_cpu_ptm0: 0xF889C1FC debug_cpu_ptm1: 0xF889D1FC Width 4 bits Access Type rw Reset Value 0x00000000 Description Auxiliary Control Register Register ETMAUXCR Details Field Name ForceSyncInsert Bits 3 Type rw Reset Value 0x0 Description Force insertion of synchronization packets, regardless of current trace activity.
Appendix B: Field Name DisableTSOnBarr Bits 1 Type rw Reset Value 0x0 Register Details Description Specifies whether the PTM issues a timestamp on a barrier instruction. Possible values for this bit are: b0 = PTM issues timestamps on barrier instructions. This is the reset value. b1 = PTM does not issue timestamps on barriers DisableForcedOF 0 rw 0x0 Specifies whether the PTM enters overflow state when synchronization is requested, and the previous synchronization sequence has not yet completed.
Appendix B: Width 32 bits Access Type ro Reset Value 0x00000000 Description OS Lock Status Register Register Details Register OSLSR Details Field Name Bits 31:0 Type ro Reset Value 0x0 Description Shows that OS Locking is not implemented.
Appendix B: Register Details Register ITMISCOUT Details Field Name Bits Type Reset Value Description PTMEXTOUT 9:8 wo 0x0 Drives the PTMEXTOUT[1:0] outputs reserved 7:6 wo 0x0 Reserved PTMIDLEACK 5 wo 0x0 Drives the PTMIDLEACK output PTMDBGREQ 4 wo 0x0 Drives the PTMDBGREQ output reserved 3:0 wo 0x0 Reserved Register (ptm) ITMISCIN Name ITMISCIN Relative Address 0x00000EE0 Absolute Address debug_cpu_ptm0: 0xF889CEE0 debug_cpu_ptm1: 0xF889DEE0 Width 7 bits Access Type
Appendix B: Register Details Register ITTRIGGER Details Field Name PTMTRIGGER Bits 0 Type wo Reset Value 0x0 Description Drives the PTMTRIGGER output Register (ptm) ITATBDATA0 Name ITATBDATA0 Relative Address 0x00000EEC Absolute Address debug_cpu_ptm0: 0xF889CEEC debug_cpu_ptm1: 0xF889DEEC Width 5 bits Access Type wo Reset Value 0x00000000 Description ATB Data 0 Register Register ITATBDATA0 Details Field Name Bits Type Reset Value Description ATDATAM31 4 wo 0x0 Drives the ATDAT
Appendix B: Register Details Register ITATBCTR2 Details Field Name Bits Type Reset Value Description AFVALIDM 1 ro x Returns the value of the AFVALIDM input ATREADYM 0 ro x Returns the value of the ATREADYM input Register (ptm) ITATBID Name ITATBID Relative Address 0x00000EF4 Absolute Address debug_cpu_ptm0: 0xF889CEF4 debug_cpu_ptm1: 0xF889DEF4 Width 7 bits Access Type wo Reset Value 0x00000000 Description ATB Identification Register Register ITATBID Details Field Name ATIDM
Appendix B: Field Name Bits Type Reset Value Register Details Description AFREADYM 1 wo 0x0 Drives the AFREADYM output ATVALIDM 0 wo 0x0 Drives the ATVALIDM output Register (ptm) ETMITCTRL Name ETMITCTRL Relative Address 0x00000F00 Absolute Address debug_cpu_ptm0: 0xF889CF00 debug_cpu_ptm1: 0xF889DF00 Width 1 bits Access Type rw Reset Value 0x00000000 Description Integration Mode Control Register Register ETMITCTRL Details Field Name Bits 0 Type rw Reset Value 0x0 Descript
Appendix B: Register Details Register CTSR Details Field Name Bits 7:0 Type rw Reset Value 0xFF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Appendix B: Description Register Details Lock Access Register Register LAR Details Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), PTM is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register.
Appendix B: Register Details Register LSR Details Field Name Bits Type Reset Value Description 8BIT 2 ro 0x0 Set to 0 since PTM implements a 32-bit lock access register STATUS 1 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether PTM is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0.
Appendix B: Field Name NSNI Bits 3:2 Type ro Reset Value x Register Details Description Non-secure non-invasive debug IF NIDEN or DBGEN is 1, this field is 2'b11, indicating the functionality is implemented and enabled. Otherwise, this field is 2'b10 (implemented but disabled) NSI 1:0 ro 0x0 Non-secure invasive debug Always 2'b00. This functionality is not implemented.
Appendix B: Register Details Register DTIR Details Field Name Bits 7:0 Type ro Reset Value 0x13 Description A trace source and processor trace Register (ptm) PERIPHID4 Name PERIPHID4 Relative Address 0x00000FD0 Absolute Address debug_cpu_ptm0: 0xF889CFD0 debug_cpu_ptm1: 0xF889DFD0 Width 8 bits Access Type ro Reset Value 0x00000004 Description Peripheral ID4 Register PERIPHID4 Details Field Name Bits Type Reset Value Description 4KB_count 7:4 ro 0x0 4KB Count, set to 0 JEP106ID
Appendix B: Register Details Register (ptm) PERIPHID6 Name PERIPHID6 Relative Address 0x00000FD8 Absolute Address debug_cpu_ptm0: 0xF889CFD8 debug_cpu_ptm1: 0xF889DFD8 Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID6 Register PERIPHID6 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (ptm) PERIPHID7 Name PERIPHID7 Relative Address 0x00000FDC Absolute Address debug_cpu_ptm0: 0xF889CFDC debug_cpu_ptm1: 0xF889DFDC Width 8
Appendix B: Access Type ro Reset Value 0x00000050 Description Peripheral ID0 Register Details Register PERIPHID0 Details Field Name Bits 7:0 Type ro Reset Value 0x50 Description PartNumber0 Register (ptm) PERIPHID1 Name PERIPHID1 Relative Address 0x00000FE4 Absolute Address debug_cpu_ptm0: 0xF889CFE4 debug_cpu_ptm1: 0xF889DFE4 Width 8 bits Access Type ro Reset Value 0x000000B9 Description Peripheral ID1 Register PERIPHID1 Details Field Name Bits Type Reset Value Description J
Appendix B: Register Details Register PERIPHID2 Details Field Name Bits Type Reset Value Description RevNum 7:4 ro 0x1 Revision number of Peripheral JEDEC 3 ro 0x1 Indicates that a JEDEC assigned value is used JEP106ID 2:0 ro 0x3 JEP106 Identity Code [6:4] Register (ptm) PERIPHID3 Name PERIPHID3 Relative Address 0x00000FEC Absolute Address debug_cpu_ptm0: 0xF889CFEC debug_cpu_ptm1: 0xF889DFEC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID3 Re
Appendix B: Register Details Register (ptm) COMPID1 Name COMPID1 Relative Address 0x00000FF4 Absolute Address debug_cpu_ptm0: 0xF889CFF4 debug_cpu_ptm1: 0xF889DFF4 Width 8 bits Access Type ro Reset Value 0x00000090 Description Component ID1 Register COMPID1 Details Field Name Bits 7:0 Type ro Reset Value 0x90 Description Preamble Register (ptm) COMPID2 Name COMPID2 Relative Address 0x00000FF8 Absolute Address debug_cpu_ptm0: 0xF889CFF8 debug_cpu_ptm1: 0xF889DFF8 Width 8 bits Acc
Appendix B: Access Type ro Reset Value 0x000000B1 Description Component ID3 Register Details Register COMPID3 Details Field Name Bits 7:0 Type ro Reset Value 0xB1 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 Description Preamble www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description COMPID0 0x00000FF0 8 ro 0x0000000D Component ID0 COMPID1 0x00000FF4 8 ro 0x00000010 Component ID1 COMPID2 0x00000FF8 8 ro 0x00000005 Component ID2 COMPID3 0x00000FFC 8 ro 0x000000B1 Component ID3 Register (dap) ROMENTRY00 Name ROMENTRY00 Relative Address 0x00000000 Absolute Address 0xF8800000 Width 32 bits Access Type ro Reset Value 0x00001003 Description ROM entry 00 Register
Appendix B: Reset Value 0x00002003 Description ROM entry 01 Register Details Register ROMENTRY01 Details Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x2 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved 11:2 ro 0x0 Format 1 ro 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0.
Appendix B: Field Name Format Bits 1 Type ro Reset Value 0x1 Register Details Description Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.
Appendix B: Reset Value 0x00005003 Description ROM entry 04 Register Details Register ROMENTRY04 Details Field Name AddressOffset Bits 31:12 Type ro Reset Value 0x5 Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved 11:2 ro 0x0 Format 1 ro 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0.
Appendix B: Field Name Format Bits 1 Type ro Reset Value 0x1 Register Details Description Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.
Appendix B: Reset Value 0x0000B003 Description ROM entry 07 Register Details Register ROMENTRY07 Details Field Name AddressOffset Bits 31:12 Type ro Reset Value 0xB Description Base address of the component, relative to the ROM address. Negative values are permitted using two's complement. ComponentAddress = ROMAddress + (AddressOffset SHL 12) reserved 11:2 ro 0x0 Format 1 ro 0x1 Reserved Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0.
Appendix B: Field Name Format Bits 1 Type ro Reset Value 0x1 Register Details Description Format of ROM entry Enumerated Value List: 32BIT=1. 8BIT=0. EntryPresent 0 ro 0x1 Set HIGH to indicate an entry is present.
Appendix B: Reset Value 0x00000000 Description ROM entry 10 Register Details Register ROMENTRY10 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Invalid entry Register (dap) ROMENTRY11 Name ROMENTRY11 Relative Address 0x0000002C Absolute Address 0xF880002C Width 32 bits Access Type rw Reset Value 0x00000000 Description ROM entry 11 Register ROMENTRY11 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Invalid entry Register (dap) ROMENTRY12 Name
Appendix B: Register Details Register (dap) ROMENTRY13 Name ROMENTRY13 Relative Address 0x00000034 Absolute Address 0xF8800034 Width 32 bits Access Type rw Reset Value 0x00000000 Description ROM entry 13 Register ROMENTRY13 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Invalid entry Register (dap) ROMENTRY14 Name ROMENTRY14 Relative Address 0x00000038 Absolute Address 0xF8800038 Width 32 bits Access Type rw Reset Value 0x00000000 Description ROM entry 14
Appendix B: Register Details Register ROMENTRY15 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Invalid entry Register (dap) PERIPHID4 Name PERIPHID4 Relative Address 0x00000FD0 Absolute Address 0xF8800FD0 Width 8 bits Access Type ro Reset Value 0x00000003 Description Peripheral ID4 Register PERIPHID4 Details Field Name 4KB_count Bits Type Reset Value Description 7:4 ro 0x0 4KB Count, set to 0 3:0 ro 0x3 JEP106 continuation code Register (dap) PERIPHID5 Na
Appendix B: Relative Address 0x00000FD8 Absolute Address 0xF8800FD8 Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID6 Register Details Register PERIPHID6 Details Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Description Reserved Register (dap) PERIPHID7 Name PERIPHID7 Relative Address 0x00000FDC Absolute Address 0xF8800FDC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID7 Register PERIPHID7 Details Field Name res
Appendix B: Register Details Register PERIPHID0 Details Field Name PartNumber0 Bits 7:0 Type ro Reset Value 0xB2 Description PartNumber0 Register (dap) PERIPHID1 Name PERIPHID1 Relative Address 0x00000FE4 Absolute Address 0xF8800FE4 Width 8 bits Access Type ro Reset Value 0x00000093 Description Peripheral ID1 Register PERIPHID1 Details Field Name Bits Type Reset Value Description JEP106ID 7:4 ro 0x9 JEP106 Identity Code [3:0] PartNumber1 3:0 ro 0x3 PartNumber1 Register (d
Appendix B: Register Details Register (dap) PERIPHID3 Name PERIPHID3 Relative Address 0x00000FEC Absolute Address 0xF8800FEC Width 8 bits Access Type ro Reset Value 0x00000007 Description Peripheral ID3 Register PERIPHID3 Details Field Name Bits Type Reset Value Description RevAnd 7:4 ro 0x0 RevAnd, at top level CustMod 3:0 ro 0x7 Customer Modified Register (dap) COMPID0 Name COMPID0 Relative Address 0x00000FF0 Absolute Address 0xF8800FF0 Width 8 bits Access Type ro
Appendix B: Description Register Details Component ID1 Register COMPID1 Details Field Name Preamble Bits 7:0 Type ro Reset Value 0x10 Description Preamble Register (dap) COMPID2 Name COMPID2 Relative Address 0x00000FF8 Absolute Address 0xF8800FF8 Width 8 bits Access Type ro Reset Value 0x00000005 Description Component ID2 Register COMPID2 Details Field Name Preamble Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (dap) COMPID3 Name COMPID3 Relative Address 0x000
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description CTSR 0x00000FA0 4 rw 0x0000000F Claim Tag Set Register CTCR 0x00000FA4 4 rw 0x00000000 Claim Tag Clear Register LAR 0x00000FB0 32 wo 0x00000000 Lock Access Register LSR 0x00000FB4 3 ro 0x00000003 Lock Status Register ASR 0x00000FB8 8 ro 0x00000000 Authentication Status Register DEVID 0x00000FC8 6 ro 0x00000000 Device ID DTIR 0x00000FCC 8 ro 0x00000021 Device Type Identifier
Appendix B: Register Details Register (etb) STS Name STS Relative Address 0x0000000C Absolute Address 0xF880100C Width 4 bits Access Type ro Reset Value 0x00000000 Description Status Register Register STS Details Field Name Bits Type Reset Value Description FtEmpty 3 ro 0x0 Formatter pipeline empty. All data stored to RAM. AcqComp 2 ro 0x0 Acquisition complete.
Appendix B: Register Details Register RRD Details Field Name Bits 31:0 Type ro Reset Value 0x0 Description Data read from the ETB Trace RAM. Register (etb) RRP Name RRP Relative Address 0x00000014 Absolute Address 0xF8801014 Width 10 bits Access Type rw Reset Value 0x00000000 Description RAM Read Pointer Register Register RRP Details Field Name Bits 9:0 Type rw Reset Value 0x0 Description Sets the read pointer used to read entries from the Trace RAM over the APB interface.
Appendix B: Relative Address 0x0000001C Absolute Address 0xF880101C Width 10 bits Access Type rw Reset Value 0x00000000 Description Trigger Counter Register Register Details Register TRG Details Field Name Bits 9:0 Type rw Reset Value 0x0 Description The counter is used as follows: - Trace after The counter is set to a large value, slightly less than the number of entries in the RAM. - Trace before The counter is set to a small value.
Appendix B: Register Details Register CTL Details Field Name TraceCaptEn Bits 0 Type rw Reset Value 0x0 Description ETB Trace Capture Enable. 1 = enable trace capture 0 = disable trace capture. This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all data is stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes HIGH.
Appendix B: Relative Address 0x00000300 Absolute Address 0xF8801300 Width 2 bits Access Type ro Reset Value 0x00000002 Description Formatter and Flush Status Register Register Details Register FFSR Details Field Name Bits Type Reset Value Description FtStopped 1 ro 0x1 Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and ATREADYS goes HIGH.
Appendix B: Field Name Bits Type Reset Value Register Details Description TrigIn 8 rw 0x0 Indicate a trigger on TRIGIN being asserted. reserved 7 ro 0x0 Reserved FOnMan 6 rw 0x0 Manually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when the flush has been serviced. This bit is clear on reset. FOnTrig 5 rw 0x0 Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs.
Appendix B: Register Details Register (etb) ITTRFLINACK Name ITTRFLINACK Relative Address 0x00000EE4 Absolute Address 0xF8801EE4 Width 2 bits Access Type wo Reset Value 0x00000000 Description Integration Test Trigger In and Flush In Acknowledge Register Register ITTRFLINACK Details Field Name Bits Type Reset Value Description FLUSHINACK 1 wo 0x0 Set the value of FLUSHINACK TRIGINACK 0 wo 0x0 Set the value of TRIGINACK Register (etb) ITTRFLIN Name ITTRFLIN Relative Address 0
Appendix B: Reset Value 0x00000000 Description Integration Test ATB Data Register Register Details Register ITATBDATA0 Details Field Name Bits Type Reset Value Description ATDATA31 4 ro 0x0 Read the value of ATDATA[31] ATDATA23 3 ro 0x0 Read the value of ATDATA[23] ATDATA15 2 ro 0x0 Read the value of ATDATA[15] ATDATA7 1 ro 0x0 Read the value of ATDATA[7] ATDATA0 0 ro 0x0 Read the value of ATDATA[0] Register (etb) ITATBCTR2 Name ITATBCTR2 Relative Address 0x00000EF0 A
Appendix B: Register Details Register ITATBCTR1 Details Field Name ATID Bits 6:0 Type ro Reset Value 0x0 Description Read the value of ATIDS Register (etb) ITATBCTR0 Name ITATBCTR0 Relative Address 0x00000EF8 Absolute Address 0xF8801EF8 Width 10 bits Access Type ro Reset Value 0x00000000 Description Integration Test ATB Control Register 0 Register ITATBCTR0 Details Field Name Bits Type Reset Value Description ATBYTES 9:8 ro 0x0 Read the value of ATBYTES reserved 7:2 ro 0x0
Appendix B: Register Details Register (etb) CTSR Name CTSR Relative Address 0x00000FA0 Absolute Address 0xF8801FA0 Width 4 bits Access Type rw Reset Value 0x0000000F Description Claim Tag Set Register Register CTSR Details Field Name Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Appendix B: Register Details Register (etb) LAR Name LAR Relative Address 0x00000FB0 Absolute Address 0xF8801FB0 Width 32 bits Access Type wo Reset Value 0x00000000 Description Lock Access Register Register LAR Details Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), ETB is locked, i.e., writes to all other registers using lower 2GB addresses are ignored.
Appendix B: Register Details Register LSR Details Field Name Bits Type Reset Value Description 8BIT 2 ro 0x0 Set to 0 since ETB implements a 32-bit lock access register STATUS 1 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether ETB is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0.
Appendix B: Access Type ro Reset Value 0x00000000 Description Device ID Register Details Register DEVID Details Field Name Bits Type Reset Value Description SyncATCLK 5 ro 0x0 ETB RAM is synchronous to ATCLK InputMux 4:0 ro 0x0 no input multiplexing Register (etb) DTIR Name DTIR Relative Address 0x00000FCC Absolute Address 0xF8801FCC Width 8 bits Access Type ro Reset Value 0x00000021 Description Device Type Identifier Register Register DTIR Details Field Name Bits 7:0
Appendix B: Register Details Register PERIPHID4 Details Field Name Bits Type Reset Value Description 4KB_count 7:4 ro 0x0 4KB Count, set to 0 JEP106ID 3:0 ro 0x4 JEP106 continuation code Register (etb) PERIPHID5 Name PERIPHID5 Relative Address 0x00000FD4 Absolute Address 0xF8801FD4 Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID5 Register PERIPHID5 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (etb) PERIPHID
Appendix B: Relative Address 0x00000FDC Absolute Address 0xF8801FDC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID7 Register Details Register PERIPHID7 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (etb) PERIPHID0 Name PERIPHID0 Relative Address 0x00000FE0 Absolute Address 0xF8801FE0 Width 8 bits Access Type ro Reset Value 0x00000007 Description Peripheral ID0 Register PERIPHID0 Details Field Name Bits 7:0 T
Appendix B: Register Details Register PERIPHID1 Details Field Name Bits Type Reset Value Description JEP106ID 7:4 ro 0xB JEP106 Identity Code [3:0] PartNumber1 3:0 ro 0x9 PartNumber1 Register (etb) PERIPHID2 Name PERIPHID2 Relative Address 0x00000FE8 Absolute Address 0xF8801FE8 Width 8 bits Access Type ro Reset Value 0x0000003B Description Peripheral ID2 Register PERIPHID2 Details Field Name Bits Type Reset Value Description RevNum 7:4 ro 0x3 Revision number of Periph
Appendix B: Register Details Register (etb) COMPID0 Name COMPID0 Relative Address 0x00000FF0 Absolute Address 0xF8801FF0 Width 8 bits Access Type ro Reset Value 0x0000000D Description Component ID0 Register COMPID0 Details Field Name Bits 7:0 Type ro Reset Value 0xD Description Preamble Register (etb) COMPID1 Name COMPID1 Relative Address 0x00000FF4 Absolute Address 0xF8801FF4 Width 8 bits Access Type ro Reset Value 0x00000090 Description Component ID1 Register COMPID1 Det
Appendix B: Register Details Register COMPID2 Details Field Name Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (etb) COMPID3 Name COMPID3 Relative Address 0x00000FFC Absolute Address 0xF8801FFC Width 8 bits Access Type ro Reset Value 0x000000B1 Description Component ID3 Register COMPID3 Details Field Name Bits 7:0 Type ro Reset Value 0xB1 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 Description Preamble www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description FTMITATBCTR2 0x00000EF0 2 ro 0x00000001 ATB Control Integration Test Register 2 FTMITATBCTR1 0x00000EF4 7 rw 0x00000000 ATB Control Integration Test Register 1 FTMITATBCTR0 0x00000EF8 10 wo 0x00000000 ATB Control Integration Test Register 0 FTMITCR 0x00000F00 1 rw 0x00000000 FTM Test Control Register CLAIMTAGSET 0x00000FA0 8 rw 0x000000FF Claim Tag Set Register CLAIMTAGCLR 0x00000FA4
Appendix B: Reset Value 0x00000000 Description FTM Global Control Register Register Details Register FTMGLBCTRL Details Field Name FTMENABLE Bits 0 Type rw Reset Value 0x0 Description Enable FTM Register (ftm) FTMSTATUS Name FTMSTATUS Relative Address 0x00000004 Absolute Address 0xF880B004 Width 8 bits Access Type ro Reset Value 0x00000082 Description FTM Status Register Register FTMSTATUS Details Field Name Bits Type Reset Value Description IDLE 7 ro 0x1 FTM IDLE Status S
Appendix B: Description Register Details FTM Configuration Register FTMCONTROL Details Field Name Bits Type Reset Value Description CYCEN 2 rw 0x0 Enable Cycle Count packets TRACEN 1 rw 0x0 Enable Trace packets PROG 0 rw 0x0 Not used Register (ftm) FTMP2FDBG0 Name FTMP2FDBG0 Relative Address 0x0000000C Absolute Address 0xF880B00C Width 8 bits Access Type rw Reset Value 0x00000000 Description FPGA Debug Register P2F0 Register FTMP2FDBG0 Details Field Name PSS2FPGA Bits
Appendix B: Register Details Register FTMP2FDBG1 Details Field Name PSS2FPGA Bits 7:0 Type rw Reset Value 0x0 Description Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.
Appendix B: Register Details Register FTMP2FDBG3 Details Field Name PSS2FPGA Bits 7:0 Type rw Reset Value 0x0 Description Signals presented to the fabric. These signals do not affect the FTM, they are provided for user specific debug. To modify the contents of this register, the SPIDEN pin must be asserted.
Appendix B: Register Details Register (ftm) FTMF2PDBG2 Name FTMF2PDBG2 Relative Address 0x00000024 Absolute Address 0xF880B024 Width 8 bits Access Type ro Reset Value 0x00000000 Description FPGA Debug Register F2P2 Register FTMF2PDBG2 Details Field Name FPGA2PSS Bits 7:0 Type ro Reset Value 0x0 Description Signals that are presented to the PSS from the Fabric.
Appendix B: Description Register Details AXI Cycle Count clock pre-scaler Register CYCOUNTPRE Details Field Name Bits PRESCALE 3:0 Type rw Reset Value 0x0 Description The incoming clock is divided by 2^ PRESCALE.
Appendix B: Register Details Register FTMSYNCCOUT Details Field Name SYNCCOUT Bits 11:0 Type ro Reset Value 0x0 Description Current value of the Synchronization packet counter. The initial value is zero. The counter value increments every time a packet is issued by the FTM. When the counter reaches SYNCCOUNTTERM, a Synchronization packet is emitted.
Appendix B: Register Details Register FTMITTRIGOUTACK Details Field Name TRIGACK Bits 3:0 Type ro Reset Value 0x0 Description Read the current value of the FTMTrigOutAck[3:0] inputs Register (ftm) FTMITTRIGGER Name FTMITTRIGGER Relative Address 0x00000ED4 Absolute Address 0xF880BED4 Width 4 bits Access Type wo Reset Value 0x00000000 Description Trigger Output Integration Test Register Register FTMITTRIGGER Details Field Name TRIGGER Bits 3:0 Type wo Reset Value 0x0 Description When
Appendix B: Relative Address 0x00000EDC Absolute Address 0xF880BEDC Width 32 bits Access Type rw Reset Value 0x00000001 Description Cycle Counter Test Register Register Details Register FTMITCYCCOUNT Details Field Name FTMCYCCOUNT Bits 31:0 Type rw Reset Value 0x1 Description Read/write the value of the cycle counter Register (ftm) FTMITATBDATA0 Name FTMITATBDATA0 Relative Address 0x00000EEC Absolute Address 0xF880BEEC Width 5 bits Access Type wo Reset Value 0x00000000 Descrip
Appendix B: Absolute Address 0xF880BEF0 Width 2 bits Access Type ro Reset Value 0x00000001 Description ATB Control Integration Test Register 2 Register Details Register FTMITATBCTR2 Details Field Name Bits Type Reset Value Description AFVALID 1 ro 0x0 Read the current value of the AFVALIDM input ATREADY 0 ro 0x1 Read the current value of the ATREADYM input Register (ftm) FTMITATBCTR1 Name FTMITATBCTR1 Relative Address 0x00000EF4 Absolute Address 0xF880BEF4 Width 7 bits Acc
Appendix B: Register Details Register FTMITATBCTR0 Details Field Name Bits Type Reset Value Description ATBYTES 9:8 wo 0x0 When ITEN is 1, this value determines the ATBYTESM[1:0] output reserved 7:2 wo 0x0 Reserved AFREADY 1 wo 0x0 When ITEN is 1, this value determines the AFREADY output ATVALID 0 wo 0x0 When ITEN is 1, this value determines the ATVALID output Register (ftm) FTMITCR Name FTMITCR Relative Address 0x00000F00 Absolute Address 0xF880BF00 Width 1 bits Access Ty
Appendix B: Register Details Register CLAIMTAGSET Details Field Name Bits CLAIMTAGSETVAL 7:0 Type rw Reset Value 0xFF Description Read: 1 = Claim tag implemented, 0 = not implemented Write: 1 = Set claim tag bit, 0 = no effect Register (ftm) CLAIMTAGCLR Name CLAIMTAGCLR Relative Address 0x00000FA4 Absolute Address 0xF880BFA4 Width 8 bits Access Type rw Reset Value 0x00000000 Description Claim Tag Clear Register Register CLAIMTAGCLR Details Field Name Bits CLAIMTAGCLRVAL 7:0 Type r
Appendix B: Register Details Register (ftm) LOCK_STATUS Name LOCK_STATUS Relative Address 0x00000FB4 Absolute Address 0xF880BFB4 Width 3 bits Access Type ro Reset Value 0x00000003 Description Lock Status Register Register LOCK_STATUS Details Field Name Bits Type Reset Value Description 8BITACCESS 2 ro 0x0 8-bit lock access is not used LOCKSTATUS 1 ro 0x1 1:Access Locked, 0:Access OK LOCKIMP 0 ro 0x1 1:Lock exists if PADDRDBG31 is low, else 0 Register (ftm) FTMAUTHSTATUS N
Appendix B: Absolute Address 0xF880BFC8 Width 1 bits Access Type ro Reset Value 0x00000000 Description Device Configuration Register Register Details Register FTMDEVID Details Field Name reserved Bits 0 Type ro Reset Value 0x0 Description Reserved Register (ftm) FTMDEV_TYPE Name FTMDEV_TYPE Relative Address 0x00000FCC Absolute Address 0xF880BFCC Width 8 bits Access Type ro Reset Value 0x00000033 Description Device Type Identification Register Register FTMDEV_TYPE Details Field
Appendix B: Register Details Register FTMPERIPHID4 Details Field Name Bits Type Reset Value Description 4KBCount 7:4 ro 0x0 4KB Count JEP106 3:0 ro 0x0 JEP106 Continuation Code Register (ftm) FTMPERIPHID5 Name FTMPERIPHID5 Relative Address 0x00000FD4 Absolute Address 0xF880BFD4 Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID5 Register FTMPERIPHID5 Details Field Name reserved Bits 7:0 Type ro Reset Value 0x0 Description Reserved Register (ftm)
Appendix B: Relative Address 0x00000FDC Absolute Address 0xF880BFDC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID7 Register Details Register FTMPERIPHID7 Details Field Name Bits reserved 7:0 Type ro Reset Value 0x0 Description Reserved Register (ftm) FTMPERIPHID0 Name FTMPERIPHID0 Relative Address 0x00000FE0 Absolute Address 0xF880BFE0 Width 8 bits Access Type ro Reset Value 0x00000001 Description Peripheral ID0 Register FTMPERIPHID0 Details
Appendix B: Register Details Register FTMPERIPHID1 Details Field Name Bits Type Reset Value Description JEP106 7:4 ro 0x9 JEP106 identity bits [3:0] PARTNUMUPPER 3:0 ro 0x0 Part Number Upper [11:8] Register (ftm) FTMPERIPHID2 Name FTMPERIPHID2 Relative Address 0x00000FE8 Absolute Address 0xF880BFE8 Width 8 bits Access Type ro Reset Value 0x0000000C Description Peripheral ID2 Register FTMPERIPHID2 Details Field Name Bits Type Reset Value Description REVISION 7:4 ro 0x0
Appendix B: Register Details Register (ftm) FTMCOMPONID0 Name FTMCOMPONID0 Relative Address 0x00000FF0 Absolute Address 0xF880BFF0 Width 8 bits Access Type ro Reset Value 0x0000000D Description Component ID0 Register FTMCOMPONID0 Details Field Name Preamble Bits 7:0 Type ro Reset Value 0xD Description Preamble Register (ftm) FTMCOMPONID1 Name FTMCOMPONID1 Relative Address 0x00000FF4 Absolute Address 0xF880BFF4 Width 8 bits Access Type ro Reset Value 0x00000090 Description C
Appendix B: Description Register Details Component ID2 Register FTMCOMPONID2 Details Field Name Preamble Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (ftm) FTMCOMPONID3 Name FTMCOMPONID3 Relative Address 0x00000FFC Absolute Address 0xF880BFFC Width 8 bits Access Type ro Reset Value 0x000000B1 Description Component ID3 Register FTMCOMPONID3 Details Field Name Preamble Bits 7:0 Type ro Reset Value 0xB1 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description PERIPHID3 0x00000FEC 8 ro 0x00000000 Peripheral ID3 COMPID0 0x00000FF0 8 ro 0x0000000D Component ID0 COMPID1 0x00000FF4 8 ro 0x00000090 Component ID1 COMPID2 0x00000FF8 8 ro 0x00000005 Component ID2 COMPID3 0x00000FFC 8 ro 0x000000B1 Component ID3 Register (funnel) Control Name Control Relative Address 0x00000000 Absolute Address 0xF8804000 Width 12 bits Access Type rw Reset
Appendix B: Field Name Bits Type Reset Value Register Details Description EnableSlave3 3 rw 0x0 Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. EnableSlave2 2 rw 0x0 Setting this bit enables this slave port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. EnableSlave1 1 rw 0x0 Setting this bit enables this slave port.
Appendix B: Absolute Address 0xF8804EEC Width 5 bits Access Type rw Reset Value 0x00000000 Description Integration Test ATB Data 0 Register Register Details Register ITATBDATA0 Details Field Name Bits Type Reset Value Description ATDATA31 4 rw 0x0 Read the value of ATDATAS[31], set the value of ATDATAM[31] ATDATA23 3 rw 0x0 Read the value of ATDATAS[23], set the value of ATDATAM[23] ATDATA15 2 rw 0x0 Read the value of ATDATAS[15], set the value of ATDATAM[15] ATDATA7 1 rw
Appendix B: Register Details Register (funnel) ITATBCTR1 Name ITATBCTR1 Relative Address 0x00000EF4 Absolute Address 0xF8804EF4 Width 7 bits Access Type rw Reset Value 0x00000000 Description Integration Test ATB Control 1 Register Register ITATBCTR1 Details Field Name ATID Bits 6:0 Type rw Reset Value 0x0 Description Read the value of ATIDS. Set the value of ATIDM.
Appendix B: Absolute Address 0xF8804F00 Width 1 bits Access Type rw Reset Value 0x00000000 Description Integration Mode Control Register Register Details Register IMCR Details Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers.
Appendix B: Reset Value 0x00000000 Description Claim Tag Clear Register Register Details Register CTCR Details Field Name Bits 3:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag.
Appendix B: Register Details Register (funnel) LSR Name LSR Relative Address 0x00000FB4 Absolute Address 0xF8804FB4 Width 3 bits Access Type ro Reset Value 0x00000003 Description Lock Status Register Register LSR Details Field Name Bits Type Reset Value Description 8BIT 2 ro 0x0 Set to 0 since Funnel implements a 32-bit lock access register STATUS 1 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register
Appendix B: Register Details Register ASR Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description Indicates functionality not implemented Register (funnel) DEVID Name DEVID Relative Address 0x00000FC8 Absolute Address 0xF8804FC8 Width 8 bits Access Type ro Reset Value 0x00000028 Description Device ID Register DEVID Details Field Name Bits Type Reset Value Description StaticPrio 7:4 ro 0x2 CSTF implements a static priority scheme NumInPorts 3:0 ro 0x8 Number of inpu
Appendix B: Relative Address 0x00000FD0 Absolute Address 0xF8804FD0 Width 8 bits Access Type ro Reset Value 0x00000004 Description Peripheral ID4 Register Details Register PERIPHID4 Details Field Name Bits Type Reset Value Description 4KB_count 7:4 ro 0x0 4KB Count, set to 0 JEP106ID 3:0 ro 0x4 JEP106 continuation code Register (funnel) PERIPHID5 Name PERIPHID5 Relative Address 0x00000FD4 Absolute Address 0xF8804FD4 Width 8 bits Access Type ro Reset Value 0x00000000
Appendix B: Register Details Register PERIPHID6 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (funnel) PERIPHID7 Name PERIPHID7 Relative Address 0x00000FDC Absolute Address 0xF8804FDC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID7 Register PERIPHID7 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (funnel) PERIPHID0 Name PERIPHID0 Relative Address 0x00000FE0 Absolute Address 0xF
Appendix B: Absolute Address 0xF8804FE4 Width 8 bits Access Type ro Reset Value 0x000000B9 Description Peripheral ID1 Register Details Register PERIPHID1 Details Field Name Bits Type Reset Value Description JEP106ID 7:4 ro 0xB JEP106 Identity Code [3:0] PartNumber1 3:0 ro 0x9 PartNumber1 Register (funnel) PERIPHID2 Name PERIPHID2 Relative Address 0x00000FE8 Absolute Address 0xF8804FE8 Width 8 bits Access Type ro Reset Value 0x0000001B Description Peripheral ID2 Regis
Appendix B: Register Details Register PERIPHID3 Details Field Name Bits Type Reset Value Description RevAnd 7:4 ro 0x0 RevAnd, at top level CustMod 3:0 ro 0x0 Customer Modified Register (funnel) COMPID0 Name COMPID0 Relative Address 0x00000FF0 Absolute Address 0xF8804FF0 Width 8 bits Access Type ro Reset Value 0x0000000D Description Component ID0 Register COMPID0 Details Field Name Bits 7:0 Type ro Reset Value 0xD Description Preamble Register (funnel) COMPID1 Name COMPI
Appendix B: Relative Address 0x00000FF8 Absolute Address 0xF8804FF8 Width 8 bits Access Type ro Reset Value 0x00000005 Description Component ID2 Register Details Register COMPID2 Details Field Name Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (funnel) COMPID3 Name COMPID3 Relative Address 0x00000FFC Absolute Address 0xF8804FFC Width 8 bits Access Type ro Reset Value 0x000000B1 Description Component ID3 Register COMPID3 Details Field Name Bits 7:0 Type ro
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description StimPort23 0x0000005C 32 rw 0x00000000 Stimulus Port Register 23 StimPort24 0x00000060 32 rw 0x00000000 Stimulus Port Register 24 StimPort25 0x00000064 32 rw 0x00000000 Stimulus Port Register 25 StimPort26 0x00000068 32 rw 0x00000000 Stimulus Port Register 26 StimPort27 0x0000006C 32 rw 0x00000000 Stimulus Port Register 27 StimPort28 0x00000070 32 rw 0x00000000 Stimulus Port Regis
Appendix B: Register Name Address Width Type Reset Value Register Details Description PERIPHID6 0x00000FD8 8 ro 0x00000000 Peripheral ID6 PERIPHID7 0x00000FDC 8 ro 0x00000000 Peripheral ID7 PERIPHID0 0x00000FE0 8 ro 0x00000013 Peripheral ID0 PERIPHID1 0x00000FE4 8 ro 0x000000B9 Peripheral ID1 PERIPHID2 0x00000FE8 8 ro 0x0000002B Peripheral ID2 PERIPHID3 0x00000FEC 8 ro 0x00000000 Peripheral ID3 COMPID0 0x00000FF0 8 ro 0x0000000D Component ID0 COMPID1 0x0000
Appendix B: Register Details Register StimPort00 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort01 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort02 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort03 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort04 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort05 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort06 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort07 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort08 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort09 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort10 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort11 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort12 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort13 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort14 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort15 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort16 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort17 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort18 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort19 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort20 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort21 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort22 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort23 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort24 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort25 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort26 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort27 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort28 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort29 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort30 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Register Details Register StimPort31 Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Each of the 32 stimulus ports is represented by a virtual address, creating 32 stimulus registers. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set and ITM is enabled. Reading from any of the stimulus ports returns the FIFO status (notFull(1) / Full(0)) only if the ITM is enabled.
Appendix B: Absolute Address 0xF8805E20 Width 32 bits Access Type rw Reset Value 0x00000000 Description Trace Trigger Register Register Details Register TTR Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Bit mask to enable trigger generation, TRIGOUT, on selected writes to the Stimulus Registers.
Appendix B: Register Details Register (itm) SCR Name SCR Relative Address 0x00000E90 Absolute Address 0xF8805E90 Width 12 bits Access Type rw Reset Value 0x00000400 Description Synchronization Control Register Register SCR Details Field Name SyncCount Bits 11:0 Type rw Reset Value 0x400 Description Counter value for time between synchronization markers Register (itm) ITTRIGOUTACK Name ITTRIGOUTACK Relative Address 0x00000EE4 Absolute Address 0xF8805EE4 Width 1 bits Access Type
Appendix B: Description Register Details Integration Test Trigger Out Register Register ITTRIGOUT Details Field Name ITTRIGOUT Bits 0 Type wo Reset Value 0x0 Description Set the value of TRIGOUT Register (itm) ITATBDATA0 Name ITATBDATA0 Relative Address 0x00000EEC Absolute Address 0xF8805EEC Width 2 bits Access Type wo Reset Value 0x00000000 Description Integration Test ATB Data Register 0 Register ITATBDATA0 Details Field Name Bits Type Reset Value Description ITATDATAM7 1 wo
Appendix B: Register Details Register (itm) ITATABCTR1 Name ITATABCTR1 Relative Address 0x00000EF4 Absolute Address 0xF8805EF4 Width 7 bits Access Type wo Reset Value 0x00000000 Description Integration Test ATB Control Register 1 Register ITATABCTR1 Details Field Name ITATIDM Bits 6:0 Type wo Reset Value 0x0 Description Set the value of ATIDM[6:0] Register (itm) ITATBCTR0 Name ITATBCTR0 Relative Address 0x00000EF8 Absolute Address 0xF8805EF8 Width 2 bits Access Type wo Reset V
Appendix B: Description Register Details Integration Mode Control Register Register IMCR Details Field Name Bits 0 Type rw Reset Value 0x0 Description Enable Integration Test registers.
Appendix B: Register Details Register CTCR Details Field Name Bits 7:0 Type rw Reset Value 0x0 Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed. Read: Current value of claim tag.
Appendix B: Relative Address 0x00000FB4 Absolute Address 0xF8805FB4 Width 3 bits Access Type ro Reset Value 0x00000003 Description Lock Status Register Register Details Register LSR Details Field Name Bits Type Reset Value Description 8BIT 2 ro 0x0 Set to 0 since ITM implements a 32-bit lock access register STATUS 1 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether ITM is
Appendix B: Register Details Register ASR Details Field Name Bits 7:0 Type ro Reset Value 0x88 Description Value is 0b1S001N00 where S is secure non-invasive debug state and N is non-secure, non-invasive debug.
Appendix B: Relative Address 0x00000FD0 Absolute Address 0xF8805FD0 Width 8 bits Access Type ro Reset Value 0x00000004 Description Peripheral ID4 Register Details Register PERIPHID4 Details Field Name Bits Type Reset Value Description 4KB_count 7:4 ro 0x0 4KB Count, set to 0 JEP106ID 3:0 ro 0x4 JEP106 continuation code Register (itm) PERIPHID5 Name PERIPHID5 Relative Address 0x00000FD4 Absolute Address 0xF8805FD4 Width 8 bits Access Type ro Reset Value 0x00000000 Des
Appendix B: Register Details Register PERIPHID6 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (itm) PERIPHID7 Name PERIPHID7 Relative Address 0x00000FDC Absolute Address 0xF8805FDC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID7 Register PERIPHID7 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (itm) PERIPHID0 Name PERIPHID0 Relative Address 0x00000FE0 Absolute Address 0xF8805FE
Appendix B: Absolute Address 0xF8805FE4 Width 8 bits Access Type ro Reset Value 0x000000B9 Description Peripheral ID1 Register Details Register PERIPHID1 Details Field Name Bits Type Reset Value Description JEP106ID 7:4 ro 0xB JEP106 Identity Code [3:0] PartNumber1 3:0 ro 0x9 PartNumber1 Register (itm) PERIPHID2 Name PERIPHID2 Relative Address 0x00000FE8 Absolute Address 0xF8805FE8 Width 8 bits Access Type ro Reset Value 0x0000002B Description Peripheral ID2 Register
Appendix B: Register Details Register PERIPHID3 Details Field Name Bits Type Reset Value Description RevAnd 7:4 ro 0x0 RevAnd, at top level CustMod 3:0 ro 0x0 Customer Modified Register (itm) COMPID0 Name COMPID0 Relative Address 0x00000FF0 Absolute Address 0xF8805FF0 Width 8 bits Access Type ro Reset Value 0x0000000D Description Component ID0 Register COMPID0 Details Field Name Bits 7:0 Type ro Reset Value 0xD Description Preamble Register (itm) COMPID1 Name COMPID1 Re
Appendix B: Relative Address 0x00000FF8 Absolute Address 0xF8805FF8 Width 8 bits Access Type ro Reset Value 0x00000005 Description Component ID2 Register Details Register COMPID2 Details Field Name Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (itm) COMPID3 Name COMPID3 Relative Address 0x00000FFC Absolute Address 0xF8805FFC Width 8 bits Access Type ro Reset Value 0x000000B1 Description Component ID3 Register COMPID3 Details Field Name Bits 7:0 Type ro Re
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description ITATBCTR1 0x00000EF4 7 ro x Integration Test ATB Control Register 1 ITATBCTR0 0x00000EF8 10 ro x Integration Test ATB Control Register 0 IMCR 0x00000F00 1 rw 0x00000000 Integration Mode Control Register CTSR 0x00000FA0 4 rw 0x0000000F Claim Tag Set Register CTCR 0x00000FA4 4 rw 0x00000000 Claim Tag Clear Register LAR 0x00000FB0 32 wo 0x00000000 Lock Access Register LSR 0x00000FB
Appendix B: Register Details Register SuppSize Details Field Name Bits 31:0 Type rw Reset Value 0xFFFFFFFF Description Each bit location represents a single port size that is supported on the device, that is, 32-1 in bit locations [31:0].
Appendix B: Register Details Register SuppTrigMode Details Field Name Bits Type Reset Value Description TrgRun 17 ro 0x0 Trigger Counter running. A trigger has occurred but the counter is not at zero. Triggered 16 ro 0x0 A trigger has occurred and the counter has reached zero. reserved 15:9 ro 0x0 Reserved TCount8 8 ro 0x1 8-bit wide counter register implemented. reserved 7:5 ro 0x0 Reserved Mult64k 4 ro 0x1 Multiply the Trigger Counter by 65536 supported.
Appendix B: Access Type rw Reset Value 0x00000000 Description Trigger Multiplier Register Register Details Register TrigMult Details Field Name Bits Type Reset Value Description Mult64k 4 rw 0x0 Multiply the Trigger Counter by 65536. Mult256 3 rw 0x0 Multiply the Trigger Counter by 256. Mult16 2 rw 0x0 Multiply the Trigger Counter by 16. Mult4 1 rw 0x0 Multiply the Trigger Counter by 4. Mult2 0 rw 0x0 Multiply the Trigger Counter by 2.
Appendix B: Absolute Address 0xF8803204 Width 18 bits Access Type mixed Reset Value 0x00000000 Description Current Test Patterns/Modes Register Register Details Register CurrentTest Details Field Name Bits Type Reset Value Description PContEn 17 rw 0x0 Continuous mode. PTimeEn 16 rw 0x0 Timed mode.
Appendix B: Width 3 bits Access Type ro Reset Value 0x00000006 Description Formatter and Flush Status Register Register Details Register FFSR Details Field Name Bits Type Reset Value Description TCPresent 2 ro 0x1 If this bit is set then TRACECTL is present. FtStopped 1 ro 0x1 Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and ATREADYS goes HIGH.
Appendix B: Field Name Bits Type Reset Value Register Details Description FOnMan 6 rw 0x0 Manually generate a flush of the system. Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. FOnTrig 5 rw 0x0 Generate a flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs. FOnFlIn 4 rw 0x0 Generate flush using the FLUSHIN interface. Set this bit to enable use of the FLUSHIN connection.
Appendix B: Width 8 bits Access Type ro Reset Value 0x00000000 Description EXTCTL In Port Register Details Register EXTCTLIn Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description Tied to 0 Register (tpiu) EXTCTLOut Name EXTCTLOut Relative Address 0x00000404 Absolute Address 0xF8803404 Width 8 bits Access Type rw Reset Value 0x00000000 Description EXTCTL Out Port Register EXTCTLOut Details Field Name Bits 7:0 Type rw Reset Value 0x0 Description Output not connected
Appendix B: Register Details Register ITTRFLINACK Details Field Name Bits Type Reset Value Description FLUSHINACK 1 wo 0x0 Set the value of FLUSHINACK TRIGINACK 0 wo 0x0 Set the value of TRIGINACK Register (tpiu) ITTRFLIN Name ITTRFLIN Relative Address 0x00000EE8 Absolute Address 0xF8803EE8 Width 2 bits Access Type ro Reset Value x Description Integration Test Trigger In and Flush In Register Register ITTRFLIN Details Field Name Bits Type Reset Value Description FLUSHIN
Appendix B: Field Name Bits Type Reset Value Register Details Description ATDATA7 1 ro x Read the value of ATDATAS[7] ATDATA0 0 ro x Read the value of ATDATAS[0] Register (tpiu) ITATBCTR2 Name ITATBCTR2 Relative Address 0x00000EF0 Absolute Address 0xF8803EF0 Width 2 bits Access Type wo Reset Value 0x00000000 Description Integration Test ATB Control Register 2 Register ITATBCTR2 Details Field Name Bits Type Reset Value Description AFVALID 1 wo 0x0 Set the value of AFVA
Appendix B: Relative Address 0x00000EF8 Absolute Address 0xF8803EF8 Width 10 bits Access Type ro Reset Value x Description Integration Test ATB Control Register 0 Register Details Register ITATBCTR0 Details Field Name Bits Type Reset Value Description ATBYTES 9:8 ro x Read the value of ATBYTESS reserved 7:2 ro x Reserved AFREADY 1 ro x Read the value of AFREADYS ATVALID 0 ro x Read the value of ATVALIDS Register (tpiu) IMCR Name IMCR Relative Address 0x00000F00 Abs
Appendix B: Description Register Details Claim Tag Set Register Register CTSR Details Field Name Bits 3:0 Type rw Reset Value 0xF Description The claim tag register is used for any interrogating tools to determine if the device is being programmed or has been programmed.
Appendix B: Description Register Details Lock Access Register Register LAR Details Field Name Bits 31:0 Type wo Reset Value 0x0 Description Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), TPIU is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register.
Appendix B: Register Details Register LSR Details Field Name Bits Type Reset Value Description 8BIT 2 ro 0x0 Set to 0 since TPIU implements a 32-bit lock access register STATUS 1 ro 0x1 Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether TPIU is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0.
Appendix B: Access Type ro Reset Value 0x000000A0 Description Device ID Register Details Register DEVID Details Field Name Bits Type Reset Value Description UartNRZ 11 ro 0x0 UART/NRZ not supported Manchester 10 ro 0x0 Manchester not support ClockData 9 ro 0x0 Trace clock + data is supported FifoSize 8:6 ro 0x2 FIFO size is 4 AsyncClock 5 ro 0x1 ATCLK and TRACECLKIN is asynchronous InputMux 4:0 ro 0x0 No input multiplexing Register (tpiu) DTIR Name DTIR Relative
Appendix B: Register Details Register PERIPHID4 Details Field Name Bits Type Reset Value Description 4KB_count 7:4 ro 0x0 4KB Count, set to 0 JEP106ID 3:0 ro 0x4 JEP106 continuation code Register (tpiu) PERIPHID5 Name PERIPHID5 Relative Address 0x00000FD4 Absolute Address 0xF8803FD4 Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID5 Register PERIPHID5 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (tpiu) PERIPH
Appendix B: Relative Address 0x00000FDC Absolute Address 0xF8803FDC Width 8 bits Access Type ro Reset Value 0x00000000 Description Peripheral ID7 Register Details Register PERIPHID7 Details Field Name Bits 7:0 Type ro Reset Value 0x0 Description reserved Register (tpiu) PERIPHID0 Name PERIPHID0 Relative Address 0x00000FE0 Absolute Address 0xF8803FE0 Width 8 bits Access Type ro Reset Value 0x00000012 Description Peripheral ID0 Register PERIPHID0 Details Field Name Bits 7:0
Appendix B: Register Details Register PERIPHID1 Details Field Name Bits Type Reset Value Description JEP106ID 7:4 ro 0xB JEP106 Identity Code [3:0] PartNumber1 3:0 ro 0x9 PartNumber1 Register (tpiu) PERIPHID2 Name PERIPHID2 Relative Address 0x00000FE8 Absolute Address 0xF8803FE8 Width 8 bits Access Type ro Reset Value 0x0000004B Description Peripheral ID2 Register PERIPHID2 Details Field Name Bits Type Reset Value Description RevNum 7:4 ro 0x4 Revision number of Perip
Appendix B: Register Details Register (tpiu) COMPID0 Name COMPID0 Relative Address 0x00000FF0 Absolute Address 0xF8803FF0 Width 8 bits Access Type ro Reset Value 0x0000000D Description Component ID0 Register COMPID0 Details Field Name Bits 7:0 Type ro Reset Value 0xD Description Preamble Register (tpiu) COMPID1 Name COMPID1 Relative Address 0x00000FF4 Absolute Address 0xF8803FF4 Width 8 bits Access Type ro Reset Value 0x00000090 Description Component ID1 Register COMPID1 D
Appendix B: Register Details Register COMPID2 Details Field Name Bits 7:0 Type ro Reset Value 0x5 Description Preamble Register (tpiu) COMPID3 Name COMPID3 Relative Address 0x00000FFC Absolute Address 0xF8803FFC Width 8 bits Access Type ro Reset Value 0x000000B1 Description Component ID3 Register COMPID3 Details Field Name Bits 7:0 Type ro Reset Value 0xB1 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 Description Preamble www.xilinx.
Appendix B: Register Details B.16 Device Configuration Interface (devcfg) Module Name Device Configuration Interface (devcfg) Software Name XDCFG Base Address 0xF8007000 devcfg Description Device configuraion Interface Vendor Info Register Summary Register Name CTRL Address 0x00000000 Width Type 32 mixed Reset Value 0x0C006000 Description Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
Appendix B: Register Name INT_STS Address 0x0000000C Width Type 32 mixed Reset Value 0x00000000 Register Details Description Interrupt Status Register : This register contains interrupt status flags. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true.
Appendix B: Register Name DMA_DST_ADDR Address 0x0000001C Width Type 32 rw Reset Value 0x00000000 Register Details Description DMA Destination address Register: This register contains the destination address for DMA transfer. A DMA command consists of source address, destination address, source transfer length, and destination transfer length. It is important that the parameters are programmed in the exact sequence as described.
Appendix B: Register Name UNLOCK Address 0x00000034 Width Type 32 rw Reset Value 0x00000000 Register Details Description Unlock Register: This register is used to protect the DEVCI configuration registers from ROM code corruption. The boot ROM will unlock the DEVCI by writing 0x757BDF0D to this register. Writing anything other than the unlock word to this register will cause an illegal access state and make the DEVCI inaccessible until a system reset occurs.
Appendix B: Register Name Address Width Type Reset Value Register Details Description XADCIF_MSTS 0x0000010C 32 ro 0x00000500 XADC Interface miscellaneous Status Register : This register contains miscellaneous status of the XADC Interface XADCIF_CMDFIFO 0x00000110 32 wo 0x00000000 XADC Interface Command FIFO Register : This address is the entry point to the command FIFO.
Appendix B: Field Name PCFG_POR_CNT_4K Bits 29 Type rw Reset Value 0x0 Register Details Description This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer reserved 28 rw 0x0 Reserved PCAP_PR 27 rw 0x1 After the initial configuration of the PL, a partial reconfiguration can be performed using either the ICAP or PCAP interface. These interfaces are mutually exclusive and cannot be used simultaneously.
Appendix B: Field Name Bits Type Reset Value reserved 13 rw 0x1 PCFG_AES_FUSE 12 rw 0x0 Register Details Description Reserved - always write with 1 (Lockable, see 0x004, bit 4) This bit is used to select the AES key source 0 - BBRAM key 1 - eFuse key User access to this bit is restricted. The boot ROM will make the key selection and lock this bit during the initial boot sequence. This bit is only cleared by PS_POR_B reset.
Appendix B: Field Name Bits SPIDEN 5 Type rw Reset Value 0x0 Register Details Description (Lockable, see 0x004, bit 0) Secure Invasive Debug Enable 0 - Disable 1 - Enable NIDEN 4 rw 0x0 (Lockable, see 0x004, bit 0) Non-Invasive Debug Enable 0 - Disable 1 - Enable DBGEN 3 rw 0x0 (Lockable, see 0x004, bit 0) Invasive Debug Enable 0 - Disable 1 - Enable DAP_EN 2:0 rw 0x0 (Lockable, see 0x004, bit 0) These bits will enable the ARM DAP.
Appendix B: Field Name AES_EN_LOCK Bits 3 Type rwso Reset Value 0x0 (AES_EN) Register Details Description This bit locks the PCFG_AES_EN bits (CTRL[11:9]). 0 - Open 1 - Locked User access to this bit is restricted, the boot ROM will always set this bit prior to handing control over to user code. This bit is only cleared by a PS_POR_B reset. SEU_LOCK 2 rwso 0x0 (SEU) This bit locks the SEU_EN bit (CTRL[8]). 0 - Open 1 - Locked This bit is only cleared by a PS_POR_B reset.
Appendix B: Register Details Register CFG Details Field Name Bits Type Reset Value Description reserved 31:12 rw 0x0 Reserved RFIFO_TH 11:10 rw 0x1 These two bits define Rx FIFO level that sets interrupt flag 00 - One fourth full for read 01 - Half full for read 10 - Three fourth full for read 11 - Full for read(User could use this signal to trigger interrupt when read FIFO overflow) WFIFO_TH 9:8 rw 0x1 These two bits define Tx FIFO level that sets interrupt flag 00 - One fourth empty f
Appendix B: Access Type mixed Reset Value 0x00000000 Description Register Details Interrupt Status Register : This register contains interrupt status flags. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x010 is set.
Appendix B: Field Name Bits RD_FIFO_LVL_INT Type Reset Value Register Details Description 16 wtc 0x0 Rx FIFO level >= threshold, see reg 0x008 15 wtc 0x0 Illegal DMA command 14 wtc 0x0 DMA command queue overflows 13 wtc 0x0 (IXR_RD_FIFO_LVL) DMA_CMD_ERR_INT (IXR_DMA_CMD_ERR ) DMA_Q_OV_INT (IXR_DMA_Q_OV) DMA_DONE_INT This bit is used to indicate a DMA command (IXR_DMA_DONE) is done.
Appendix B: Width 32 bits Access Type rw Reset Value 0xFFFFFFFF Description Interrupt Mask Register: This register contains interrupt mask information. Register Details Set a bit to 1 to mask the interrupt generation from the corresponding interrupting source in Interrupt Status Register 0x00C.
Appendix B: Field Name Bits Type Reset Value Register Details Description 14 rw 0x1 Interrupt mask for DMA command FIFO overflows 13 rw 0x1 Interrupt mask for DMA command done interrupt 12 rw 0x1 Interrupt mask for DMA and PCAP done interrupt 11 rw 0x1 Interrupt mask Inconsistent xfer length error interrupt reserved 10:7 rw 0xF Reserved M_PCFG_HMAC_ERR _INT 6 rw 0x1 Interrupt mask for HMAC error 5 rw 0x1 Interrupt mask for PCFG_SEU_ERR interrupt 4 rw 0x1 Interrupt mas
Appendix B: Reset Value 0x40000820 Description Status Register: This register contains miscellaneous status.
Appendix B: Field Name Bits PCFG_INIT 4 Type ro Reset Value 0x0 Register Details Description PL INIT signal, indicates when housecleaning is done and the PL is ready to receive PCAP data. Positive and negative edges of the signal generate maskable interrupts in 0x00C. EFUSE_BBRAM_KEY_ DISABLE 3 ro 0x0 When this eFuse is blown, the BBRAM AES key is disabled. (EFUSE_SW_RESERVE ) EFUSE_SEC_EN If the device is booted securely, the eFuse key must be used.
Appendix B: Register Details Register (devcfg) DMA_DST_ADDR Name DMA_DST_ADDR Software Name DMA_DEST_ADDR Relative Address 0x0000001C Absolute Address 0xF800701C Width 32 bits Access Type rw Reset Value 0x00000000 Description DMA Destination address Register: This register contains the destination address for DMA transfer. A DMA command consists of source address, destination address, source transfer length, and destination transfer length.
Appendix B: Register Details Register DMA_SRC_LEN Details Field Name Bits Type Reset Value Description reserved 31:27 rw 0x0 Reserved LEN 26:0 rw 0x0 Up to 512MB data (DMA_LEN) Register (devcfg) DMA_DEST_LEN Name DMA_DEST_LEN Relative Address 0x00000024 Absolute Address 0xF8007024 Width 32 bits Access Type rw Reset Value 0x00000000 Description DMA Destination transfer Length Register: This register contains the DMA destination transfer length in unit of 4-byte word.
Appendix B: Description Register Details MULTI Boot Addr Pointer Register: This register defines multi-boot address pointer. This register is power on reset only used to remember multi-boot address pointer set by previous boot.
Appendix B: Register Details Register MCTRL Details Field Name PS_VERSION Bits 31:28 Type ro Reset Value x Description Version ID for silicon 0x0 = 1.0 Silicon 0x1 = 2.0 Silicon 0x2 = 3.0 Silicon 0x3 = 3.1 Silicon reserved 27 ro 0x0 Reserved. Do not modify. reserved 26 ro 0x0 Reserved. Do not modify. reserved 25 ro 0x0 Reserved. Do not modify. reserved 24 ro 0x0 Reserved. Do not modify.
Appendix B: Register Details Register XADCIF_CFG Details Field Name Bits Type Reset Value Description ENABLE 31 rw 0x0 Enable PS access of the XADC, if set reserved 30:24 rw 0x0 Reserved CFIFOTH 23:20 rw 0x0 Command FIFO level threshold. Interrupt status flag is set if the FIFO level is less than or equal to the threshold DFIFOTH 19:16 rw 0x0 Data FIFO level threshold.
Appendix B: Description Register Details XADC Interface Interrupt Status Register : This register contains the interrupt status flags of the XADC interface block. All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Note that individual status bits will be set if the corresponding condition is satisfied regardless of whether the interrupt mask bit in 0x108 is set.
Appendix B: Field Name Bits Type Reset Value Register Details Description M_DFIFO_GTH 8 rw 0x1 Interrupt mask Data FIFO level greater than threshold interrupt. M_OT 7 rw 0x1 Interrupt mask for over temperature alarm interrupt M_ALM 6:0 rw 0x7F Interrupt mask for alarm signals from XADC.
Appendix B: Register Details Absolute Address 0xF8007110 Width 32 bits Access Type wo Reset Value 0x00000000 Description XADC Interface Command FIFO Register : This address is the entry point to the command FIFO. Commands get push into the FIFO when there is a write to this address Register XADCIF_CMDFIFO Details Field Name CMD Bits 31:0 Type wo Reset Value 0x0 Description 32-bit command.
Appendix B: Register Details Register XADCIF_MCTL Details Field Name Bits Type Reset Value Description reserved 31:5 rw 0x0 Reserved RESET 4 rw 0x1 This bit will reset the communication channel between the PS and XADC. If set, the PS-XADC communication channel will remain in reset until a 0 is written to this bit. reserved 3:1 rw 0x0 Reserved reserved 0 rw 0x0 Reserved - always write with 0 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description CPC2 0x00000114 32 mixed 0x00000000 Channel PC for DMA Channel 2 CSR3 0x00000118 32 mixed 0x00000000 Channel Status DMA Channel 3 CPC3 0x0000011C 32 mixed 0x00000000 Channel PC for DMA Channel 3 CSR4 0x00000120 32 mixed 0x00000000 Channel Status DMA Channel 4 CPC4 0x00000124 32 mixed 0x00000000 Channel PC for DMA Channel 4 CSR5 0x00000128 32 mixed 0x00000000 Channel Status DMA Cha
Appendix B: Register Name Address Width Type Reset Value Register Details Description SAR3 0x00000460 32 mixed 0x00000000 Source Address DMA Channel 3 DAR3 0x00000464 32 mixed 0x00000000 Destination Addr DMA Channel 3 CCR3 0x00000468 32 mixed dmac0_ns: 0x00000000 Channel Control DMA Channel 3 dmac0_s: 0x00800200 LC0_3 0x0000046C 32 mixed 0x00000000 Loop Counter 0 DMA Channel 3 LC1_3 0x00000470 32 mixed 0x00000000 Loop Counter 1 DMA Channel 3 SAR4 0x00000480 32 mixed
Appendix B: Register Name CCR7 Address 0x000004E8 Width Type 32 mixed Reset Value dmac0_ns: 0x00000000 Register Details Description Channel Control DMA Channel 7 dmac0_s: 0x00800200 LC0_7 0x000004EC 32 mixed 0x00000000 Loop Counter 0 DMA Channel 7 LC1_7 0x000004F0 32 mixed 0x00000000 Loop Counter 1 DMA Channel 7 DBGSTATUS 0x00000D00 32 mixed 0x00000000 DMA Manager Execution Status DBGCMD 0x00000D04 32 mixed 0x00000000 DMA Manager Instr.
Appendix B: Register Name Address Width Type Reset Value Register Details Description periph_id_3 0x00000FEC 32 mixed 0x00000000 Peripheral Idenfication register 3 pcell_id_0 0x00000FF0 32 mixed dmac0_ns: 0x00000000 Compontent Idenfication register 0 dmac0_s: 0x0000000D pcell_id_1 0x00000FF4 32 mixed dmac0_ns: 0x00000000 Compontent Idenfication register 1 dmac0_s: 0x000000F0 pcell_id_2 0x00000FF8 32 mixed dmac0_ns: 0x00000000 Compontent Idenfication register 2 dmac0_s: 0x0000
Appendix B: Field Name Wakeup_event Bits 8:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA manager executes a DMAWFE instruction, it is waiting for one of the following events to occur from any of the DMA channel treads: 0 0000: event[0] 0 0001: event[1] ...
Appendix B: Absolute Address Register Details dmac0_ns: 0xF8004020 dmac0_s: 0xF8003020 Width 32 bits Access Type mixed Reset Value 0x00000000 Description DMASEV Instruction Response Control Register INTEN Details Field Name event_irq_select Bits 31:0 Type Reset Value srw,ns 0x0 sraz,n snsrw Description Control the respond of a DMA channel thread when it executes a DMASEV instruction.
Appendix B: Register Details Register INT_EVENT_RIS Details Field Name DMASEV_active Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Raw status of the event or interrupt state. There are sixteen possible event settings [15:0] and eight possible interrupts [7:0]: 0: Inactive 1: Active Note: When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register controls whether the DMAC: signals an interrupt using the appropriate irq sends the event to all of the threads.
Appendix B: Width 32 bits Access Type mixed Reset Value 0x00000000 Description Interrupt Clear Register Details Register INTCLR Details Field Name irq_clr Bits 31:0 Type swo,n ssraz, nsns wo Reset Value 0x0 Description Clear interrupt(s) for DMA channel [7:0]: 0: no affect 1: clear the interrupt Reserved Register (dmac) FSRD Name FSRD Software Name FSM Relative Address 0x00000030 Absolute Address dmac0_ns: 0xF8004030 dmac0_s: 0xF8003030 Width 32 bits Access Type mixed Reset Value
Appendix B: Width 32 bits Access Type mixed Reset Value 0x00000000 Description Fault Status DMA Channel Register Details Register FSRC Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined fault_status 7:0 sro,ns sraz,n snsro 0x0 Each bit provides the fault status of the corresponding DMA channel, Bits [7:0]: 0: No fault present 1: Fault or Fault completing state Register (dmac) FTRD Name FTRD Software Name FTM Relative Address 0x00
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 15:6 rud 0x0 read undefined mgr_evnt_err 5 sro,ns sraz,n snsro 0x0 Indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate security permissions: 0: the DMA manager has appropriate security to execute DMAWFE or DMASEV 1: a DMA manager thread in the Non-secure state attempted to execute either: DMAWFE to wait for a secure event H18DMASEV to create a secure event or secure
Appendix B: Register Details Register FTR0 Details Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort.
Appendix B: Field Name mfifo_err Bits 12 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 4:2 sro,ns sraz,n snsro 0x0 read undefined operand_invalid 1 sro,ns sraz,n snsro 0x0 Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.
Appendix B: Field Name Bits Type Reset Value reserved 29:19 sro,ns sraz,n snsro 0x0 read undefined data_read_err 18 sro,ns sraz,n snsro 0x0 Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: Register Details Description 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 11:8 sro,ns sraz,n snsro 0x0 read undefined ch_rdwr_err 7 sro,ns sraz,n snsro 0x0 Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure wri
Appendix B: Register Details Register (dmac) FTR2 Name FTR2 Software Name XDmaPs_FTCn_OFFSET(2) Relative Address 0x00000048 Absolute Address dmac0_ns: 0xF8004048 dmac0_s: 0xF8003048 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Default Type DMA Channel 2 Register FTR2 Details Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has ade
Appendix B: Field Name instr_fetch_err Bits 16 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.
Appendix B: Field Name ch_periph_err Bits 6 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP
Appendix B: Width 32 bits Access Type mixed Reset Value 0x00000000 Description Default Type DMA Channel 3 Register Details Register FTR3 Details Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort.
Appendix B: Field Name st_data_unavailable Bits 13 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.
Appendix B: Field Name ch_evnt_err Bits 5 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt.
Appendix B: Register Details Register FTR4 Details Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort.
Appendix B: Field Name mfifo_err Bits 12 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST: DMALD: 0: MFIFO contains sufficient space 1: MFIFO is too small to hold the data that DMALD requires. DMAST: 0: MFIFO contains sufficient data 1: MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 4:2 sro,ns sraz,n snsro 0x0 read undefined operand_invalid 1 sro,ns sraz,n snsro 0x0 Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0: valid operand 1: invalid operand. This fault is a precise abort.
Appendix B: Field Name Bits Type Reset Value reserved 29:19 sro,ns sraz,n snsro 0x0 read undefined data_read_err 18 sro,ns sraz,n snsro 0x0 Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: Register Details Description 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 11:8 sro,ns sraz,n snsro 0x0 read undefined ch_rdwr_err 7 sro,ns sraz,n snsro 0x0 Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCR registers to perform a secure read or secure write: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to perform a secure read or secure wri
Appendix B: Register Details Register (dmac) FTR6 Name FTR6 Software Name XDmaPs_FTCn_OFFSET(6) Relative Address 0x00000058 Absolute Address dmac0_ns: 0xF8004058 dmac0_s: 0xF8003058 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Default Type DMA Channel 6 Register FTR6 Details Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has ade
Appendix B: Field Name instr_fetch_err Bits 16 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates the AXI response that the DMAC receives on the RRESP bus after the DMA channel thread performs an instruction fetch: 0: OKAY response 1: EXOKAY, SLVERR, or DECERR response. This fault is a precise abort.
Appendix B: Field Name ch_periph_err Bits 6 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFP to wait for a secure peripheral, b) DMALDP or DMASTP
Appendix B: Width 32 bits Access Type mixed Reset Value 0x00000000 Description Default Type DMA Channel 7 Register Details Register FTR7 Details Field Name lockup_err Bits 31 Type sro,ns sraz,n snsro Reset Value 0x0 Description Indicates whether the DMA channel thread has locked-up because of resource starvation: 0: DMA channel has adequate resources 1: DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort.
Appendix B: Field Name st_data_unavailable Bits 13 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0: MFIFO contains all the data to enable the DMAST to complete 1: previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort.
Appendix B: Field Name ch_evnt_err Bits 5 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0: a DMA channel thread in the Non-secure state is not violating the security permissions 1: a DMA channel thread in the Non-secure state attempted to execute either: a) DMAWFE to wait for a secure event, or b) DMASEV to create a secure event or secure interrupt.
Appendix B: Register Details Register CSR0 Details Field Name Bits Type Reset Value Description reserved 31:22 rud 0x0 reserved,read undefined CNS 21 sro,ns sraz,n snsro 0x0 Security status of the DMA channel thread: 0: Secure state 1: Non-secure state.
Appendix B: Field Name wakeup_num Bits 8:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ...
Appendix B: Register Details Register CPC0 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name wakeup_num Bits 8:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ...
Appendix B: Description Register Details Channel PC for DMA Channel 1 Register CPC1 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 13:9 rud 0x0 reserved wakeup_num 8:4 sro,ns sraz,n snsro 0x0 When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for Event (WFE): 0 0000: waiting for event 0 0 0001: waiting for event 1 ...
Appendix B: Reset Value 0x00000000 Description Channel PC for DMA Channel 2 Register Details Register CPC2 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name dmawfp_b_ns Bits 14 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0: single operand set 1: burst operand set reserved 13:9 rud 0x0 reserved wakeup_num 8:4 sro,ns sraz,n snsro 0x0 When the DMA channel thread executes a WFE or WFP instruction, these bits indicate the event or peripheral number that the channel is waiting for: Waiting for E
Appendix B: Absolute Address Register Details dmac0_ns: 0xF800411C dmac0_s: 0xF800311C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Channel PC for DMA Channel 3 Register CPC3 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name dmawfp_periph Bits 15 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.
Appendix B: Register Details Register (dmac) CPC4 Name CPC4 Software Name XDmaPs_CPCn_OFFSET(4) Relative Address 0x00000124 Absolute Address dmac0_ns: 0xF8004124 dmac0_s: 0xF8003124 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Channel PC for DMA Channel 4 Register CPC4 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name dmawfp_periph Bits 15 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.
Appendix B: Register Details Register (dmac) CPC5 Name CPC5 Software Name XDmaPs_CPCn_OFFSET(5) Relative Address 0x0000012C Absolute Address dmac0_ns: 0xF800412C dmac0_s: 0xF800312C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Channel PC for DMA Channel 5 Register CPC5 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name dmawfp_periph Bits 15 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.
Appendix B: Register Details Register (dmac) CPC6 Name CPC6 Software Name XDmaPs_CPCn_OFFSET(6) Relative Address 0x00000134 Absolute Address dmac0_ns: 0xF8004134 dmac0_s: 0xF8003134 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Channel PC for DMA Channel 6 Register CPC6 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Field Name dmawfp_periph Bits 15 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand is set: 0: periph operand not set 1: periph operand set. Note: the status only applies when the channel is connected to one of the four peripheral request interfaces.
Appendix B: Register Details Register (dmac) CPC7 Name CPC7 Software Name XDmaPs_CPCn_OFFSET(7) Relative Address 0x0000013C Absolute Address dmac0_ns: 0xF800413C dmac0_s: 0xF800313C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Channel PC for DMA Channel 7 Register CPC7 Details Field Name pc_chnl Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Program counter (physical memory address) for DMA channel thread.
Appendix B: Software Name DA_0 Relative Address 0x00000404 Absolute Address dmac0_ns: 0xF8004404 Register Details dmac0_s: 0xF8003404 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Destination Addr DMA Channel 0 Register DAR0 Details Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.
Appendix B: Field Name dst_cache_ctrl Bits Type 27:25 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Programs the AXI AWCACHE signals that are used when the DMAC writes to the destination (0: Low, 1: High): Bit [27] programs AWCACHE[3] Hardwired Low to AWCACHE[2] Bit [26] programs AWCACHE[1] Bit [25] programs AWCACHE[0] Note: Setting AWCACHE[3,1]=b10 violates the AXI protocol.
Appendix B: Field Name dst_burst_size Bits Type 17:15 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved.
Appendix B: Field Name src_burst_len Bits 7:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size.
Appendix B: Register Details Register LC0_0 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.
Appendix B: Description Register Details Source address DMA Channel 1 Register SAR1 Details Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.
Appendix B: Register Details Register CCR1 Details Field Name Bits Type Reset Value Description reserved 31 rud 0x0 reserved, read undefined endian_swap_size 30:28 sro,ns sraz,n snsro 0x0 Data swap: little-endian and byte-invariant big-endian (BE-8) formats.
Appendix B: Field Name dst_burst_size Bits Type 17:15 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved.
Appendix B: Field Name src_burst_len Bits 7:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size.
Appendix B: Description Register Details Loop Counter 0 DMA Channel 1 Register LC0_1 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.
Appendix B: Access Type mixed Reset Value 0x00000000 Description Source Address DMA Channel 2 Register Details Register SAR2 Details Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.
Appendix B: Reset Value Register Details dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Description Channel Control DMA Channel 2 Register CCR2 Details Field Name Bits Type Reset Value Description reserved 31 rud 0x0 reserved, read undefined endian_swap_size 30:28 sro,ns sraz,n snsro 0x0 Data swap: little-endian and byte-invariant big-endian (BE-8) formats.
Appendix B: Field Name dst_burst_len Bits Type 21:18 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size.
Appendix B: Field Name src_prot_ctrl Bits 10:8 Register Details Type Reset Value Description sro,ns sraz,n snsro dmac0_ns: 0x0 Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): dmac0_s: 0x2 Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access.
Appendix B: Register Details Register (dmac) LC0_2 Name LC0_2 Software Name XDmaPs_LC0_n_OFFSET(2) Relative Address 0x0000044C Absolute Address dmac0_ns: 0xF800444C dmac0_s: 0xF800344C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Loop Counter 0 DMA Channel 2 Register LC0_2 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop count
Appendix B: Register Details Register LC1_2 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.
Appendix B: Register Details Register DAR3 Details Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.
Appendix B: Field Name dst_prot_ctrl Bits Type Reset Value 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Register Details Description Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access.
Appendix B: Field Name src_cache_ctrl Bits Type 13:11 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.
Appendix B: Field Name Bits src_burst_size 3:1 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved.
Appendix B: Register Details Register (dmac) LC1_3 Name LC1_3 Software Name XDmaPs_LC1_n_OFFSET(3) Relative Address 0x00000470 Absolute Address dmac0_ns: 0xF8004470 dmac0_s: 0xF8003470 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Loop Counter 1 DMA Channel 3 Register LC1_3 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop count
Appendix B: Register Details Register (dmac) DAR4 Name DAR4 Software Name XDmaPs_DA_n_OFFSET(4) Relative Address 0x00000484 Absolute Address dmac0_ns: 0xF8004484 dmac0_s: 0xF8003484 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Destination Addr DMA Channel 4 Register DAR4 Details Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.
Appendix B: Register Details Register CCR4 Details Field Name Bits Type Reset Value Description reserved 31 rud 0x0 reserved, read undefined endian_swap_size 30:28 sro,ns sraz,n snsro 0x0 Data swap: little-endian and byte-invariant big-endian (BE-8) formats.
Appendix B: Field Name dst_burst_size Bits Type 17:15 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved.
Appendix B: Field Name src_burst_len Bits 7:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size.
Appendix B: Description Register Details Loop Counter 0 DMA Channel 4 Register LC0_4 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.
Appendix B: Access Type mixed Reset Value 0x00000000 Description Source Address DMA Channel 5 Register Details Register SAR5 Details Field Name src_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Source data address (physical memory address) for DMA channel thread.
Appendix B: Reset Value Register Details dmac0_ns: 0x00000000 dmac0_s: 0x00800200 Description Channel Control DMA Channel 5 Register CCR5 Details Field Name Bits Type Reset Value Description reserved 31 rud 0x0 reserved, read undefined endian_swap_size 30:28 sro,ns sraz,n snsro 0x0 Data swap: little-endian and byte-invariant big-endian (BE-8) formats.
Appendix B: Field Name dst_burst_len Bits Type 21:18 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0000: 1 data transfer 0001: 2 data transfers 0010: 3 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size.
Appendix B: Field Name src_prot_ctrl Bits 10:8 Register Details Type Reset Value Description sro,ns sraz,n snsro dmac0_ns: 0x0 Programs the AXI ARPROT signals that are used for DMA reads of the source data (0: Low, 1: High): dmac0_s: 0x2 Bit [10] programs ARPROT[2] Bit [9] programs ARPROT[1] Bit [8] programs ARPROT[0] Note: Only DMA channels in the Secure state can program ARPROT[1] Low, that is, a secure access.
Appendix B: Register Details Register (dmac) LC0_5 Name LC0_5 Software Name XDmaPs_LC0_n_OFFSET(5) Relative Address 0x000004AC Absolute Address dmac0_ns: 0xF80044AC dmac0_s: 0xF80034AC Width 32 bits Access Type mixed Reset Value 0x00000000 Description Loop Counter 0 DMA Channel 5 Register LC0_5 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop count
Appendix B: Register Details Register LC1_5 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop counter one for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one.
Appendix B: Register Details Register DAR6 Details Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.
Appendix B: Field Name dst_prot_ctrl Bits Type Reset Value 24:22 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x2 Register Details Description Programs the AWPROT signals that are used when the DMAC writes the destination data (0: Low, 1: High): Bit [24] programs AWPROT[2] Bit [23] programs AWPROT[1] Bit [22] programs AWPROT[0] Note: Only DMA channels in the Secure state can program AWPROT[1] Low, that is, a secure access.
Appendix B: Field Name src_cache_ctrl Bits Type 13:11 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description Programs the AXI ARCACHE signals that are used for DMA reads of the source data (0: Low, 1: High): Bit [13] programs ARCACHE[2] Bit [12] programs ARCACHE[1] Bit [11] programs ARCACHE[0] Note: The DMAC ties ARCACHE[3] Low. Setting ARCACHE[2:1]= b10 violates the AXI protocol.
Appendix B: Field Name Bits src_burst_size 3:1 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 000: reads 1 byte per beat 001: reads 2 bytes per beat 010: reads 4 bytes per beat 011: reads 8 bytes per beat 100: reads 16 bytes per beat 101 to 111: reserved.
Appendix B: Register Details Register (dmac) LC1_6 Name LC1_6 Software Name XDmaPs_LC1_n_OFFSET(6) Relative Address 0x000004D0 Absolute Address dmac0_ns: 0xF80044D0 dmac0_s: 0xF80034D0 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Loop Counter 1 DMA Channel 6 Register LC1_6 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop count
Appendix B: Register Details Register (dmac) DAR7 Name DAR7 Software Name XDmaPs_DA_n_OFFSET(7) Relative Address 0x000004E4 Absolute Address dmac0_ns: 0xF80044E4 dmac0_s: 0xF80034E4 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Destination Addr DMA Channel 7 Register DAR7 Details Field Name dest_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Destination data address (physical memory address) for DMA channel thread.
Appendix B: Register Details Register CCR7 Details Field Name Bits Type Reset Value Description reserved 31 rud 0x0 reserved, read undefined endian_swap_size 30:28 sro,ns sraz,n snsro 0x0 Data swap: little-endian and byte-invariant big-endian (BE-8) formats.
Appendix B: Field Name dst_burst_size Bits Type 17:15 sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 000: writes 1 byte per beat 001: writes 2 bytes per beat 010: writes 4 bytes per beat 011: writes 8 bytes per beat 100: writes 16 bytes per beat 101 to 111: reserved.
Appendix B: Field Name src_burst_len Bits 7:4 Type sro,ns sraz,n snsro Reset Value 0x0 Register Details Description For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0000: 1 data transfer 0001: 2 data transfers ... 1111: 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size.
Appendix B: Description Register Details Loop Counter 0 DMA Channel 7 Register LC0_7 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 reserved, read undefined loop_counter_iteration 7:0 sro,ns sraz,n snsro 0x0 Provides the status of loop counter zero for the DMA channel thread. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero.
Appendix B: Reset Value 0x00000000 Description DMA Manager Execution Status Register Details Register DBGSTATUS Details Field Name Bits Type Reset Value Description reserved 31:1 rud 0x0 reserved, read undefined dbgstatus 0 sro,ns sraz,n snsro 0x0 The DMA manager Execution/Debug status: 0: Idle 1: Busy.
Appendix B: Description Register Details DMA Manager Instruction Part A Register DBGINST0 Details Field Name Bits Type Reset Value Description instruction_byte1 31:24 swo,n ssraz, nsns wo 0x0 instruction byte 1 instruction_byte0 23:16 swo,n ssraz, nsns wo 0x0 instruction byte 0 reserved 15:11 waz 0x0 reserved, write as 0 channel_num 10:8 swo,n ssraz, nsns wo 0x0 DMA channel number: 000: DMA channel 0 001: DMA channel 1 010: DMA channel 2 ...
Appendix B: Register Details Register DBGINST1 Details Field Name Bits Type Reset Value Description instruction_byte5 31:24 swo,n ssraz, nsns wo 0x0 instruction byte 5 instruction_byte4 23:16 swo,n ssraz, nsns wo 0x0 instruction byte 4 instruction_byte3 15:8 swo,n ssraz, nsns wo 0x0 instruction byte 3 instruction_byte2 7:0 swo,n ssraz, nsns wo 0x0 instruction byte 2 Register (dmac) CR0 Name CR0 Relative Address 0x00000E00 Absolute Address dmac0_ns: 0xF8004E00 dmac0_s: 0xF8003
Appendix B: Field Name num_chnls Bits 6:4 Register Details Type Reset Value Description sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x7 The DMA Controller supports eight channel threads. This register always reads 00111 (7d). reserved 3 rud 0x0 read undefined mgr_ns_at_rst 2 sro,ns sraz,n snsro 0x0 Indicates the status of the slcr.
Appendix B: Register Details Register (dmac) CR2 Name CR2 Relative Address 0x00000E08 Absolute Address dmac0_ns: 0xF8004E08 dmac0_s: 0xF8003E08 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Config. 2: DMA Mgr Boot Addr Register CR2 Details Field Name boot_addr Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description The boot address for the DMAC manager is hardwired to 0. This is a system memory address.
Appendix B: Absolute Address Register Details dmac0_ns: 0xF8004E10 dmac0_s: 0xF8003E10 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Config 4, Security of Periph Interfaces Register CR4 Details Field Name PNS Bits 31:0 Type sro,ns sraz,n snsro Reset Value 0x0 Description Reflects the slcr.TZ_DMA_PERIPH_NS register values for the four peripheral request interfaces when the DMAC is unreset.
Appendix B: Field Name rd_cap wr_q_dep Register Details Bits Type Reset Value 14:12 sro,ns sraz,n snsro dmac0_ns: 0x0 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0xF The depth of the Write Queue is hardwired at 16 lines. 11:8 dmac0_s: 0x7 Description The number of possible outstanding Read Transactions is hardwired at 8. reserved 7 rud 0x0 read undefined wr_cap 6:4 sro,ns sraz,n snsro dmac0_ns: 0x0 dmac0_s: 0x7 The number of outstanding Write Transactions is is hardwired at 8.
Appendix B: Absolute Address Register Details dmac0_ns: 0xF8004FE0 dmac0_s: 0xF8003FE0 Width 32 bits Access Type mixed Reset Value dmac0_ns: 0x00000000 dmac0_s: 0x00000030 Description Peripheral Idenfication register 0 Register periph_id_0 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 read undefined part_number_0 7:0 sro,ns sraz,n snsro dmac0_ns: 0x0 returns 0x30 dmac0_s: 0x30 Register (dmac) periph_id_1 Name periph_id_1 Software Name PERIPH_ID_1
Appendix B: Register Details Register (dmac) periph_id_2 Name periph_id_2 Software Name PERIPH_ID_2 Relative Address 0x00000FE8 Absolute Address dmac0_ns: 0xF8004FE8 dmac0_s: 0xF8003FE8 Width 32 bits Access Type mixed Reset Value dmac0_ns: 0x00000000 dmac0_s: 0x00000024 Description Peripheral Idenfication register 2 Register periph_id_2 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 read undefined revision 7:4 sro,ns sraz,n snsro dmac0_ns: 0x0 DMAC
Appendix B: Register Details Register periph_id_3 Details Field Name Bits Type Reset Value Description reserved 31:1 rud 0x0 read undefined integration_cfg 0 sro,ns sraz,n snsro 0x0 The DMAC does not contain integration test logic Register (dmac) pcell_id_0 Name pcell_id_0 Software Name PCELL_ID_0 Relative Address 0x00000FF0 Absolute Address dmac0_ns: 0xF8004FF0 dmac0_s: 0xF8003FF0 Width 32 bits Access Type mixed Reset Value dmac0_ns: 0x00000000 dmac0_s: 0x0000000D Description
Appendix B: Description Register Details Compontent Idenfication register 1 Register pcell_id_1 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 read undefined pcell_id_1 7:0 sro,ns sraz,n snsro dmac0_ns: 0x0 returns 0xF0 dmac0_s: 0xF0 Register (dmac) pcell_id_2 Name pcell_id_2 Software Name PCELL_ID_2 Relative Address 0x00000FF8 Absolute Address dmac0_ns: 0xF8004FF8 dmac0_s: 0xF8003FF8 Width 32 bits Access Type mixed Reset Value dmac0_ns: 0x0000000
Appendix B: Reset Value Register Details dmac0_ns: 0x00000000 dmac0_s: 0x000000B1 Description Compontent Idenfication register 3 Register pcell_id_3 Details Field Name Bits Type Reset Value Description reserved 31:8 rud 0x0 read undefined pcell_id_3 7:0 sro,ns sraz,n snsro dmac0_ns: 0x0 returns 0xB1 dmac0_s: 0xB1 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description spec_addr3_top 0x0000009C 32 mixed 0x00000000 Specific Address 3 Top [47:32] spec_addr4_bot 0x000000A0 32 rw 0x00000000 Specific Address 4 Bottom [31:0] spec_addr4_top 0x000000A4 32 mixed 0x00000000 Specific Address 4 Top [47:32] type_id_match1 0x000000A8 32 mixed 0x00000000 Type ID Match 1 type_id_match2 0x000000AC 32 mixed 0x00000000 Type ID Match 2 type_id_match3 0x000000B0 32 mi
Appendix B: Register Name Address Width Type Reset Value Register Details Description excessive_collisns 0x00000140 32 ro 0x00000000 Excessive Collisions late_collisns 0x00000144 32 ro 0x00000000 Late Collisions deferred_tx_frames 0x00000148 32 ro 0x00000000 Deferred Transmission Frames carrier_sense_errs 0x0000014C 32 ro 0x00000000 Carrier Sense Errors.
Appendix B: Register Name Address Width Type Reset Value Register Details Description timer_s 0x000001D0 32 rw 0x00000000 1588 timer seconds timer_ns 0x000001D4 32 mixed 0x00000000 1588 timer nanoseconds timer_adjust 0x000001D8 32 mixed 0x00000000 1588 timer adjust timer_incr 0x000001DC 32 mixed 0x00000000 1588 timer increment ptp_tx_s 0x000001E0 32 ro 0x00000000 PTP event frame transmitted seconds ptp_tx_ns 0x000001E4 32 ro 0x00000000 PTP event frame transmitted n
Appendix B: Register Details Register net_ctrl Details The network control register contains general MAC control functions for both receiver and transmitter. Field Name Bits Type Reset Value Description reserved 31:19 ro 0x0 Reserved, read as zero, ignored on write. flush_next_rx_dpram_ pkt 18 wo 0x0 Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.
Appendix B: Field Name clear_stat_regs Bits 5 Type wo Reset Value 0x0 (STATCLR) mgmt_port_en Clear statistics registers - this bit is write only. 4 rw 0x0 Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. 3 rw 0x0 Transmit enable - when set, it enables the GEM transmitter to send data.
Appendix B: Register Details Register net_cfg Details The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC Field Name Bits Type Reset Value Description unidir_en 31 rw 0x0 NA. ignore_ipg_rx_er 30 rw 0x0 Ignore IPG rx_er. When set rx_er has no effect on the GEM's operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. rx_bad_preamble 29 rw 0x0 Receive bad preamble.
Appendix B: Field Name dbus_width Bits 22:21 Type rw Reset Value 0x0 Register Details Description Data bus width. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. Zynq defines gem_dma_bus_width_def as 2'b00. 00: 32 bit AMBA AHB data bus width 01: 64 bit AMBA AHB data bus width 10: 128 bit AMBA AHB data bus width 11: 128 bit AMBA AHB data bus width mdc_clk_div 20:18 rw 0x2 (MDCCLKDIV) MDC clock division - set according to cpu_1xclk speed.
Appendix B: Field Name pause_en Bits Type Reset Value Description 13 rw 0x0 Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated. 12 rw 0x0 Retry test - must be set to zero for normal operation. (PAUSEEN) retry_test Register Details (RETRYTESTEN) If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition.
Appendix B: Field Name Bits full_duplex Type Reset Value Description 1 rw 0x0 Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half-duplex pin. 0 rw 0x0 Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin.
Appendix B: Register Details Register (GEM) dma_cfg Name dma_cfg Software Name XEMACPS_DMACR Relative Address 0x00000010 Absolute Address gem0: 0xE000B010 gem1: 0xE000C010 Width 32 bits Access Type mixed Reset Value 0x00020784 Description DMA Configuration Register dma_cfg Details Field Name Bits Type Reset Value Description reserved 31:25 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Field Name csum_gen_offload_en Bits 11 Type rw Reset Value 0x0 (TCPCKSUM) Register Details Description Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as zero, ignored on write.
Appendix B: Field Name Bits Type Reset Value Register Details Description ahb_endian_swp_mgm t_en 6 rw 0x0 AHB endian swap mode enable for management descriptor accesses - When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode. reserved 5 rw 0x0 Reserved, read as zero, ignored on write ahb_fixed_burst_len 4:0 rw 0x4 AHB fixed burst length for DMA data operations - Selects the burst length to attempt to use on the AHB when transferring frame data.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:9 ro 0x0 Reserved, read as zero, ignored on write. hresp_not_ok 8 wtc 0x0 Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit. 7 wtc 0x0 Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. (HRESPNOK) late_collision Cleared by writing a one to this bit.
Appendix B: Field Name Bits retry_limit_exceeded Type Reset Value Description 2 wtc 0x0 Retry limit exceeded - cleared by writing a one to this bit. 1 wtc 0x0 Collision occurred - set by the assertion of collision. (RXOVR) collision Register Details (FRAMERX) Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.
Appendix B: Register Details Register (GEM) tx_qbar Name tx_qbar Software Name XEMACPS_TXQBASE Relative Address 0x0000001C Absolute Address gem0: 0xE000B01C gem1: 0xE000C01C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Transmit Buffer Queue Base Address Register tx_qbar Details This register holds the start address of the transmit buffer queue (transmit buffers descriptor list).
Appendix B: Description Register Details Receive Status Register rx_status Details When read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. Field Name Bits Type Reset Value Description reserved 31:4 ro 0x0 Reserved, read as 0, ignored on write. hresp_not_ok 3 wtc 0x0 Hresp not OK - set when the DMA block sees hresp not OK. Cleared by writing a one to this bit.
Appendix B: Register Details Register intr_status Details Indicates an interrupt is asserted by the controller and is enabled (unmasked). 0: not asserted 1: asserted (if any bit reads as a 1, then the ethernet_int signal will be asserted to the interrupt controller) Field Name Bits Type Reset Value Description reserved 31:27 ro 0x0 Reserved, read as 0, ignored on write. tsu_sec_incr 26 wtc 0x0 TSU seconds register increment - indicates the register has incremented.
Appendix B: Field Name pause_zero Bits Type Reset Value Register Details Description 13 wtc 0x0 Pause time zero - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. 12 wtc 0x0 Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. 11 wtc 0x0 Hresp not OK - set when the DMA block sees hresp not OK.
Appendix B: Field Name Bits rx_complete Type Reset Value Description 1 wtc 0x0 Receive complete - a frame has been stored in memory. 0 wtc 0x0 Management frame sent - the PHY maintenance register has completed its operation.
Appendix B: Field Name pdelay_req_rx Bits Type Reset Value Register Details Description 22 wo x Enable PTP pdelay_req frame received interrupt 21 wo x Enable PTP sync frame transmitted interrupt 20 wo x Enable PTP delay_req frame transmitted interrupt 19 wo x Enable PTP sync frame received interrupt 18 wo x Enable PTP delay_req frame received interrupt partner_pg_rx 17 wo x NA autoneg_complete 16 wo x NA ext_intr 15 wo x Enable external interrupt pause_tx 14 wo x
Appendix B: Field Name Bits retry_ex_late_collisn Type Reset Value tx_underrun Description 5 wo x Enable retry limit exceeded or late collision interrupt 4 wo x Enable transmit buffer under run interrupt 3 wo x Enable transmit used bit read interrupt 2 wo x Enable receive used bit read interrupt 1 wo x Enable receive complete interrupt 0 wo x Enable management done interrupt (XEMACPS_IXR_RETR Y) Register Details (XEMACPS_IXR_URU N) tx_used_read (XEMACPS_IXR_TXUS ED) rx_used
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:27 wo x Reserved tsu_sec_incr 26 wo x Disable TSU seconds register increment interrupt pdelay_resp_tx 25 wo x Disable PTP pdelay_resp frame transmitted interrupt 24 wo x Disable PTP pdelay_req frame transmitted interrupt 23 wo x Disable PTP pdelay_resp frame received interrupt 22 wo x Disable PTP pdelay_req frame received interrupt 21 wo x Disable PTP sync frame transmitted interrupt 2
Appendix B: Field Name Bits rx_overrun Type Reset Value Register Details Description 10 wo x Disable receive overrun interrupt link_chng 9 wo x Disable link change interrupt reserved 8 wo x Not used tx_complete 7 wo x Disable transmit complete interrupt 6 wo x Disable transmit frame corruption due to AHB error interrupt 5 wo x Disable retry limit exceeded or late collision interrupt 4 wo x Disable transmit buffer under run interrupt 3 wo x Disable transmit used bit
Appendix B: Description Register Details Interrupt Mask Status Register intr_mask Details Indicates the mask state of each interrupt. 0: interrupt non masked (enabled) 1: interrupt masked (disabled), reset default All interrupts are disabled after a module reset. The interrupt masks are individually controlled using the write-only interrupt enable and disable registers.
Appendix B: Field Name pause_tx Bits Type Reset Value Register Details Description 14 ro,wo 0x1 Pause frame transmitted interrupt mask. 13 ro,wo 0x1 Pause time zero interrupt mask. 12 ro,wo 0x1 Pause frame with non-zero pause quantum interrupt mask. 11 ro,wo 0x1 Hresp not OK interrupt mask. 10 ro,wo 0x1 Receive overrun interrupt mask. link_chng 9 ro,wo 0x1 Link change interrupt mask.
Appendix B: Register Details Register (GEM) phy_maint Name phy_maint Software Name XEMACPS_PHYMNTNC Relative Address 0x00000034 Absolute Address gem0: 0xE000B034 gem1: 0xE000C034 Width 32 bits Access Type rw Reset Value 0x00000000 Description PHY Maintenance Register phy_maint Details The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation, which is signaled as complete when bit-2 is set in the network status register.
Appendix B: Register Details Register (GEM) rx_pauseq Name rx_pauseq Software Name XEMACPS_RXPAUSE Relative Address 0x00000038 Absolute Address gem0: 0xE000B038 gem1: 0xE000C038 Width 32 bits Access Type ro Reset Value 0x00000000 Description Received Pause Quantum Register rx_pauseq Details Field Name Bits Type Reset Value Description reserved 31:16 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Register Details Register (GEM) hash_bot Name hash_bot Software Name XEMACPS_HASHL Relative Address 0x00000080 Absolute Address gem0: 0xE000B080 gem1: 0xE000C080 Width 32 bits Access Type rw Reset Value 0x00000000 Description Hash Register Bottom [31:0] Register hash_bot Details The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames.
Appendix B: Register Details Register (GEM) spec_addr1_bot Name spec_addr1_bot Software Name XEMACPS_LADDR1L Relative Address 0x00000088 Absolute Address gem0: 0xE000B088 gem1: 0xE000C088 Width 32 bits Access Type rw Reset Value 0x00000000 Description Specific Address 1 Bottom [31:0] Register spec_addr1_bot Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0.
Appendix B: Register Details Register (GEM) spec_addr2_bot Name spec_addr2_bot Software Name XEMACPS_LADDR2L Relative Address 0x00000090 Absolute Address gem0: 0xE000B090 gem1: 0xE000C090 Width 32 bits Access Type rw Reset Value 0x00000000 Description Specific Address 2 Bottom [31:0] Register spec_addr2_bot Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0.
Appendix B: Register Details Register (GEM) spec_addr3_bot Name spec_addr3_bot Software Name XEMACPS_LADDR3L Relative Address 0x00000098 Absolute Address gem0: 0xE000B098 gem1: 0xE000C098 Width 32 bits Access Type rw Reset Value 0x00000000 Description Specific Address 3 Bottom [31:0] Register spec_addr3_bot Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0.
Appendix B: Register Details Register (GEM) spec_addr4_bot Name spec_addr4_bot Software Name XEMACPS_LADDR4L Relative Address 0x000000A0 Absolute Address gem0: 0xE000B0A0 gem1: 0xE000C0A0 Width 32 bits Access Type rw Reset Value 0x00000000 Description Specific Address 4 Bottom [31:0] Register spec_addr4_bot Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Least significant 32 bits of the destination address, that is bits 31:0.
Appendix B: Register Details Register (GEM) type_id_match1 Name type_id_match1 Software Name XEMACPS_MATCH1 Relative Address 0x000000A8 Absolute Address gem0: 0xE000B0A8 gem1: 0xE000C0A8 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Type ID Match 1 Register type_id_match1 Details Field Name Bits Type Reset Value Description copy_en 31 rw 0x0 Enable copying of type ID match 1 matched frames reserved 30:16 ro 0x0 Reserved, read as 0, ignored on write type_
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 30:16 ro 0x0 Reserved, read as 0, ignored on write type_id_match2 15:0 rw 0x0 Type ID match 2. For use in comparisons with received frames type ID/length field.
Appendix B: Register Details Register type_id_match4 Details Field Name Bits Type Reset Value Description copy_en 31 rw 0x0 Enable copying of type ID match 4 matched frames reserved 30:16 ro 0x0 Reserved, read as 0, ignored on write type_id_match4 15:0 rw 0x0 Type ID match 4. For use in comparisons with received frames type ID/length field.
Appendix B: Register Details Register (GEM) ipg_stretch Name ipg_stretch Software Name XEMACPS_STRETCH Relative Address 0x000000BC Absolute Address gem0: 0xE000B0BC gem1: 0xE000C0BC Width 32 bits Access Type mixed Reset Value 0x00000000 Description IPG stretch register Register ipg_stretch Details Field Name Bits Type Reset Value Description reserved 31:16 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 30:16 ro 0x0 Reserved, read as 0, ignored on write. user_def_vlan_type 15:0 rw 0x0 User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100).
Appendix B: Absolute Address Register Details gem0: 0xE000B0C8 gem1: 0xE000C0C8 Width 32 bits Access Type rw Reset Value 0x00000000 Description Specific Address Mask 1 Bottom [31:0] Register spec_addr1_mask_bot Details Field Name mask_bits_bot Bits 31:0 Type rw Reset Value 0x0 Description Setting a bit to one masks the corresponding bit in the specific address 1 register Register (GEM) spec_addr1_mask_top Name spec_addr1_mask_top Relative Address 0x000000CC Absolute Address gem0: 0xE00
Appendix B: Reset Value 0x00020118 Description Module ID Register Details Register module_id Details This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value. With GEM p23, it is 0x00020118. Field Name Bits Type Reset Value Description module_id 31:16 ro 0x2 Module identification number - for the GEM, this value is fixed at 0x0002.
Appendix B: Register Details Register (GEM) octets_tx_top Name octets_tx_top Software Name XEMACPS_OCTTXH Relative Address 0x00000104 Absolute Address gem0: 0xE000B104 gem1: 0xE000C104 Width 32 bits Access Type ro Reset Value 0x00000000 Description Octets transmitted [47:32] (in frames without error) Register octets_tx_top Details Bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. In statistics register block.
Appendix B: Register Details Register frames_tx Details Statistical counter for Frames transmitted without an error and exclude pause frames. NOTES for ALL Statistical registers for Frames Transferred: The a statistical counter is read by software, it is cleared to zero by the hardware. When a counter reaches its maximum value, it stops counting and is read with all 1s. The statistical counters must be read frequently enough if data loss is to be prevented.
Appendix B: Software Name XEMACPS_TXMCCNT Relative Address 0x00000110 Absolute Address gem0: 0xE000B110 Register Details gem1: 0xE000C110 Width 32 bits Access Type ro Reset Value 0x00000000 Description Multicast frames Tx Register multi_frames_tx Details Statistical counter for Multicast Frames transmitted without an error and exclude pause frames. Refer to the FRAMES_TX register for additional information.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:16 ro 0x0 Reserved, read as 0, ignored on write. pause_frames_tx 15:0 ro 0x0 Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter.
Appendix B: Access Type ro Reset Value 0x00000000 Description Frames Tx, 65 to 127-byte length Register Details Register frames_65to127b_tx Details Statistical counter of frames of 65 to 127 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information. Field Name Bits 31:0 Type ro Reset Value 0x0 Description 65 to127 byte frames transmitted without error.
Appendix B: Absolute Address Register Details gem0: 0xE000B124 gem1: 0xE000C124 Width 32 bits Access Type ro Reset Value 0x00000000 Description Frames Tx, 256 to 511-byte length Register frames_256to511b_tx Details Statistical counter of frames of 256 to 511 bytes that are transmitted without error. Does not include pause frames. Refer to the FRAMES_TX register for additional information.
Appendix B: Register Details Register (GEM) frames_1024to1518b_tx Name frames_1024to1518b_tx Software Name XEMACPS_TX1024CNT Relative Address 0x0000012C Absolute Address gem0: 0xE000B12C gem1: 0xE000C12C Width 32 bits Access Type ro Reset Value 0x00000000 Description Frame Tx, 1024 to 1518-byte length Register frames_1024to1518b_tx Details Statistical counter of frames of1024 to 1518 bytes that are transmitted without error. Does not include pause frames.
Appendix B: Register Details Once a statistics register has been read, it is automatically cleared. Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write. tx_under_runs 9:0 ro 0x0 Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented.
Appendix B: Absolute Address Register Details gem0: 0xE000B13C gem1: 0xE000C13C Width 32 bits Access Type ro Reset Value 0x00000000 Description Multiple Collision Frames Register multi_collisn_frames Details In statistics register block. Is reset to zero on a read and sticks at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data. For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register.
Appendix B: Register Details Once a statistics register has been read, it is automatically cleared. Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write. excessive_collisns 9:0 ro 0x0 Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
Appendix B: Relative Address 0x00000148 Absolute Address gem0: 0xE000B148 Register Details gem1: 0xE000C148 Width 32 bits Access Type ro Reset Value 0x00000000 Description Deferred Transmission Frames Register deferred_tx_frames Details In statistics register block. Is reset to zero on a read and stick at all ones when it counts to its maximum value. It should be read frequently enough to prevent loss of data.
Appendix B: Register Details For test purposes, it may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared. Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Field Name octets_rx_bot Bits 31:0 Type ro Reset Value 0x0 Register Details Description Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
Appendix B: Software Name XEMACPS_RXCNT Relative Address 0x00000158 Absolute Address gem0: 0xE000B158 Register Details gem1: 0xE000C158 Width 32 bits Access Type ro Reset Value 0x00000000 Description Frames Received Register frames_rx Details Statistical counter for Frames received without an error and exclude pause frames. NOTES for ALL Statistical registers for Frames Transferred: The a statistical counter is read by software, it is cleared to zero by the hardware.
Appendix B: Field Name Bits 31:0 Type ro Reset Value 0x0 Register Details Description Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
Appendix B: Reset Value 0x00000000 Description Pause Frames Rx Register Details Register pause_rx Details Statistical counter for Pause Frames received without an error. Refer to the FRAMES_RX register for additional information. Field Name Bits Type Reset Value Description reserved 31:16 ro 0x0 Reserved, read as 0, ignored on write. pause_rx 15:0 ro 0x0 Received pause frames - a 16 bit register counting the number of pause frames received without error.
Appendix B: Absolute Address Register Details gem0: 0xE000B16C gem1: 0xE000C16C Width 32 bits Access Type ro Reset Value 0x00000000 Description Frames Rx, 65 to 127-byte length Register frames_65to127b_rx Details Statistical counter for frames of 65 to 127 bytes in length that are received without an error and exclude pause frames. Refer to the FRAMES_RX register for additional information. Field Name Bits 31:0 Type ro Reset Value 0x0 Description 65 to 127 byte frames received without error.
Appendix B: Register Details Register (GEM) frames_256to511b_rx Name frames_256to511b_rx Software Name XEMACPS_RX256CNT Relative Address 0x00000174 Absolute Address gem0: 0xE000B174 gem1: 0xE000C174 Width 32 bits Access Type ro Reset Value 0x00000000 Description Frames Rx, 256 to 511-byte length Register frames_256to511b_rx Details Statistical counter for frames of 256 to 511 bytes in length that are received without an error and exclude pause frames.
Appendix B: Field Name Bits 31:0 Type ro Reset Value 0x0 Register Details Description 512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
Appendix B: Reset Value 0x00000000 Description Undersize frames received Register Details Register undersz_rx Details Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write. undersz_rx 9:0 ro 0x0 Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error.
Appendix B: Absolute Address Register Details gem0: 0xE000B18C gem1: 0xE000C18C Width 32 bits Access Type ro Reset Value 0x00000000 Description Jabbers received Register jab_rx Details Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Register Details Register (GEM) length_field_errors Name length_field_errors Software Name XEMACPS_RXLENGTHCNT Relative Address 0x00000194 Absolute Address gem0: 0xE000B194 gem1: 0xE000C194 Width 32 bits Access Type ro Reset Value 0x00000000 Description Length field frame errors Register length_field_errors Details Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Register Details Register rx_symbol_errors Details Field Name Bits Type Reset Value Description reserved 31:10 ro 0x0 Reserved, read as 0, ignored on write. rx_symbol_errors 9:0 ro 0x0 Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error.
Appendix B: Width 32 bits Access Type ro Reset Value 0x00000000 Description Receive resource errors Register Details Register rx_resource_errors Details Field Name Bits Type Reset Value Description reserved 31:18 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Software Name XEMACPS_RXIPCCNT Relative Address 0x000001A8 Absolute Address gem0: 0xE000B1A8 Register Details gem1: 0xE000C1A8 Width 32 bits Access Type ro Reset Value 0x00000000 Description IP header checksum errors Register ip_hdr_csum_errors Details Field Name Bits Type Reset Value Description reserved 31:8 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Register Details Register (GEM) udp_csum_errors Name udp_csum_errors Software Name XEMACPS_RXUDPCCNT Relative Address 0x000001B0 Absolute Address gem0: 0xE000B1B0 gem1: 0xE000C1B0 Width 32 bits Access Type ro Reset Value 0x00000000 Description UDP checksum error Register udp_csum_errors Details Field Name Bits Type Reset Value Description reserved 31:8 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Relative Address 0x000001CC Absolute Address gem0: 0xE000B1CC Register Details gem1: 0xE000C1CC Width 32 bits Access Type mixed Reset Value 0x00000000 Description 1588 timer sync strobe nanoseconds Register timer_strobe_ns Details Field Name Bits Type Reset Value Description reserved 31:30 ro 0x0 Reserved, read as 0, ignored on write ns_reg_val 29:0 rw 0x0 The value of the Timer Nanoseconds register Register (GEM) timer_s Name timer_s Software Name XEMACPS_1588_SE
Appendix B: Absolute Address Register Details gem0: 0xE000B1D4 gem1: 0xE000C1D4 Width 32 bits Access Type mixed Reset Value 0x00000000 Description 1588 timer nanoseconds Register timer_ns Details Field Name Bits Type Reset Value Description reserved 31:30 ro 0x0 Reserved, read as 0, ignored on write. timer_ct_ns 29:0 rw 0x0 Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register.
Appendix B: Register Details Register (GEM) timer_incr Name timer_incr Software Name XEMACPS_1588_INC Relative Address 0x000001DC Absolute Address gem0: 0xE000B1DC gem1: 0xE000C1DC Width 32 bits Access Type mixed Reset Value 0x00000000 Description 1588 timer increment Register timer_incr Details Field Name Bits Type Reset Value Description reserved 31:24 ro 0x0 Reserved, read as 0, ignored on write.
Appendix B: Register Details Register ptp_tx_s Details Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated.
Appendix B: Access Type ro Reset Value 0x00000000 Description PTP event frame received seconds Register Details Register ptp_rx_s Details Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated.
Appendix B: Relative Address 0x000001F0 Absolute Address gem0: 0xE000B1F0 Register Details gem1: 0xE000C1F0 Width 32 bits Access Type ro Reset Value 0x00000000 Description PTP peer event frame transmitted seconds Register ptp_peer_tx_s Details Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface.
Appendix B: Register Details Register (GEM) ptp_peer_rx_s Name ptp_peer_rx_s Software Name XEMACPS_PTPP_RXSEC Relative Address 0x000001F8 Absolute Address gem0: 0xE000B1F8 gem1: 0xE000C1F8 Width 32 bits Access Type ro Reset Value 0x00000000 Description PTP peer event frame received seconds Register ptp_peer_rx_s Details Field Name Bits 31:0 Type ro Reset Value 0x0 Description The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive
Appendix B: Register Details Register ptp_peer_rx_ns Details Field Name Bits Type Reset Value Description reserved 31:30 ro 0x0 Reserved, read as 0, ignored on write. ns_reg_val 29:0 ro 0x0 The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated.
Appendix B: Field Name Bits Type Reset Value Register Details Description gem_rx_pkt_buffer 20 ro x Takes the value of the `gem_rx_pkt_buffer DEFINE. Defined for Zynq. Includes the receiver packet buffer. gem_hprot_value 19:16 ro 0x1 Takes the value of the `gem_hprot_value DEFINE. For Zynq, set the fixed AHB HPROT value used during transfers. gem_jumbo_max_lengt h 15:0 ro 0x3FFF Takes the value of the `gem_jumbo_max_length DEFINE. Maximum length of jumbo frames accepted by receiver.
Appendix B: Access Type ro Reset Value 0x00000000 Description Design Configuration 4 Register Details Register design_cfg4 Details Field Name Bits Type Reset Value Description gem_tx_base2_fifo_size 31:16 ro 0x0 Takes the value of the `gem_tx_base2_fifo_size DEFINE. Base-2 equivalent of `gem_tx_fifo_size. gem_tx_fifo_size ro 0x0 Takes the value of the `gem_tx_fifo_size DEFINE.
Appendix B: Field Name Bits Type Reset Value Register Details Description gem_endian_swap_def 16:15 ro 0x2 Takes the value of the `gem_endian_swap_def DEFINE. Set to big endian data, little endian management descriptors in Zynq. gem_mdc_clock_div 14:12 ro 0x2 Takes the value of the `gem_mdc_clock_div DEFINE. Set default MDC clock divisor (can still be programmed) in Zynq. gem_dma_bus_width 11:10 ro 0x0 Takes the value of the `gem_dma_bus_width_def DEFINE.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description DIRM_0 0x00000204 32 rw 0x00000000 Direction mode (GPIO Bank0, MIO) OEN_0 0x00000208 32 rw 0x00000000 Output enable (GPIO Bank0, MIO) INT_MASK_0 0x0000020C 32 ro 0x00000000 Interrupt Mask Status (GPIO Bank0, MIO) INT_EN_0 0x00000210 32 wo 0x00000000 Interrupt Enable/Unmask (GPIO Bank0, MIO) INT_DIS_0 0x00000214 32 wo 0x00000000 Interrupt Disable/Mask (GPIO Bank0, MIO) INT_STAT_0 0x000
Appendix B: Register Name Address Width Type Reset Value Register Details Description INT_MASK_2 0x0000028C 32 ro 0x00000000 Interrupt Mask Status (GPIO Bank2, EMIO) INT_EN_2 0x00000290 32 wo 0x00000000 Interrupt Enable/Unmask (GPIO Bank2, EMIO) INT_DIS_2 0x00000294 32 wo 0x00000000 Interrupt Disable/Mask (GPIO Bank2, EMIO) INT_STAT_2 0x00000298 32 wtc 0x00000000 Interrupt Status (GPIO Bank2, EMIO) INT_TYPE_2 0x0000029C 32 rw 0xFFFFFFFF Interrupt Type (GPIO Bank2, EMIO)
Appendix B: Access Type mixed Reset Value x Description Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) Register Details Register MASK_DATA_0_LSW Details This register enables software to change the value being output on up to 16bits at one time selectively. Only data values with a corresponding deasserted mask bit will be changed. Output data values are unchanged and hold their previous value for bits which are masked.
Appendix B: Field Name Bits Type Reset Value Register Details Description MASK_0_MSW 31:16 wo 0x0 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] DATA_0_MSW 15:0 rw x Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] Register (gpio) MASK_DATA_1_LSW Name MASK_DATA_1_LSW Relative Address 0x00000008 Absolute Address 0xE000A008 Width 32 bits Access Type mixed Reset Value x Description Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) Register MASK_DATA_1_LSW Details Thi
Appendix B: Field Name Bits Type Reset Value Register Details Description MASK_1_MSW 21:16 wo 0x0 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] reserved 15:6 rw 0x0 Not used, read back as zero DATA_1_MSW 5:0 rw x Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] Register (gpio) MASK_DATA_2_LSW Name MASK_DATA_2_LSW Relative Address 0x00000010 Absolute Address 0xE000A010 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Maskable Output Data (GPIO B
Appendix B: Field Name Bits Type Reset Value Register Details Description MASK_2_MSW 31:16 wo 0x0 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] DATA_2_MSW 15:0 rw 0x0 Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] Register (gpio) MASK_DATA_3_LSW Name MASK_DATA_3_LSW Relative Address 0x00000018 Absolute Address 0xE000A018 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits) Register MASK_DATA_3_LSW
Appendix B: Field Name Bits Type Reset Value Register Details Description MASK_3_MSW 31:16 wo 0x0 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] DATA_3_MSW 15:0 rw 0x0 Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] Register (gpio) DATA_0 Name DATA_0 Software Name DATA Relative Address 0x00000040 Absolute Address 0xE000A040 Width 32 bits Access Type rw Reset Value x Description Output Data (GPIO Bank0, MIO) Register DATA_0 Details This register controls the value
Appendix B: Register Details Register DATA_1 Details This register operates in exactly the same manner as DATA_0, except that it controls bank1, which corresponds to MIO[53:32].
Appendix B: Register Details Register (gpio) DATA_0_RO Name DATA_0_RO Relative Address 0x00000060 Absolute Address 0xE000A060 Width 32 bits Access Type ro Reset Value x Description Input Data (GPIO Bank0, MIO) Register DATA_0_RO Details This register enables software to observe the value on the device pin. If the GPIO signal is configured as an output, then this would normally reflect the value being driven on the output. Writes to this register are ignored.
Appendix B: Register Details Register (gpio) DATA_2_RO Name DATA_2_RO Relative Address 0x00000068 Absolute Address 0xE000A068 Width 32 bits Access Type ro Reset Value 0x00000000 Description Input Data (GPIO Bank2, EMIO) Register DATA_2_RO Details This register operates in exactly the same manner as DATA_0_RO, except that it reflects bank2, which corresponds to EMIO[31:0].
Appendix B: Width 32 bits Access Type rw Reset Value 0x00000000 Description Direction mode (GPIO Bank0, MIO) Register Details Register DIRM_0 Details This register controls whether the IO pin is acting as an input or an output. Since the input logic is always enabled, this effectively enables/disables the output driver. Each bit of the bank is independently controlled. This register controls bank0, which corresponds to MIO[31:0].
Appendix B: Field Name OP_ENABLE_0 Bits 31:0 Type rw Reset Value 0x0 Register Details Description Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank Register (gpio) INT_MASK_0 Name INT_MASK_0 Software Name INTMASK Relative Address 0x0000020C Absolute Address 0xE000A20C Width 32 bits Access Type ro Reset Value 0x00000000 Description Interrupt Mask Status (GPIO Bank0, MIO) Register INT_MASK_0 Details This register shows which bits are
Appendix B: Description Register Details Interrupt Enable/Unmask (GPIO Bank0, MIO) Register INT_EN_0 Details This register is used to enable or unmask a GPIO input for use as an interrupt source. Writing a 1 to any bit of this register enables/unmasks that signal for interrupts. Reading from this register returns an unpredictable value. This register controls bank0, which corresponds to MIO[31:0].
Appendix B: Software Name INTSTS Relative Address 0x00000218 Absolute Address 0xE000A218 Width 32 bits Access Type wtc Reset Value 0x00000000 Description Interrupt Status (GPIO Bank0, MIO) Register Details Register INT_STAT_0 Details This registers shows if an interrupt event has occurred or not. Writing a 1 to a bit in this register clears the interrupt status for that bit. Writing a 0 to a bit in this register is ignored. This register controls bank0, which corresponds to MIO[31:0].
Appendix B: Field Name INT_TYPE_0 Bits 31:0 Type rw Reset Value 0xFFFFFFFF Register Details Description Interrupt type 0: level-sensitive 1: edge-sensitive Each bit configures the corresponding pin within the 32-bit bank Register (gpio) INT_POLARITY_0 Name INT_POLARITY_0 Software Name INTPOL Relative Address 0x00000220 Absolute Address 0xE000A220 Width 32 bits Access Type rw Reset Value 0x00000000 Description Interrupt Polarity (GPIO Bank0, MIO) Register INT_POLARITY_0 Details This re
Appendix B: Description Register Details Interrupt Any Edge Sensitive (GPIO Bank0, MIO) Register INT_ANY_0 Details If INT_TYPE is set to edge sensitive, then this register enables an interrupt event on both rising and falling edges. This register is ignored if INT_TYPE is set to level sensitive. This register controls bank0, which corresponds to MIO[31:0].
Appendix B: Description Register Details Output enable (GPIO Bank1, MIO) Register OEN_1 Details This register operates in exactly the same manner as OEN_0, except that it reflects bank1, which corresponds to MIO[53:32].
Appendix B: Field Name INT_ENABLE_1 Bits 21:0 Type wo Reset Value 0x0 Register Details Description Operation is the same as INT_EN_0[INT_ENABLE_0] Register (gpio) INT_DIS_1 Name INT_DIS_1 Relative Address 0x00000254 Absolute Address 0xE000A254 Width 22 bits Access Type wo Reset Value 0x00000000 Description Interrupt Disable/Mask (GPIO Bank1, MIO) Register INT_DIS_1 Details This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank1, which corresponds to
Appendix B: Register Details Register (gpio) INT_TYPE_1 Name INT_TYPE_1 Relative Address 0x0000025C Absolute Address 0xE000A25C Width 22 bits Access Type rw Reset Value 0x003FFFFF Description Interrupt Type (GPIO Bank1, MIO) Register INT_TYPE_1 Details This register operates in exactly the same manner as INT_TYPE_0, except that it reflects bank1, which corresponds to MIO[53:32].
Appendix B: Absolute Address 0xE000A264 Width 22 bits Access Type rw Reset Value 0x00000000 Description Interrupt Any Edge Sensitive (GPIO Bank1, MIO) Register Details Register INT_ANY_1 Details This register operates in exactly the same manner as INT_ANY_0, except that it reflects bank1, which corresponds to MIO[53:32].
Appendix B: Description Register Details Output enable (GPIO Bank2, EMIO) Register OEN_2 Details This register operates in exactly the same manner as OEN_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Appendix B: Field Name INT_ENABLE_2 Bits 31:0 Type wo Reset Value 0x0 Register Details Description Operation is the same as INT_EN_0[INT_ENABLE_0] Register (gpio) INT_DIS_2 Name INT_DIS_2 Relative Address 0x00000294 Absolute Address 0xE000A294 Width 32 bits Access Type wo Reset Value 0x00000000 Description Interrupt Disable/Mask (GPIO Bank2, EMIO) Register INT_DIS_2 Details This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank2, which corresponds t
Appendix B: Register Details Register (gpio) INT_TYPE_2 Name INT_TYPE_2 Relative Address 0x0000029C Absolute Address 0xE000A29C Width 32 bits Access Type rw Reset Value 0xFFFFFFFF Description Interrupt Type (GPIO Bank2, EMIO) Register INT_TYPE_2 Details This register operates in exactly the same manner as INT_TYPE_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Appendix B: Absolute Address 0xE000A2A4 Width 32 bits Access Type rw Reset Value 0x00000000 Description Interrupt Any Edge Sensitive (GPIO Bank2, EMIO) Register Details Register INT_ANY_2 Details This register operates in exactly the same manner as INT_ANY_0, except that it reflects bank2, which corresponds to EMIO[31:0].
Appendix B: Description Register Details Output enable (GPIO Bank3, EMIO) Register OEN_3 Details This register operates in exactly the same manner as OEN_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Appendix B: Field Name INT_ENABLE_3 Bits 31:0 Type wo Reset Value 0x0 Register Details Description Operation is the same as INT_EN_0[INT_ENABLE_0] Register (gpio) INT_DIS_3 Name INT_DIS_3 Relative Address 0x000002D4 Absolute Address 0xE000A2D4 Width 32 bits Access Type wo Reset Value 0x00000000 Description Interrupt Disable/Mask (GPIO Bank3, EMIO) Register INT_DIS_3 Details This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank3, which corresponds t
Appendix B: Register Details Register (gpio) INT_TYPE_3 Name INT_TYPE_3 Relative Address 0x000002DC Absolute Address 0xE000A2DC Width 32 bits Access Type rw Reset Value 0xFFFFFFFF Description Interrupt Type (GPIO Bank3, EMIO) Register INT_TYPE_3 Details This register operates in exactly the same manner as INT_TYPE_0, except that it reflects bank3, which corresponds to EMIO[63:32].
Appendix B: Absolute Address 0xE000A2E4 Width 32 bits Access Type rw Reset Value 0x00000000 Description Interrupt Any Edge Sensitive (GPIO Bank3, EMIO) Register Details Register INT_ANY_3 Details This register operates in exactly the same manner as INT_ANY_0, except that it reflects bank3, which corresponds to EMIO[63:32]. Field Name INT_ON_ANY_3 Bits 31:0 Type rw Reset Value 0x0 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.
Appendix B: Register Details B.20 Interconnect QoS (qos301) Module Name Interconnect QoS (qos301) Base Address 0xF8946000 gpv_qos301_cpu 0xF8947000 gpv_qos301_dmac 0xF8948000 gpv_qos301_iou Description AMBA Network Interconnect Advanced Quality of Service (QoS-301) Vendor Info ARM QoS-301 Register Summary Register Name Address Width Type Reset Value Description qos_cntl 0x0000010C 32 rw 0x00000000 The QoS control register contains the enable bits for all the regulators.
Appendix B: Description Register Details The QoS control register contains the enable bits for all the regulators. Register qos_cntl Details By default, all of the bits are set to 0, and no regulation is enabled. Regulation only takes place when both the enable bit is set, and its corresponding regulation value is non-zero. The QoS regulators are reset whenever they are re-enabled.
Appendix B: Register Details A value of 0 for both the integer and fractional parts disables the programmable regulation so that the NIC-301 base product configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The AW and AR outstanding transaction limits are enabled when you set the corresponding en_aw_ot or en_ar_ot control bits of the QoS control register.
Appendix B: Width 32 bits Access Type rw Reset Value 0x00000000 Description AW channel peak rate Register Details Register aw_p Details Field Name Bits 31:24 Type rw Reset Value 0x0 Description channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.
Appendix B: Reset Value 0x00000000 Description AW channel average rate Register Details Register aw_r Details Field Name Bits 31:20 Type rw Reset Value 0x0 Description channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.
Appendix B: Reset Value 0x00000000 Description AR channel burstiness allowance Register Details Register ar_b Details Field Name Bits 15:0 Type rw Reset Value 0x0 Description channel burstiness (integer number of transfers) Register (qos301) ar_r Name ar_r Relative Address 0x0000012C Absolute Address gpv_qos301_cpu: 0xF894612C gpv_qos301_dmac: 0xF894712C gpv_qos301_iou: 0xF894812C Width 32 bits Access Type rw Reset Value 0x00000000 Description AR channel average rate Register ar_r D
Appendix B: Register Details B.21 NIC301 Address Region Control (nic301_addr_region_ctrl_registers) Module Name NIC301 Address Region Control (nic301_addr_region_ctrl_registers) Software Name XARC Base Address 0xF8900000 gpv_trustzone Description AMBA NIC301 TrustZone.
Appendix B: Width 1 bits Access Type wo Reset Value 0x00000000 Description M_AXI_GP1 security setting Register Details Register security_gp1_axi Details Field Name gp1_axi Bits 0 Type wo Reset Value 0x0 Description Controls the transactions from M_AXI_GP1 to PL: 0 - Always secure 1 - Always non-secure. Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Details Register Control_reg0 Details Field Name divisor_a Bits 15:14 Type rw Reset Value 0x0 Divisor for stage A clock divider. (DIV_A) divisor_b Description 0 - 3: Divides the input pclk frequency by divisor_a + 1. 13:8 rw 0x0 Divisor for stage B clock divider. (DIV_B) 0 - 63 : Divides the output frequency from divisor_a by divisor_b + 1. reserved 7 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Relative Address 0x00000004 Absolute Address i2c0: 0xE0004004 Register Details i2c1: 0xE0005004 Width 16 bits Access Type ro Reset Value 0x00000000 Description Status register Register Status_reg0 Details Field Name Bits Type Reset Value Description reserved 15:9 ro 0x0 Reserved, read as zero, ignored on write. BA 8 ro 0x0 Bus Active 1 - ongoing transfer on the I2C bus.
Appendix B: Access Type mixed Reset Value 0x00000000 Description IIC Address register Register Details Register I2C_address_reg0 Details Field Name Bits Type Reset Value Description reserved 15:10 ro 0x0 Reserved, read as zero, ignored on write. ADD 9:0 rw 0x0 Address (MASK) 0 - 1024: Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
Appendix B: Width 16 bits Access Type mixed Reset Value 0x00000000 Description IIC interrupt status register Register Details Register Interrupt_status_reg0 Details Field Name Bits Type Reset Value Description reserved 15:10 ro 0x0 Reserved, read as zero, ignored on write. ARB_LOST 9 wtc 0x0 arbitration lost (IXR_ARB_LOST) 1 = master loses bus ownership during a transfer due to ongoing arbitration reserved 8 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Register Details Register (IIC) Transfer_size_reg0 Name Transfer_size_reg0 Software Name TRANS_SIZE Relative Address 0x00000014 Absolute Address i2c0: 0xE0004014 i2c1: 0xE0005014 Width 8 bits Access Type rw Reset Value 0x00000000 Description Transfer Size Register Register Transfer_size_reg0 Details This register's meaning varies according to the operating mode as follows: * Master transmitter mode: number of data bytes still not transmitted minus one * Master receiver mode: nu
Appendix B: Register Details Register Slave_mon_pause_reg0 Details Field Name Bits Type Reset Value Description reserved 7:4 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Register Details Register Intrpt_mask_reg0 Details Each bit in this register corresponds to a bit in the interrupt status register. If bit i in the interrupt mask register is set, the corresponding bit in the interrupt status register is ignored. Otherwise, an interrupt is generated whenever bit i in the interrupt status register is set. Bits in this register are set through a write to the interrupt disable register and are cleared through a write to the interrupt enable register.
Appendix B: Register Details Register (IIC) Intrpt_enable_reg0 Name Intrpt_enable_reg0 Software Name IER Relative Address 0x00000024 Absolute Address i2c0: 0xE0004024 i2c1: 0xE0005024 Width 16 bits Access Type mixed Reset Value 0x00000000 Description Interrupt Enable Register Register Intrpt_enable_reg0 Details This register has the same format as the interrupt status register.
Appendix B: Register Details Register (IIC) Intrpt_disable_reg0 Name Intrpt_disable_reg0 Software Name IDR Relative Address 0x00000028 Absolute Address i2c0: 0xE0004028 i2c1: 0xE0005028 Width 16 bits Access Type mixed Reset Value 0x00000000 Description Interrupt Disable Register Register Intrpt_disable_reg0 Details This register has the same format as the interrupt status register.
Appendix B: Field Name DATA Bits 1 Type wo Reset Value 0x0 (IXR_DATA) Register Details Description Master Write or Slave Transmitter Master Read or Slave Receiver 1 = disable this interrupt COMP 0 wo 0x0 (IXR_COMP) Transfer complete Will be set when transfer is complete 1 = disable this interrupt Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Appendix B: Register Details B.23 L2 Cache (L2Cpl310) Module Name L2 Cache (L2Cpl310) Base Address 0xF8F02000 l2cache Description L2 cache PL310 Vendor Info ARM Register Summary Register Name reg0_cache_id Address 0x00000000 Width Type 32 mixed Reset Value 0x410000C8 Description cache ID register, Returns the 32-bit device ID code it reads off the CACHEID input bus. The value is specified by the system integrator.
Appendix B: Register Name reg2_ev_counter1 Address 0x0000020C Width Type 32 rw Reset Value 0x00000000 Register Details Description Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register. reg2_ev_counter0 0x00000210 32 rw 0x00000000 Enable the programmer to read off the counter value.
Appendix B: Register Name reg2_int_mask_status Address 0x00000218 Width Type 32 mixed Reset Value 0x00000000 Register Details Description This register is a read-only.It returns the masked interrupt status. This register can be accessed by secure and non-secure operations. The register gives an AND function of the raw interrupt status with the values of the interrupt mask register. All the bits are cleared by a reset. A write to this register is ignored.
Appendix B: Register Name reg7_inv_way Address 0x0000077C Width Type 32 mixed Reset Value 0x00000000 Register Details Description Invalidate by Way Invalidate all data in specified ways, including dirty data. An Invalidate by way while selecting all cache ways is equivalent to invalidating all cache entries. Completes as a background task with the way, or ways, locked, preventing allocation.
Appendix B: Register Name reg7_clean_inv_way Address 0x000007FC Width Type 32 mixed Reset Value 0x00000000 Register Details Description Clean and Invalidate by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not valid. Completes as a background task with the way, or ways, locked, preventing allocation.
Appendix B: Register Name Address Width Type Reset Value Register Details Description reg9_lock_line_en 0x00000950 32 mixed 0x00000000 Lockdown by Line Enable Register. reg9_unlock_way 0x00000954 32 mixed 0x00000000 Cache lockdown by way To control the cache lockdown by way and the cache lockdown by master mechanisms see the tables from Table 3-20 to Table 3-35 on page 3-31. For these tables each bit has the following meaning: 0 allocation can occur in the corresponding way.
Appendix B: Register Name reg15_debug_ctrl Address 0x00000F40 Width Type 32 mixed Reset Value 0x00000000 Register Details Description The Debug Control Register forces specific cache behavior required for debug. This register has read-only, non-secure, or read and write, secure, permission. Any secure access and non-secure access can read this register. Only a secure access can write to this register.
Appendix B: Description Register Details cache ID register, Returns the 32-bit device ID code it reads off the CACHEID input bus. The value is specified by the system integrator.
Appendix B: Field Name Bits Type Reset Value Register Details Description L2_assoc_D 18 ro 0x0 Read from Auxiliary Control Register bit 16 reserved 17:14 waz 0x0 reserved l2cache_line_len_D 13:12 ro 0x0 L2 cache line length - 00-32 bytes Isize_11 11 waz,r az 0x0 fixed to 0 Isize_mid 10:8 ro 0x3 L2 cache way size Read from Auxiliary Control Register[19:17] Isize_7 7 waz,r az 0x0 fixed to 0 L2_assoc_I 6 ro 0x0 Read from Auxiliary Control Register bit 16 reserved 5:2
Appendix B: Access Type mixed Reset Value 0x02060000 Description auxilary control register, reset value: 0x02020000 Register Details Register reg1_aux_control Details Field Name Bits Type Reset Value Description reserved 31 waz,r az 0x0 reserved, reserved early_bresp_en 30 rw 0x0 Early BRESP enable 0 = Early BRESP disabled. This is the default. 1 = Early BRESP enabled. instr_prefetch_en 29 rw 0x0 Instruction prefetch enable 0 = Instruction prefetching disabled.
Appendix B: Field Name Bits force_write_alloc 24:23 Type rw Reset Value 0x0 Register Details Description Force write allocate b00 = Use AWCACHE attributes for WA. This is the default. b01 = Force no allocate, set WA bit always 0. b10 = Override AWCACHE attributes, set WA bit always 1, all cacheable write misses become write allocated. b11 = Internally mapped to 00. See Cache operation on page 2-11 for more information.
Appendix B: Field Name Bits ex_cache_config 12 Type rw Reset Value 0x0 Register Details Description Exclusive cache configuration 0 = Disabled. This is the default. 1 = Enabled, store_buff_dev_lim_en 11 rw 0x0 Store buffer device limitation Enable 0 = Store buffer device limitation disabled. Device writes can take all slots in store buffer. This is the default. 1= Store buffer device limitation enabled.
Appendix B: Register Details Register reg1_tag_ram_control Details Field Name Bits Type Reset Value Description reserved 31:11 waz,r az 0x0 reserved, reserved ram_wr_access_lat 10:8 rw 0x7 RAM write access latency Default value depends on the value of pl310_TAG_WRITE_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency.
Appendix B: Register Details Register (L2Cpl310) reg1_data_ram_control Name reg1_data_ram_control Relative Address 0x0000010C Absolute Address 0xF8F0210C Width 32 bits Access Type mixed Reset Value 0x00000777 Description configures data RAM latencies Register reg1_data_ram_control Details Field Name Bits Type Reset Value Description reserved 31:11 waz,r az 0x0 reserved, reserved ram_wr_access_lat 10:8 rw 0x7 RAM write access latency Default value depends on the value of pl310_D
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 3 waz,r az 0x0 reserved, reserved ran_setup_lat 2:0 rw 0x7 RAM setup latency Default value depends on the value of pl310_DATA_SETUP_LAT b000 = 1 cycle of latency, there is no additional latency. b001 = 2 cycles of latency. b010 = 3 cycles of latency. b011 = 4 cycles of latency. b100 = 5 cycles of latency. b101 = 6 cycles of latency. b110 = 7 cycles of latency. b111 = 8 cycles of latency.
Appendix B: Relative Address 0x00000204 Absolute Address 0xF8F02204 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Enables event counter 1 to be driven by a specific event. Counter 1 Register Details increments when the event occurs.
Appendix B: Register Details Width 32 bits Access Type mixed Reset Value 0x00000000 Description Enables event counter 0 to be driven by a specific event. Counter 0 increments when the event occurs.
Appendix B: Description Register Details Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register. Register reg2_ev_counter1 Details Field Name counter_val Bits 31:0 Type rw Reset Value 0x0 Description Total of the event selected. If a counter reaches its maximum value, it saturates at that value until it is reset.
Appendix B: Description Register Details This register enables or masks interrupts from being triggered on the external pins of the cache controller. Figure 3-8 on page 3-17 shows the register bit assignments. The bit assignments enables the masking of the interrupts on both their individual outputs and the combined L2CCINTR line. Clearing a bit by writing a 0, disables the interrupt triggering on that pin. All bits are cleared by a reset.
Appendix B: Description Register Details This register is a read-only.It returns the masked interrupt status. This register can be accessed by secure and non-secure operations. The register gives an AND function of the raw interrupt status with the values of the interrupt mask register. All the bits are cleared by a reset. A write to this register is ignored. Bits read can be HIGH or LOW: HIGH If the bits read HIGH, they reflect the status of the input lines triggering an interrupt.
Appendix B: Register Details Register reg2_int_raw_status Details Field Name Bits Type Reset Value Description reserved 31:9 raz 0x0 reserved DECERR 8 ro 0x0 DECERR: DECERR from L3 SLVERR 7 ro 0x0 SLVERR: SLVERR from L3 ERRRD 6 ro 0x0 ERRRD: Error on L2 data RAM, Read ERRRT 5 ro 0x0 ERRRT: Error on L2 tag RAM, Read ERRWD 4 ro 0x0 ERRWD: Error on L2 data RAM, Write ERRWT 3 ro 0x0 ERRWT: Error on L2 tag RAM, Write PARRD 2 ro 0x0 PARRD: Parity Error on L2 data RAM,
Appendix B: Field Name Bits Type Reset Value Register Details Description PARRT 1 wtc 0x0 PARRT: Parity Error on L2 tag RAM, Read ECNTR 0 wtc 0x0 ECNTR: Event Counter1/0 Overflow Increment Register (L2Cpl310) reg7_cache_sync Name reg7_cache_sync Relative Address 0x00000730 Absolute Address 0xF8F02730 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Drain the STB.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 4:1 waz 0x0 reserved c 0 rw 0x0 C Flag When written must be 0. When read, indicates that a background operation is in progress Register (L2Cpl310) reg7_inv_way Name reg7_inv_way Relative Address 0x0000077C Absolute Address 0xF8F0277C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Invalidate by Way Invalidate all data in specified ways, including dirty data.
Appendix B: Register Details Register reg7_clean_pa Details Field Name Bits Type Reset Value Description tag 31:12 rw 0x0 tag index 11:5 rw 0x0 index reserved 4:1 waz 0x0 reserved c 0 rw 0x0 C Flag When written must be 0.
Appendix B: Register Details Access Type mixed Reset Value 0x00000000 Description Clean by Way Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not dirty. The valid bits are unchanged. Completes as a background task with the way, or ways, locked, preventing allocation.
Appendix B: Register Details Relative Address 0x000007F8 Absolute Address 0xF8F027F8 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Clean and Invalidate Line by Set/Way Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty.
Appendix B: Register Details Register (L2Cpl310) reg9_d_lockdown0 Name reg9_d_lockdown0 Relative Address 0x00000900 Absolute Address 0xF8F02900 Width 32 bits Access Type mixed Reset Value 0x00000000 Description All reg9 registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Each register pair (reg9_d_lockdown, reg9_i_lockdown) is for accesses coming from a particular master.
Appendix B: Register Details Register (L2Cpl310) reg9_d_lockdown1 Name reg9_d_lockdown1 Relative Address 0x00000908 Absolute Address 0xF8F02908 Width 32 bits Access Type mixed Reset Value 0x00000000 Description data lock down 1 Register reg9_d_lockdown1 Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved DATALOCK001 15:0 rw 0x0 Use for master CPU1 Register (L2Cpl310) reg9_i_lockdown1 Name reg9_i_lockdown1 Relative Address 0x0000090C Ab
Appendix B: Access Type mixed Reset Value 0x00000000 Description data lock down 2 Register Details Register reg9_d_lockdown2 Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved reserved 15:0 rw 0x0 reserved Register (L2Cpl310) reg9_i_lockdown2 Name reg9_i_lockdown2 Relative Address 0x00000914 Absolute Address 0xF8F02914 Width 32 bits Access Type mixed Reset Value 0x00000000 Description instruction lock down 2 Register reg9_i_lockdown
Appendix B: Register Details Register reg9_d_lockdown3 Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved reserved 15:0 rw 0x0 reserved Register (L2Cpl310) reg9_i_lockdown3 Name reg9_i_lockdown3 Relative Address 0x0000091C Absolute Address 0xF8F0291C Width 32 bits Access Type mixed Reset Value 0x00000000 Description instruction lock down 3 Register reg9_i_lockdown3 Details Field Name Bits Type Reset Value Description reserved 31:16
Appendix B: Register Details Register (L2Cpl310) reg9_i_lockdown4 Name reg9_i_lockdown4 Relative Address 0x00000924 Absolute Address 0xF8F02924 Width 32 bits Access Type mixed Reset Value 0x00000000 Description instruction lock down 4 Register reg9_i_lockdown4 Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved INSTRLOCK100 15:0 rw 0x0 Use for ACP master with SAXIACPAxID[2:1]=00 Register (L2Cpl310) reg9_d_lockdown5 Name reg9_d_lockdown5
Appendix B: Access Type mixed Reset Value 0x00000000 Description instruction lock down 5 Register Details Register reg9_i_lockdown5 Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved INSTRLOCK101 15:0 rw 0x0 Use for ACP master with SAXIACPAxID[2:1]=01 Register (L2Cpl310) reg9_d_lockdown6 Name reg9_d_lockdown6 Relative Address 0x00000930 Absolute Address 0xF8F02930 Width 32 bits Access Type mixed Reset Value 0x00000000 Description dat
Appendix B: Register Details Register reg9_i_lockdown6 Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved INSTRLOCK110 15:0 rw 0x0 Use for ACP master with SAXIACPAxID[2:1]=10 Register (L2Cpl310) reg9_d_lockdown7 Name reg9_d_lockdown7 Relative Address 0x00000938 Absolute Address 0xF8F02938 Width 32 bits Access Type mixed Reset Value 0x00000000 Description data lock down 7 Register reg9_d_lockdown7 Details Field Name Bits Type Reset Valu
Appendix B: Register Details Register (L2Cpl310) reg9_lock_line_en Name reg9_lock_line_en Relative Address 0x00000950 Absolute Address 0xF8F02950 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Lockdown by Line Enable Register. Register reg9_lock_line_en Details Field Name Bits Type Reset Value Description reserved 31:1 waz,r az 0x0 reserved lock_down_by_line_en able 0 rw 0x0 0 = Lockdown by line disabled. This is the default. 1 = Lockdown by line enabled.
Appendix B: Register Details Register reg9_unlock_way Details Field Name Bits Type Reset Value Description reserved 31:16 waz,r az 0x0 reserved unlock_all_lines_by_w ay_operation 15:0 rw 0x0 For all bits: 0 = Unlock all lines disabled. This is the default. 1 = Unlock all lines operation in progress for the corresponding way.
Appendix B: Register Details Reset Value 0xFFF00000 Description When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and
Appendix B: Field Name DWB Bits 1 Type rw Reset Value 0x0 Register Details Description DWB: Disable write-back, force WT 0 = Enable write-back behavior. This is the default. 1 = Force write-through behavior DCL 0 rw 0x0 DCL: Disable cache linefill 0 = Enable cache linefills. This is the default. 1 = Disable cache linefills.
Appendix B: Field Name data_pref_en Bits 28 Type rw Reset Value 0x0 Register Details Description Data prefetch enable: You can set the following options for this register bit: 0 Data prefetching disabled. This is the default. 1 Data prefetching enabled. double_linefill_on_wra pread_en 27 rw 0x0 Double linefill on WRAP read disable: You can set the following options for this register bit: 0 Double linefill on WRAP read enabled. This is the default.
Appendix B: Register Details Register (L2Cpl310) reg15_power_ctrl Name reg15_power_ctrl Relative Address 0x00000F80 Absolute Address 0xF8F02F80 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Purpose Controls the operating mode clock and power modes. Usage constraints There are no usage constraints.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description ICCIDR 0x000001FC 32 ro 0x3901243B CPU Interface Implementer Identification Register Global_Timer_Counter _Register0 0x00000200 32 rw 0x00000000 Global Timer Counter Register 0 Global_Timer_Counter _Register1 0x00000204 32 rw 0x00000000 Global Timer Counter Register 1 Global_Timer_Control_ 0x00000208 Register 32 rw 0x00000000 Global Timer Control Register Global_Timer_Interrup t_Status_Regist
Appendix B: Register Name Address Width Type Reset Value Register Details Description ICDISR0 0x00001080 32 rw 0x00000000 Interrupt Security Register_0 ICDISR1 0x00001084 32 rw 0x00000000 Interrupt Security Register_1 ICDISR2 0x00001088 32 rw 0x00000000 Interrupt Security Register_2 ICDISER0 0x00001100 32 rw 0x0000FFFF Interrupt Set-enable Register 0 ICDISER1 0x00001104 32 rw 0x00000000 Interrupt Set-enable Register 1 ICDISER2 0x00001108 32 rw 0x00000000 Interrupt
Appendix B: Register Name Address Width Type Reset Value Register Details Description ICDIPR10 0x00001428 32 rw 0x00000000 Interrupt Priority Register_10 ICDIPR11 0x0000142C 32 rw 0x00000000 Interrupt Priority Register_11 ICDIPR12 0x00001430 32 rw 0x00000000 Interrupt Priority Register_12 ICDIPR13 0x00001434 32 rw 0x00000000 Interrupt Priority Register_13 ICDIPR14 0x00001438 32 rw 0x00000000 Interrupt Priority Register_14 ICDIPR15 0x0000143C 32 rw 0x00000000 Interr
Appendix B: Register Name Address Width Type Reset Value Register Details Description ICDIPTR12 0x00001830 32 rw 0x00000000 Interrupt Processor Targets Register 12 ICDIPTR13 0x00001834 32 rw 0x00000000 Interrupt Processor Targets Register 13 ICDIPTR14 0x00001838 32 rw 0x00000000 Interrupt Processor Targets Register 14 ICDIPTR15 0x0000183C 32 rw 0x00000000 Interrupt Processor Targets Register 15 ICDIPTR16 0x00001840 32 rw 0x00000000 Interrupt Processor Targets Register 16
Appendix B: Register Name Address Width Type Reset Value Register Details Description ICPIDR4 0x00001FD0 32 rw 0x00000004 Peripheral ID4 ICPIDR5 0x00001FD4 32 rw 0x00000000 Peripheral ID5 ICPIDR6 0x00001FD8 32 rw 0x00000000 Peripheral ID6 ICPIDR7 0x00001FDC 32 rw 0x00000000 Peripheral ID7 ICPIDR0 0x00001FE0 32 rw 0x00000090 Peripheral ID0 ICPIDR1 0x00001FE4 32 rw 0x000000B3 Peripheral ID1 ICPIDR2 0x00001FE8 32 rw 0x0000001B Peripheral ID2 ICPIDR3 0x00001FEC
Appendix B: Field Name Bits SCU_standby_enable 5 Type rw Reset Value 0x0 Register Details Description When set, SCU CLK is turned off when all processors are in WFI mode, there is no pending request on the ACP (if implemented), and there is no remaining activity in the SCU. When SCU CLK is off, ARREADYS, AWREADYS and WREADYS on the ACP are forced LOW. The clock is turned on when any processor leaves WFI mode, or if there is a new request on the ACP.
Appendix B: Relative Address 0x00000004 Absolute Address 0xF8F00004 Width 32 bits Access Type ro Reset Value 0x00000501 Description SCU Configuration Register Register Details Register SCU_CONFIGURATION_REGISTER Details Field Name Bits Type Reset Value Description reserved 31:16 ro 0x0 Should Be Zero (SBZ) Tag_RAM_sizes 15:8 ro 0x5 Bits [15:14] indicate Cortex-A9 processor CPU3 tag RAM size if present. Bits [13:12] indicate Cortex-A9 processor CPU2 tag RAM size if present.
Appendix B: Register Details Register (mpcore) SCU_CPU_Power_Status_Register Name SCU_CPU_Power_Status_Register Relative Address 0x00000008 Absolute Address 0xF8F00008 Width 32 bits Access Type rw Reset Value 0x00000000 Description SCU CPU Power Status Register Register SCU_CPU_Power_Status_Register Details Field Name Bits Type Reset Value Description reserved 31:26 rw 0x0 Should Be Zero (SBZ) CPU3_status 25:24 rw 0x0 Power status of the Cortex-A9 processor: b00: Normal mode.
Appendix B: Description Register Details SCU Invalidate All Registers in Secure State Register SCU_Invalidate_All_Registers_in_Secure_State Details Field Name Bits Type Reset Value Description NA 31:16 wo 0x0 NA CPU3_ways 15:12 wo 0x0 Specifies the ways that must be invalidated for CPU3. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than four processors. CPU2_ways 11:8 wo 0x0 Specifies the ways that must be invalidated for CPU2.
Appendix B: Register Details Register (mpcore) Filtering_End_Address_Register Name Filtering_End_Address_Register Relative Address 0x00000044 Absolute Address 0xF8F00044 Width 32 bits Access Type rw Reset Value 0x00000000 Description Defined by FILTEREND input Register Filtering_End_Address_Register Details Field Name Bits Filtering_end_address 31:20 Type rw Reset Value 0x0 Description End address for use with master port 1 in a two-master port configuration, when address filtering is
Appendix B: Field Name Bits CPU2 2 Type rw Reset Value 0x1 Register Details Description 0 = CPU2 cannot access the components. 1 = CPU2 can access the components. This is the default. CPU1 1 rw 0x1 0 = CPU1 cannot access the components. 1 = CPU1 can access the components. This is the default. CPU0 0 rw 0x1 0 = CPU0 cannot access the components. 1 = CPU0 can access the components. This is the default.
Appendix B: Field Name Bits Type Reset Value Register Details Description Private_timers_for_CP U1 5 ro 0x0 same as above Private_timers_for_CP U0 4 ro 0x0 Non-secure access to the private timer and watchdog for CPU. * is 3 for bit[7] * is 2 for bit[6]] * is 1 for bit[5] * is 0 for bit[4]. 0 = Secure accesses only. Non-secure reads return 0. This is the default value. 1 = Secure accesses and Non-secure accesses.
Appendix B: Register Details Register ICCICR Details Field Name Bits Type Reset Value Description reserved 31:5 rw 0x0 reserved SBPR 4 rw 0x0 Controls whether the CPU interface uses the Secure or Non-secure Binary Point Register for preemption. (GIC_CNTR_SBPR) 0: use the Secure Binary Point Register for Secure interrupts, and use the Non-secure Binary Point Register for Non-secure interrupts. 1: use the Secure Binary Point Register for both Secure and Non-secure interrupts.
Appendix B: Register Details Register ICCPMR Details Field Name Bits Type Reset Value Description reserved 31:8 rw 0x0 reserved Priority 7:0 rw 0x0 The priority mask level for the CPU interface. (GIC_PRIORITY) If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor.
Appendix B: Register Details Register ICCIAR Details Field Name Bits Type Reset Value Description reserved 31:13 rw 0x0 reserved CPUID 12:10 rw 0x0 Identifies the processor that requested the interrupt. Returns the number of the CPU interface that made the request. ACKINTID 9:0 rw 0x3FF The interrupt ID. (GIC_ACK_INTID) This read acts as an acknowledge for the interrupt.
Appendix B: Access Type rw Reset Value 0x000000FF Description Running Priority Register Register Details Register ICCRPR Details Field Name Bits Type Reset Value Description reserved 31:8 rw 0x0 reserved Priority 7:0 rw 0xFF The priority value of the highest priority interrupt that is active on the CPU interface.
Appendix B: Absolute Address 0xF8F0011C Width 32 bits Access Type rw Reset Value 0x00000003 Description Aliased Non-secure Binary Point Register Register Details Register ICCABPR Details Field Name Bits Type Reset Value Description reserved 31:3 rw 0x0 reserved Binary_point 2:0 rw 0x3 Provides an alias of the Non-secure ICCBPR.
Appendix B: Register Details Register (mpcore) Global_Timer_Counter_Register0 Name Global_Timer_Counter_Register0 Relative Address 0x00000200 Absolute Address 0xF8F00200 Width 32 bits Access Type rw Reset Value 0x00000000 Description Global Timer Counter Register 0 Note: This register is the first in an array of 2 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Register (mpcore) Global_Timer_Control_Register Name Global_Timer_Control_Register Relative Address 0x00000208 Absolute Address 0xF8F00208 Width 32 bits Access Type rw Reset Value 0x00000000 Description Global Timer Control Register Register Global_Timer_Control_Register Details Field Name Bits Type Reset Value Description reserved 31:16 rw 0x0 Reserved Prescaler 15:8 rw 0x0 The prescaler modifies the clock period for the decrementing event for the
Appendix B: Field Name Comp_Enablea Bits 1 Type rw Reset Value 0x0 Register Details Description This bit is banked per Cortex-A9 processor. If set, it allows the comparison between the 64-bit Timer Counter and the related 64-bit Comparator Register. Timer_Enable 0 rw 0x0 Timer enable 1'b0 = Timer is disabled and the counter does not increment.
Appendix B: Absolute Address 0xF8F00210 Width 32 bits Access Type rw Reset Value 0x00000000 Description Comparator Value Register_0 Register Details Note: This register is the first in an array of 2 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Access Type rw Reset Value 0x00000000 Description Auto-increment Register Register Details Register Auto_increment_Register Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Auto-increment Register This 32-bit register gives the increment value of the Comparator Register when the Auto-increment bit is set in the Timer Control Register.
Appendix B: Register Details Register (mpcore) Private_Timer_Counter_Register Name Private_Timer_Counter_Register Software Name TIMER_COUNTER Relative Address 0x00000604 Absolute Address 0xF8F00604 Width 32 bits Access Type rw Reset Value 0x00000000 Description Private Timer Counter Register Register Private_Timer_Counter_Register Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description The Timer Counter Register is a decrementing counter.
Appendix B: Relative Address 0x00000608 Absolute Address 0xF8F00608 Width 32 bits Access Type rw Reset Value 0x00000000 Description Private Timer Control Register Register Details Register Private_Timer_Control_Register Details Field Name Bits Type Reset Value Description SBZP 31:16 rw 0x0 UNK/SBZP. Prescaler 15:8 rw 0x0 The prescaler modifies the clock period for the decrementing event for the Counter (PRESCALER) Register.
Appendix B: Reset Value 0x00000000 Description Private Timer Interrupt Status Register Register Details Register Private_Timer_Interrupt_Status_Register Details Field Name UNK_SBZP Bits Type Reset Value Description 31:1 rw 0x0 UNK/SBZP 0 rw 0x0 This is a banked register for all Cortex-A9 processors present. The event flag is a sticky bit that is automatically set when the Counter Register reaches zero.
Appendix B: Software Name WDT_COUNTER Relative Address 0x00000624 Absolute Address 0xF8F00624 Width 32 bits Access Type rw Reset Value 0x00000000 Description Watchdog Counter Register Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 www.xilinx.
Appendix B: Register Details Register Watchdog_Counter_Register Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Watchdog Counter Register The Watchdog Counter Register is a down counter. It decrements if the Watchdog is enabled using the Watchdog enable bit in the Watchdog Control Register. If the Cortex-A9 processor associated with the Watchdog is in debug state, the counter does not decrement until the Cortex-A9 processor returns to non debug state.
Appendix B: Register Details Register (mpcore) Watchdog_Control_Register Name Watchdog_Control_Register Software Name WDT_CONTROL Relative Address 0x00000628 Absolute Address 0xF8F00628 Width 32 bits Access Type rw Reset Value 0x00000000 Description Watchdog Control Register Register Watchdog_Control_Register Details Field Name Bits Type Reset Value Description reserved 31:16 rw 0x0 Reserved.
Appendix B: Register Details Register (mpcore) Watchdog_Interrupt_Status_Register Name Watchdog_Interrupt_Status_Register Software Name WDT_ISR Relative Address 0x0000062C Absolute Address 0xF8F0062C Width 32 bits Access Type rw Reset Value 0x00000000 Description Watchdog Interrupt Status Register Register Watchdog_Interrupt_Status_Register Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved Event_flag 0 rw 0x0 The event flag is a sticky bit tha
Appendix B: Register Details Register Watchdog_Reset_Status_Register Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is always zero. Reset_flag 0 rw 0x0 The reset flag is a sticky bit that is automatically set when the Counter Register reaches (RESET_FLAG) zero and a reset request is sent accordingly. (In watchdog mode) The reset flag is cleared when written with a value of 1.
Appendix B: Register Details Register Watchdog_Disable_Register Details Field Name Bits 31:0 Type rw Reset Value 0x0 Description Watchdog Disable Register Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.
Appendix B: Field Name Bits Enable_Non_secure 1 Type rw Reset Value 0x0 Register Details Description 0 = disables all Non-secure interrupts control bits in the distributor from changing state because of any external stimulus change that occurs on the corresponding SPI or PPI signals 1 = enables the distributor to update register locations for Non-secure interrupts FOR: ICDDCR_for_Non_secure_mode 31,1 --> Reserved. Writes are ignored, read data is always zero.
Appendix B: Register Details Register ICDICTR Details Field Name Bits Type Reset Value Description reserved 31:29 ro 0x0 Reserved. Writes are ignored, read data is always zero. LSPI 15:11 ro 0x1F Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the controller (GIC_LSPI) contains. The encoding is: b11111 = 31 LSPIs, which are the interrupts of IDs 32-62.
Appendix B: Register Details Register (mpcore) ICDIIDR Name ICDIIDR Software Name GIC_DIST_IDENT Relative Address 0x00001008 Absolute Address 0xF8F01008 Width 32 bits Access Type ro Reset Value 0x0102043B Description Distributor Implementer Identification Register Register ICDIIDR Details Field Name Bits Type Reset Value Description Implementation_Versio 31:24 n ro 0x1 Gives implementation version number Revision_Number 23:12 ro 0x20 Return the revision number of the controlle
Appendix B: Register Details Register ICDISR0 to ICDISR2 Details Field Name Security_Status Bits 31:0 Type rw Reset Value 0x0 Description The ICDISRn provide a Security status bit for each interrupt supported by the GIC. (GIC_INT_NS) Each bit controls the security status of the corresponding interrupt. Accessible by Secure accesses only. The register addresses are RAZ/WI to Non-secure accesses. ICDISR0 is banked for each connected processor.
Appendix B: Reset Value 0x00000000 Description Interrupt Set-enable Register 1 Register Details Register ICDISER1 Details Field Name Set Bits 31:0 Type rw Reset Value 0x0 Description The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC. Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access.
Appendix B: Reset Value 0x0000FFFF Description Interrupt Clear-Enable Register 0 Register Details Register ICDICER0 Details Field Name Clear Bits 31:0 Type rw Reset Value 0xFFFF Description The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC. (GIC_INT_CLR) Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
Appendix B: Access Type rw Reset Value 0x00000000 Description Interrupt Clear-Enable Register 2 Register Details Register ICDICER2 Details Field Name Clear Bits 31:0 Type rw Reset Value 0x0 Description The ICDICERs provide a Clear-enable bit for each interrupt supported by the GIC. Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
Appendix B: Register Details Register ICDISPR0 to ICDISPR2 Details Field Name Bits Set 31:0 Type rw Reset Value 0x0 Description The ICDISPRs provide a Set-pending bit for each interrupt supported by the GIC. (GIC_PEND_SET) Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses. ICDISPR0 is banked for each connected processor.
Appendix B: Register Details Register (mpcore) ICDABR0 Name ICDABR0 Software Name GIC_ACTIVE0 Relative Address 0x00001300 Absolute Address 0xF8F01300 Width 32 bits Access Type rw Reset Value 0x00000000 Description Active Bit register_0 Note: This register is the first in an array of 3 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Note: This register is the first in an array of 24 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Register ICDIPR0 to ICDIPR23 Details Field Name Priority Bits 31:0 Type rw Reset Value 0x0 Description The ICDIPRs provide an 8-bit Priority field for each interrupt supported by the GIC; however, Zynq implemented only the upper 7 bits of each 8-bit field, i.e. supporing 128 levels, all even values. These registers are byte accessible. (MASK) A register field that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses.
Appendix B: Field Name target_1 Bits 9:8 Type ro Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#1 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) target_0 1:0 ro 0x0 Targeted CPU(s) for interrupt ID#0 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) Register (mpcore) ICDIPTR1 Name ICDIPTR1 Software Name GIC_SPI_TARGET Rela
Appendix B: Field Name target_5 Bits 9:8 Type ro Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#5 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) target_4 1:0 ro 0x0 Targeted CPU(s) for interrupt ID#4 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) Register (mpcore) ICDIPTR2 Name ICDIPTR2 Software Name GIC_SPI_TARGET Rela
Appendix B: Field Name target_9 Bits 9:8 Type ro Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#9 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) target_8 1:0 ro 0x0 Targeted CPU(s) for interrupt ID#8 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) Register (mpcore) ICDIPTR3 Name ICDIPTR3 Software Name GIC_SPI_TARGET Rela
Appendix B: Field Name target_13 Bits 9:8 Type ro Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#13 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) target_12 1:0 ro 0x0 Targeted CPU(s) for interrupt ID#12 (GIC_SPI_CPUn) 01: CPU 0 targeted (CPU 0 always reads this value) 10: CPU 1 targeted (CPU 1 always reads this value) Register (mpcore) ICDIPTR4 Name ICDIPTR4 Software Name GIC_SPI_TARGET
Appendix B: Register Details Register ICDIPTR5 Details The ICDIPTR5 register always returns 0.
Appendix B: Field Name target_31 Bits 25:24 Type ro Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#31 (GIC_SPI_CPUn) 01: CPU 0 targeted 10: CPU 1 targeted target_30 17:16 ro 0x0 Targeted CPU(s) for interrupt ID#30 (GIC_SPI_CPUn) 01: CPU 0 targeted 10: CPU 1 targeted target_29 9:8 ro 0x0 Targeted CPU(s) for interrupt ID#29 (GIC_SPI_CPUn) 01: CPU 0 targeted 10: CPU 1 targeted target_28 1:0 ro 0x0 Targeted CPU(s) for interrupt ID#28 (GIC_SPI_CPUn) 01:
Appendix B: Field Name target_33 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#33 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_32 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#32 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR9 Name ICDIPTR9 Software Name GIC_SPI_TARGET Relative Add
Appendix B: Field Name target_37 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#37 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_36 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#36 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR10 Name ICDIPTR10 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_41 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#41 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_40 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#40 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR11 Name ICDIPTR11 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_45 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#45 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_44 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#44 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR12 Name ICDIPTR12 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_49 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#49 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_48 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#48 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR13 Name ICDIPTR13 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_53 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#53 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_52 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#52 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR14 Name ICDIPTR14 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_57 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#57 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_56 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#56 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR15 Name ICDIPTR15 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_61 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#61 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_60 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#60 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR16 Name ICDIPTR16 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_65 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#65 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_64 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#64 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR17 Name ICDIPTR17 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_69 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#69 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_68 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#68 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR18 Name ICDIPTR18 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_73 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#73 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_72 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#72 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR19 Name ICDIPTR19 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_77 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#77 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_76 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#76 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR20 Name ICDIPTR20 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_81 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#81 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_80 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#80 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR21 Name ICDIPTR21 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_85 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#85 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_84 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#84 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR22 Name ICDIPTR22 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_89 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#89 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_88 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#88 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDIPTR23 Name ICDIPTR23 Software Name GIC_SPI_TARGET Relative A
Appendix B: Field Name target_93 Bits 9:8 Type rw Reset Value 0x0 Register Details Description Targeted CPU(s) for interrupt ID#93 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted target_92 1:0 rw 0x0 Targeted CPU(s) for interrupt ID#92 (GIC_SPI_CPUn) 00: no CPU targeted 01: CPU 0 targeted 10: CPU 1 targeted 11: CPU 0 and CPU 1 are both targeted Register (mpcore) ICDICFR0 Name ICDICFR0 Software Name GIC_INT_CFG Relative Addres
Appendix B: Field Name config_12 Bits 25:24 Type ro Reset Value 0x0 (MASK) config_11 23:22 ro 0x0 21:20 ro 0x0 19:18 ro 0x0 17:16 ro 0x0 15:14 ro 0x0 13:12 ro 0x0 11:10 ro 0x0 9:8 ro 0x0 7:6 ro 0x0 5:4 ro 0x0 Configuration for interrupt ID#3 Configuration for interrupt ID#2 10: edge sensitive and must be handeled by the targeted CPU(s). 3:2 ro 0x0 (MASK) config_0 Configuration for interrupt ID#4 10: edge sensitive and must be handeled by the targeted CPU(s).
Appendix B: Register Details Register (mpcore) ICDICFR1 Name ICDICFR1 Relative Address 0x00001C04 Absolute Address 0xF8F01C04 Width 32 bits Access Type rw Reset Value 0x00000000 Description Interrupt Configuration Register 1 Register ICDICFR1 Details The ICD ICFR 1 register controls the interrupt sensitivity of the CPU Private Peripheral Interrupts (PPI), IRQ ID #27 to ID #31. This read-only register has two bits per interrupt.
Appendix B: Reset Value 0x00000000 Description Interrupt Configuration Register 2 Register Details Register ICDICFR2 Details The ICDICFR 2 register control the interrupt sensitivity of the Shared Peripheral Interrupts (SPI), IRQ ID #32 to ID #47 (IRQ 36 is reserved). This register has two bits per interrupt. This two bit field is either equal to 01 (high-level active) or equal to 11 (rising-edge sensitive).
Appendix B: Field Name config_40 Bits 17:16 Type rw Reset Value 0x0 Register Details Description Configuration for interrupt ID#40 (GIC_INT_CFG) 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. config_39 15:14 rw 0x0 Configuration for interrupt ID#39 (GIC_INT_CFG) 01: high-level active 11: rising-edge The lower bit is read-only and is always 1.
Appendix B: Relative Address 0x00001C0C Absolute Address 0xF8F01C0C Width 32 bits Access Type rw Reset Value 0x00000000 Description Interrupt Configuration Register 3 Register Details Register ICDICFR3 Details The ICDICFR 3 register control the interrupt sensitivity of the Shared Peripheral Interrupts (SPI), IRQ ID #48 to ID #63. This register has two bits per interrupt. This two bit field is either equal to 01 (high-level active) or equal to 11 (rising-edge sensitive).
Appendix B: Field Name config_57 Bits 19:18 Type rw Reset Value 0x0 (GIC_INT_CFG) Register Details Description Configuration for interrupt ID#57 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. config_56 17:16 rw 0x0 (GIC_INT_CFG) Configuration for interrupt ID#56 01: high-level active 11: rising-edge The lower bit is read-only and is always 1.
Appendix B: Register Details Register (mpcore) ICDICFR4 Name ICDICFR4 Relative Address 0x00001C10 Absolute Address 0xF8F01C10 Width 32 bits Access Type rw Reset Value 0x00000000 Description Interrupt Configuration Register 4 Register ICDICFR4 Details The ICDICFR 4 register control the interrupt sensitivity of the Shared Peripheral Interrupts (SPI), IRQ ID #64 to ID #79. This register has two bits per interrupt.
Appendix B: Field Name config_74 Bits 21:20 Type rw Reset Value 0x0 (GIC_INT_CFG) Register Details Description Configuration for interrupt ID#74 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. config_73 19:18 rw 0x0 (GIC_INT_CFG) Configuration for interrupt ID#73 01: high-level active 11: rising-edge The lower bit is read-only and is always 1.
Appendix B: Field Name config_65 Bits 3:2 Type rw Reset Value 0x0 Register Details Description Configuration for interrupt ID#65 (GIC_INT_CFG) 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. config_64 1:0 rw 0x0 Configuration for interrupt ID#64 (GIC_INT_CFG) 01: high-level active 11: rising-edge The lower bit is read-only and is always 1.
Appendix B: Field Name config_93 Bits 27:26 Type rw Reset Value 0x0 (GIC_INT_CFG) Register Details Description Configuration for interrupt ID#93 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. config_92 25:24 rw 0x0 (GIC_INT_CFG) Configuration for interrupt ID#92 01: high-level active 11: rising-edge The lower bit is read-only and is always 1.
Appendix B: Field Name config_83 Bits 7:6 Type rw Reset Value 0x0 Register Details Description Configuration for interrupt ID#83 (GIC_INT_CFG) 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. config_82 5:4 rw 0x0 Configuration for interrupt ID#82 (GIC_INT_CFG) 01: high-level active 11: rising-edge The lower bit is read-only and is always 1.
Appendix B: Register Details Register ppi_status Details Field Name Bits Type Reset Value Description reserved 31:16 ro 0x0 Reserved. Writes are ignored, read data is always zero ppi_status 15:11 ro 0x0 Returns the status of the PPI(4:0) inputs on the distributor: * PPI[4] is nIRQ * PPI[3] is the private watchdog * PPI[2] is the private timer * PPI[1] is nFIQ * PPI[0] is the global timer. PPI[1] and PPI[4] are active LOW PPI[0], PPI[2] and PPI[3] are active HIGH.
Appendix B: Register Details Register (mpcore) spi_status_1 Name spi_status_1 Relative Address 0x00001D08 Absolute Address 0xF8F01D08 Width 32 bits Access Type ro Reset Value 0x00000000 Description SPI Status Register 1 Register spi_status_1 Details Field Name spi_status Bits 31:0 Type ro Reset Value 0x0 Description Returns the status of the IRQ ID64 to ID95 inputs on the distributor. These bits return the actual status of the IRQ signals.
Appendix B: Register Details Register ICDSGIR Details Field Name Bits Type Reset Value Description reserved 31:26 rw 0x0 reserved TargetListFilter 25:24 rw 0x0 0b00: send the interrupt to the CPU interfaces specified in the CPUTargetList field (TRGFILT) 0b01: send the interrupt to all CPU interfaces except the CPU interface that requested the interrupt 0b10: send the interrupt on only to the CPU interface that requested the interrupt 0b11: reserved CPUTargetList 23:16 rw 0x0 When Targe
Appendix B: Register Details Register ICPIDR4 Details Field Name Bits Type Reset Value Description reserved 31:4 rw 0x0 reserved ContinuationCode 3:0 rw 0x4 ARM-defined ContinuationCode field Register (mpcore) ICPIDR5 Name ICPIDR5 Relative Address 0x00001FD4 Absolute Address 0xF8F01FD4 Width 32 bits Access Type rw Reset Value 0x00000000 Description Peripheral ID5 Register ICPIDR5 Details Field Name reserved Bits 31:0 Type rw Reset Value 0x0 Description Reserved Register (
Appendix B: Relative Address 0x00001FDC Absolute Address 0xF8F01FDC Width 32 bits Access Type rw Reset Value 0x00000000 Description Peripheral ID7 Register Details Register ICPIDR7 Details Field Name reserved Bits 31:0 Type rw Reset Value 0x0 Description Reserved Register (mpcore) ICPIDR0 Name ICPIDR0 Relative Address 0x00001FE0 Absolute Address 0xF8F01FE0 Width 32 bits Access Type rw Reset Value 0x00000090 Description Peripheral ID0 Register ICPIDR0 Details Field Name Bits
Appendix B: Register Details Register ICPIDR1 Details Field Name Bits Type Reset Value Description reserved 31:8 rw 0x0 reserved ARchID_low 7:4 rw 0xB ARM-defined ArchID[3:0] field DevID_high 3:0 rw 0x3 ARM-defined DevID[11:8] field Register (mpcore) ICPIDR2 Name ICPIDR2 Relative Address 0x00001FE8 Absolute Address 0xF8F01FE8 Width 32 bits Access Type rw Reset Value 0x0000001B Description Peripheral ID2 Register ICPIDR2 Details Field Name Bits Type Reset Value Descrip
Appendix B: Register Details Register ICPIDR3 Details Field Name Bits Type Reset Value Description reserved 31:8 rw 0x0 reserved Revision 7:4 rw 0x0 ARM-defined Revision field reserved 3:0 rw 0x0 reserved Register (mpcore) ICCIDR0 Name ICCIDR0 Software Name GIC_PCELLID Relative Address 0x00001FF0 Absolute Address 0xF8F01FF0 Width 32 bits Access Type rw Reset Value 0x0000000D Description Component ID0 Register ICCIDR0 Details Field Name Bits 31:0 Type rw Reset Value 0
Appendix B: Register Details Register (mpcore) ICCIDR2 Name ICCIDR2 Relative Address 0x00001FF8 Absolute Address 0xF8F01FF8 Width 32 bits Access Type rw Reset Value 0x00000005 Description Component ID2 Register ICCIDR2 Details Field Name Bits 31:0 Type rw Reset Value 0x5 Description ARM-defined fixed values for the preamble for component discovery Register (mpcore) ICCIDR3 Name ICCIDR3 Relative Address 0x00001FFC Absolute Address 0xF8F01FFC Width 32 bits Access Type rw Reset V
Appendix B: Register Details B.25 On-Chip Memory (ocm) Module Name On-Chip Memory (ocm) Base Address 0xF800C000 ocm Description On-Chip Memory Registers Vendor Info Xilinx Register Summary Register Name Address Width Type Reset Value Description OCM_PARITY_CTRL 0x00000000 32 mixed 0x00000000 Control fields for RAM parity operation OCM_PARITY_ERRA DDRESS 0x00000004 32 mixed 0x00000000 Stores the first parity error access address.
Appendix B: Register Details Register OCM_PARITY_CTRL Details Field Name Bits Type Reset Value Description reserved 31:21 ro 0x0 Returns 0 when read OddParityEn 20:5 rw 0x0 Enable RAM Odd Parity Generation. The default computed parity is even but this can be changed to odd parity via this APB register field. Note that, on reads, parity is always computed as even parity. The odd parity generation option is useful for verification purposes, enabling parity errors to be injected.
Appendix B: Register Details Register (ocm) OCM_PARITY_ERRADDRESS Name OCM_PARITY_ERRADDRESS Relative Address 0x00000004 Absolute Address 0xF800C004 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Stores the first parity error access address. This register is sticky and will retain its value unless explicitly cleared (written with 1's) with an APB write access. The physical RAM address is logged.
Appendix B: Field Name Bits MultipleParityErr 1 Type wtc Reset Value 0x0 Register Details Description Status of OCM multiple parity error. This is a sticky bit. Once set it can only be cleared by explicitly writing a 1 to this field. This field drives the interrupt pin. (Associated irq enable bit must be set) 0: Multiple OCM parity Errors have not occurred 1: Multiple OCM parity Errors have occurred SingleParityErr 0 wtc 0x0 Status of OCM single parity error. This is a sticky bit.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description TXD3 0x00000088 32 wo 0x00000000 Transmit Data Register. Keyhole addresses for the Transmit data FIFO.
Appendix B: Field Name endian Bits 26 Type rw Reset Value 0x0 (ENDIAN) Register Details Description 0 for little endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20. 1 for big endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20. reserved 25:20 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Field Name Bits BAUD_RATE_DIV 5:3 Type rw Reset Value 0x0 Register Details Description Master mode baud rate divisor 000: divide by 2. This is the only baud rate setting that can be used if the loopback clock is enabled (USE_LPBK). This setting also works in non-loopback mode.
Appendix B: Register Details Register Intr_status_REG Details This register is set when the described event occurs. Interrupt mask value does not affect interrupt status register. Mask value is only used to mask interrupt output. Bit 0 and 6 are write to clear. All other bits are read only. Field Name Bits Type Reset Value Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write. TX_FIFO_underflow 6 wtc 0x0 TX FIFO underflow, write one to this bit location to clear.
Appendix B: Reset Value 0x00000000 Description Interrupt Enable register. Register Details Register Intrpt_en_REG Details Writing a 1 to this register sets the corresponding bits of the interrupt mask register. Field Name Bits Type Reset Value Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Access Type mixed Reset Value 0x00000000 Description Interrupt disable register. Register Details Register Intrpt_dis_REG Details Field Name Bits Type Reset Value Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Access Type ro Reset Value 0x00000000 Description Interrupt mask register Register Details Register Intrpt_mask_REG Details Field Name Bits Type Reset Value Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Access Type mixed Reset Value 0x00000000 Description SPI_Enable Register Register Details Register En_REG Details Field Name Bits Type Reset Value Description reserved 31:1 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Register Details Register (qspi) TXD0 Name TXD0 Software Name TXD_00 Relative Address 0x0000001C Absolute Address 0xE000D01C Width 32 bits Access Type wo Reset Value 0x00000000 Description Transmit Data Register. Keyhole addresses for the Transmit data FIFO. See also TXD1-3. Register TXD0 Details Field Name TXD Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO, for 4-byte instruction for normal read/write data transfer.
Appendix B: Width 32 bits Access Type mixed Reset Value 0x000000FF Description Slave Idle Count Register Register Details Register Slave_Idle_count_REG Details Field Name Bits Type Reset Value Description reserved 31:8 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Reset Value 0x00000001 Description RX FIFO Threshold Register Register Details Register RX_thres_REG Details Field Name Bits Threshold_of_RX_FIF O 31:0 Type rw Reset Value 0x1 Description Defines the level at which the RX FIFO not empty interrupt is generated Register (qspi) GPIO Name GPIO Relative Address 0x00000030 Absolute Address 0xE000D030 Width 32 bits Access Type rw Reset Value 0x00000001 Description General Purpose Inputs and Outputs Register for the Quad-SPI Co
Appendix B: Register Details Register LPBK_DLY_ADJ Details Register for adjusting the internal loopback clock delay for read data capturing. This feature is only active if bit 5 is set AND if the baud rate divisor in reg 0x00 is programmed to 2 (i.e., 000). Field Name Bits Type Reset Value Description reserved 31:9 rw 0x0 Reserved.
Appendix B: Absolute Address 0xE000D084 Width 32 bits Access Type wo Reset Value 0x00000000 Description Transmit Data Register. Keyhole addresses for the Transmit data FIFO. Register Details Register TXD2 Details Field Name TXD Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO, for 2-byte instruction, not for normal data transfer. In little endian mode (default), only bits 15:0 are valid, bits 31:16 are ignored. In big endian mode, only the 16 MS bits are valid.
Appendix B: Absolute Address 0xE000D0A0 Width 32 bits Access Type rw Reset Value x Description Configuration Register specifically for the Linear Quad-SPI Controller Register Details Register LQSPI_CFG Details Field Name LQ_MODE Bits Type Reset Value Description 31 rw 0x0 Linear quad SPI mode, if set, else quad SPI mode TWO_MEM 30 rw 0x0 Both upper and lower memories are active, if set SEP_BUS 29 rw 0x0 Separate memory bus, if set.
Appendix B: Field Name MODE_ON Bits 24 Type rw Reset Value 0x1 Register Details Description This bit is only relevant if bit 25 is set, else it is ignored. If this bit is set, instruction code is only sent for the very first read transfer. If this bit is clear, instruction code will be sent for all read transfers. This bit is configured in association with the MODE_BITS. For Winbond devices, this bit MUST BE SET if the MODE_BITS are 8'bxx10xxxx, else this bit MUST BE CLEAR.
Appendix B: Reset Value 0x00000000 Description Status Register specifically for the Linear Quad-SPI Controller Register Details Register LQSPI_STS Details Field Name Bits Type Reset Value Description reserved 8:3 rw 0x0 Reserved D_FSM_ERR 2 rw 0x0 Data FSM error, if set WR_RECVD 1 rw 0x0 AXI write command received, if set reserved 0 rw 0x0 Reserved (FB_RECVD) Register (qspi) MOD_ID Name MOD_ID Relative Address 0x000000FC Absolute Address 0xE000D0FC Width 32 bits Acces
Appendix B: Register Details B.27 SD Controller (sdio) Module Name SD Controller (sdio) Base Address 0xE0100000 sd0 0xE0101000 sd1 Description SD2.0/ SDIO2.0/ MMC3.
Appendix B: Register Name Address Width Type 30 mixed Reset Value 0x00000000 Register Details Description Normal_interrupt_sign al_enable_Error_interr upt_signal_enable 0x00000038 Normal interrupt signal enable register Auto_CMD12_error_st atus 0x0000003C 8 ro 0x00000000 Auto CMD12 error status register Capabilities 0x00000040 31 ro 0x69EC0080 Capabilities register Maximum_current_cap 0x00000048 abilities 24 ro 0x00000001 Maximum current capabilities register 0x00000050 Force_e
Appendix B: Register Details Buffer Size in the Block Size register. The Host Controller generates DMA Interrupt to request to update this register. The HD sets the next system address of the next data position to this register. When most upper byte of this register (003h) is written, the HC restart the DMA transfer.
Appendix B: Register Details Register Block_Size_Block_Count Details Field Name Blocks_Count_for_Cur rent_Transfer Bits 31:16 Type rw Reset Value 0x0 Description This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be accessed only if no transaction is executing (i.e. after a transaction has stopped).
Appendix B: Field Name Bits Host_SDMA_Buffer_Si ze 14:12 Type rw Reset Value 0x0 Register Details Description To perform long DMA transfer, the System Address register shall be updated at every system boundary during a DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at every boundary specified by these fields and the HC generates the DMA Interrupt to request the HD to update the System Address register.
Appendix B: Width 32 bits Access Type rw Reset Value 0x00000000 Description Argument register Register Details Register Argument Details Field Name Bits Command_Argument 31:0 Type rw Reset Value 0x0 Description The SD Command Argument is specified as bit 39-8 of Command-Format.
Appendix B: Field Name Command_Type Bits 23:22 Type rw Reset Value 0x0 Register Details Description There are three types of special commands. Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions.
Appendix B: Field Name Command_CRC_Chec k_Enable Bits 19 Type rw Reset Value 0x0 Register Details Description If this bit is set to 1, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.
Appendix B: Register Details Register (sdio) Response0 Name Response0 Relative Address 0x00000010 Absolute Address sd0: 0xE0100010 sd1: 0xE0101010 Width 32 bits Access Type ro Reset Value 0x00000000 Description Response register Note: This register is the first in an array of 4 identical registers listed in the table below. The details provided in this section apply to the entire array.
Appendix B: Register Details Register (sdio) Present_State Name Present_State Relative Address 0x00000024 Absolute Address sd0: 0xE0100024 sd1: 0xE0101024 Width 25 bits Access Type ro Reset Value 0x01F20000 Description Present State register Register Present_State Details Field Name CMD_Line_Signal_Lev el Bits 24 DAT_Bit3_Bit0_Line_Si 23:20 gnal_Level Type Reset Value Description ro 0x1 This status is used to check CMD line level to recover from errors, and for debugging.
Appendix B: Field Name Card_Inserted Bits 16 Type ro Reset Value 0x0 Register Details Description This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit.
Appendix B: Field Name Read_Transfer_Active Bits 9 Type ro Reset Value 0x0 Register Details Description This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: 1. After the end bit of the read command 2. When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer This bit is cleared to 0 for either of the following conditions: 1.
Appendix B: Field Name Bits Command_Inhibit_DA T 1 Type ro Reset Value 0x0 Register Details Description This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register.
Appendix B: Description Register Details Host control register Power control register Block gap control register Wake-up control register Register Host_control_Power_control_Block_Gap_Control_Wakeup_control Details Field Name Bits Type Reset Value Description reserved 31:27 ro 0x0 Reserved Wakeup_Event_Enable _On_SD_Card_Remov al 26 rw 0x0 This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register.
Appendix B: Field Name Read_Wait_Control Bits 18 Type rw Reset Value 0x0 Register Details Description The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card.
Appendix B: Field Name Stop_At_Block_Gap_R equest Bits 16 Type rw Reset Value 0x0 Register Details Description This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set to 1, indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap.
Appendix B: Field Name Bits Card_Detect_Test_Leve 6 l Type rw Reset Value 0x0 Register Details Description This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set. 1 - Card Inserted 0 - No Card reserved 5 ro 0x0 Reserved DMA_Select 4:3 rw 0x0 One of supported DMA modes can be selected.
Appendix B: Absolute Address Register Details sd0: 0xE010002C sd1: 0xE010102C Width 27 bits Access Type mixed Reset Value 0x00000000 Description Clock Control register Timeout control register Software reset register Register Clock_Control_Timeout_control_Software_reset Details Field Name Software_Reset_for_D AT_Line Bits 26 Type rw Reset Value 0x0 Description Only part of data circuit is reset.
Appendix B: Field Name Bits Software_Reset_for_All 24 Type rw Reset Value 0x0 Register Details Description This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read them.
Appendix B: Field Name SDCLK_Frequency_Sel ect Bits 15:8 Type rw Reset Value 0x0 Register Details Description This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed.
Appendix B: Field Name Bits Internal_Clock_Stable 1 Type ro Reset Value 0x0 Register Details Description This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock oscillator that requires setup time.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 27:26 ro 0x0 Reserved ADMA_Error 25 wtc 0x0 This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register. 1- Error 0 -No error Auto_CMD12_Error 24 wtc 0x0 Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1.
Appendix B: Field Name Command_Index_Erro r Bits 19 Type wtc Reset Value 0x0 Register Details Description Occurs if a Command Index error occurs in the Command Response. 0 - No Error 1 - Error Command_End_Bit_Er ror 18 wtc 0x0 Occurs when detecting that the end bit of a command response is 0. 0 - No Error 1 - End Bit Error Generated Command_CRC_Error 17 wtc 0x0 Command CRC Error is generated in two cases. 1.
Appendix B: Field Name Card_Interrupt Bits 8 Type ro Reset Value 0x0 Register Details Description Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system.
Appendix B: Field Name Buffer_Write_Ready Bits 4 Type wtc Reset Value 0x0 Register Details Description This status is set if the Buffer Write Enable changes from 0 to 1. 0 - Not Ready to Write Buffer. 1 - Ready to Write Buffer. DMA_Interrupt 3 wtc 0x0 This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size register.
Appendix B: Field Name Bits Transfer_Complete 1 Type wtc Reset Value 0x0 Register Details Description This bit is set when a read / write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host System).
Appendix B: Absolute Address Register Details sd0: 0xE0100034 sd1: 0xE0101034 Width 30 bits Access Type mixed Reset Value 0x00000000 Description Normal interrupt status enable register Error interrupt status enable register Register Normal_interrupt_status_enable_Error_interrupt_status_enable Details Field Name Ceata_Error_Status_En able Bits 29 Type rw Reset Value 0x0 Description 0 - Masked 1 - Enabled Target_Response_Error 28 _Status_Enable rw reserved ro 0x0 Reserved ADMA_Error_Sta
Appendix B: Field Name Bits Type Boot_terminate_Interru 10 pt_enable rw Boot_ack_rcv_enable rw 9 Reset Value 0x0 Register Details Description 0 - Masked 1 - Enabled 0x0 0 - Masked 1 - Enabled Card_Interrupt_Status _Enable 8 rw 0x0 If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1.
Appendix B: Reset Value 0x00000000 Description Normal interrupt signal enable register Register Details Error interrupt signal enable register Register Normal_interrupt_signal_enable_Error_interrupt_signal_enable Details Field Name Ceata_Error_Signal_En able Bits 29 Type rw Reset Value 0x0 Description 0 - Masked 1 - Enabled Target_Response_Error 28 _Signal_Enable rw 0x0 0 - Masked reserved 27:26 ro 0x0 Reserved ADMA_Error_Signal_ Enable 25 rw 0x0 0 - Masked Auto_CMD12_Error_Si gnal
Appendix B: Field Name Bits Card_Interrupt_Signal _Enable 8 Type rw Reset Value 0x0 Register Details Description 0 - Masked 1 - Enabled Card_Removal_Signal_ 7 Enable rw Card_Insertion_Signal_ 6 Enable rw Buffer_Read_Ready_Si gnal_Enable 5 rw Buffer_Write_Ready_Si gnal_Enable 4 DMA_Interrupt_Signal _Enable 3 Block_Gap_Event_Sign al_Enable 2 0x0 0 - Masked 1 - Enabled 0x0 0 - Masked 1 - Enabled 0x0 0 - Masked 1 - Enabled rw 0x0 0 - Masked 1 - Enabled rw 0x0 0 - Masked 1 - Enab
Appendix B: Field Name Bits Command_Not_Issued _By_Auto_CMD12_Err or 7 Type ro Reset Value 0x0 Register Details Description Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register. 0 - No Error 1 - Not Issued reserved 6:5 ro 0x0 Reserved Auto_CMD12_Index_E rror 4 ro 0x0 Occurs if the Command Index error occurs in response to a command.
Appendix B: Access Type ro Reset Value 0x69EC0080 Description Capabilities register Register Details Register Capabilities Details This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization.
Appendix B: Field Name Bits High_Speed_Support 21 Type ro Reset Value 0x1 Register Details Description This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 MHz (for SD)/ 20MHz to 52MHz (for MMC). 0 - High Speed Not Supported 1 - High Speed Supported reserved 20 ro 0x0 Reserved ADMA2_Support 19 ro 0x1 1 - ADMA2 support.
Appendix B: Description Register Details Maximum current capabilities register Register Maximum_current_capabilities Details Field Name Bits Type Reset Value Description Maximum_Current_for 23:16 _1_8V ro 0x0 Maximum Current for 1.8V Maximum_Current_for 15:8 _3_0V ro 0x0 Maximum Current for 3.0V Maximum_Current_for 7:0 _3_3V ro 0x1 Maximum Current for 3.
Appendix B: Field Name Force_Event_for_Vend or_Specific_Error_Stat us Bits 31:30 Type wo Reset Value 0x0 Register Details Description Additional status bits can be defined in this register by the vendor.
Appendix B: Field Name Bits Force_Event_for_Com mand_Timeout_Error 16 Type wo Reset Value 0x0 Register Details Description Force Event for Command Timeout Error 1 - Interrupt is generated 0 - No interrupt reserved 15:8 ro 0x0 Reserved Force_Event_for_com mand_not_issued_by_ Auto_CMD12_Error 7 wo 0x0 1 - Interrupt is generated reserved 6:5 ro 0x0 Reserved Force_Event_for_Auto _CMD12_Index_Error 4 wo 0x0 1 - Interrupt is generated Force_Event_for_Auto _CMD12_End_bit_Erro r 3 For
Appendix B: Field Name Bits ADMA_Length_Mism atch_Error 2 Type wtc Reset Value 0x0 Register Details Description This error occurs in the following 2 cases. 1. While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. 2. Total data length can not be divided by the block length.
Appendix B: Register Details Register ADMA_system_address Details Field Name Bits ADMA_System_Addre ss 31:0 Type rw Reset Value 0x0 Description This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line.
Appendix B: Register Details Register Boot_Timeout_control Details Field Name Bits Boot_Data_Timeout_C ounter_Value 31:0 Type rw Reset Value 0x0 Description This value determines the interval by which DAT line time-outs are detected during boot operation for MMC3.31 card. The value is in number of sd clock.
Appendix B: Register Details Register SPI_interrupt_support Details Field Name Bits SPI_INT_SUPPORT 7:0 Type rw Reset Value 0x0 Description This bit is set to indicate the assertion of interrupts in the SPI mode at any time, irrespective of the status of the card select (CS) line. If this bit is zero, then SDIO card can only assert the interrupt line in the SPI mode when the CS line is asserted.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 15:8 ro 0x0 Reserved Interrupt_Signal_for_E ach_Slot 7:0 ro 0x0 These status bit indicate the logical OR of Interrupt signal and Wakeup signal for each slot. A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots. the HD can know which interrupt is generated by reading these status bits.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description SDIO_CLK_CTRL 0x00000150 32 rw 0x00001E03 SDIO Ref Clock Control UART_CLK_CTRL 0x00000154 32 rw 0x00003F03 UART Ref Clock Control SPI_CLK_CTRL 0x00000158 32 rw 0x00003F03 SPI Ref Clock Control CAN_CLK_CTRL 0x0000015C 32 rw 0x00501903 CAN Ref Clock Control CAN_MIOCLK_CTRL 0x00000160 32 rw 0x00000000 CAN MIO Clock Control DBG_CLK_CTRL 0x00000164 32 rw 0x00000F03 SoC Debug Clock Cont
Appendix B: Register Name Address Width Type Reset Value Register Details Description GEM_RST_CTRL 0x00000214 32 rw 0x00000000 Gigabit Ethernet SW Reset Control SDIO_RST_CTRL 0x00000218 32 rw 0x00000000 SDIO Software Reset Control SPI_RST_CTRL 0x0000021C 32 rw 0x00000000 SPI Software Reset Control CAN_RST_CTRL 0x00000220 32 rw 0x00000000 CAN Software Reset Control I2C_RST_CTRL 0x00000224 32 rw 0x00000000 I2C Software Reset Control UART_RST_CTRL 0x00000228 32 rw 0x00
Appendix B: Register Name Address Width Type Reset Value Description MIO_PIN_04 0x00000710 32 rw 0x00000601 MIO Pin 4 Control MIO_PIN_05 0x00000714 32 rw 0x00000601 MIO Pin 5 Control MIO_PIN_06 0x00000718 32 rw 0x00000601 MIO Pin 6 Control MIO_PIN_07 0x0000071C 32 rw 0x00000601 MIO Pin 7 Control MIO_PIN_08 0x00000720 32 rw 0x00000601 MIO Pin 8 Control MIO_PIN_09 0x00000724 32 rw 0x00001601 MIO Pin 9 Control MIO_PIN_10 0x00000728 32 rw 0x00001601 MIO Pin 10 Con
Appendix B: Register Name Address Width Type Reset Value Register Details Description MIO_PIN_38 0x00000798 32 rw 0x00001601 MIO Pin 38 Control MIO_PIN_39 0x0000079C 32 rw 0x00001601 MIO Pin 39 Control MIO_PIN_40 0x000007A0 32 rw 0x00001601 MIO Pin 40 Control MIO_PIN_41 0x000007A4 32 rw 0x00001601 MIO Pin 41 Control MIO_PIN_42 0x000007A8 32 rw 0x00001601 MIO Pin 42 Control MIO_PIN_43 0x000007AC 32 rw 0x00001601 MIO Pin 43 Control MIO_PIN_44 0x000007B0 32 rw 0x
Appendix B: Register Name Address Width Type Reset Value Register Details Description DDRIOB_ADDR1 0x00000B44 32 rw 0x00000800 DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B DDRIOB_DATA0 0x00000B48 32 rw 0x00000800 DDR IOB Config for Data 15:0 DDRIOB_DATA1 0x00000B4C 32 rw 0x00000800 DDR IOB Config for Data 31:16 DDRIOB_DIFF0 0x00000B50 32 rw 0x00000800 DDR IOB Config for DQS 1:0 DDRIOB_DIFF1 0x00000B54 32 rw 0x00000800 DDR IOB Config for DQS 3:2 DDRIOB_CL
Appendix B: Register Details Register SCL Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero. LOCK 0 rw 0x0 Secure configuration lock for these slcr registers: SCL, PSS_RST_CTRL, APU_CTRL, and WDT_CLK_SEL. Read: 0: unlocked, Secure writes to secure configuration registers are enabled. 1: locked, all writes to secure configuration registers are ignored. Write: 0: noaffect. 1: lock the secure configuration registers.
Appendix B: Width 32 bits Access Type wo Reset Value 0x00000000 Description SLCR Write Protection Unlock Register Details Register SLCR_UNLOCK Details Field Name Bits Type Reset Value Description reserved 31:16 wo 0x0 Reserved. Writes are ignored, read data is zero. UNLOCK_KEY 15:0 wo 0x0 Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register.
Appendix B: Absolute Address 0xF8000100 Width 32 bits Access Type rw Reset Value 0x0001A008 Description ARM PLL Control Register Details Register ARM_PLL_CTRL Details Field Name Bits Type Reset Value Description reserved 31:19 rw 0x0 Reserved. Writes are ignored, read data is zero. PLL_FDIV 18:12 rw 0x1A Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode.
Appendix B: Relative Address 0x00000104 Absolute Address 0xF8000104 Width 32 bits Access Type rw Reset Value 0x0001A008 Description DDR PLL Control Register Details Register DDR_PLL_CTRL Details Field Name Bits Type Reset Value Description reserved 31:19 rw 0x0 Reserved. Writes are ignored, read data is zero. PLL_FDIV 18:12 rw 0x1A Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode.
Appendix B: Register Details Register (slcr) IO_PLL_CTRL Name IO_PLL_CTRL Relative Address 0x00000108 Absolute Address 0xF8000108 Width 32 bits Access Type rw Reset Value 0x0001A008 Description IO PLL Control Register IO_PLL_CTRL Details Field Name Bits Type Reset Value Description reserved 31:19 rw 0x0 Reserved. Writes are ignored, read data is zero. PLL_FDIV 18:12 rw 0x1A Provide the feedback divisor for the PLL.
Appendix B: Register Details Register (slcr) PLL_STATUS Name PLL_STATUS Relative Address 0x0000010C Absolute Address 0xF800010C Width 32 bits Access Type ro Reset Value 0x0000003F Description PLL Status Register PLL_STATUS Details Note: Reset condition is actually 0, but will read a 1 by the time this register can be read by software if PLLs are enabled by BOOT_MODE. Field Name Bits Type Reset Value reserved 31:6 ro 0x0 IO_PLL_STABLE 5 ro 0x1 Description Reserved.
Appendix B: Reset Value 0x00177EA0 Description ARM PLL Configuration Register Details Register ARM_PLL_CFG Details Field Name Bits Type Reset Value Description reserved 31:22 rw 0x0 Reserved. Writes are ignored, read data is zero. LOCK_CNT 21:12 rw 0x177 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.
Appendix B: Register Details Register (slcr) IO_PLL_CFG Name IO_PLL_CFG Relative Address 0x00000118 Absolute Address 0xF8000118 Width 32 bits Access Type rw Reset Value 0x00177EA0 Description IO PLL Configuration Register IO_PLL_CFG Details Field Name Bits Type Reset Value Description reserved 31:22 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name Bits CPU_1XCLKACT 27 Type rw Reset Value 0x1 Register Details Description CPU_1x Clock control: 0: disable, 1: enable CPU_2XCLKACT 26 rw 0x1 CPU_2x Clock control: 0: disable, 1: enable CPU_3OR2XCLKACT 25 rw 0x1 CPU_3x2x Clock control: 0: disable, 1: enable CPU_6OR4XCLKACT 24 rw 0x1 CPU_6x4x Clock control: 0: disable, 1: enable reserved 23:14 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 19:2 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Access Type rw Reset Value 0x01FFCCCD Description AMBA Peripheral Clock Control Register Details Register APER_CLK_CTRL Details Please note that these clocks must be enabled if you want to read from the peripheral register space. Field Name Bits Type Reset Value Description reserved 31:25 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 8 rw 0x0 Reserved. Writes are ignored, read data is zero. GEM1_CPU_1XCLKA CT 7 rw 0x1 Gigabit Ethernet 1 AMBA Clock control GEM0_CPU_1XCLKA CT 6 reserved 5 rw 0x0 Reserved. Writes are ignored, read data is zero. reserved 4 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 3:1 rw 0x0 Reserved. Writes are ignored, read data is zero. reserved 0 rw 0x1 Reserved. Do not modify.
Appendix B: Register Details Register GEM0_RCLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:5 rw 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL 4 rw 0x0 Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO reserved 3:1 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Access Type rw Reset Value 0x00003C01 Description GigE 0 Ref Clock Control Register Details Register GEM0_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:26 rw 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 25:20 rw 0x0 Second divisor for Ethernet controller 0 source clock. reserved 19:14 rw 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR 13:8 rw 0x3C First divisor for Ethernet controller 0 source clock.
Appendix B: Field Name Bits Type Reset Value Register Details Description DIVISOR 13:8 rw 0x3C First divisor for Ethernet controller 1 source clock. reserved 7 rw 0x0 Reserved. Writes are ignored, read data is zero. SRCSEL 6:4 rw 0x0 Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 1 EMIO clock reserved 3:1 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Absolute Address 0xF800014C Width 32 bits Access Type rw Reset Value 0x00002821 Description Quad SPI Ref Clock Control Register Details Register LQSPI_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR 13:8 rw 0x28 Divisor for Quad SPI Controller source clock. reserved 7:6 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name SRCSEL Bits 5:4 Type rw Reset Value 0x0 Register Details Description Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. reserved 3:2 rw 0x0 Reserved. Writes are ignored, read data is zero. CLKACT1 1 rw 0x1 SDIO Controller 1 Clock control. 0: disable, 1: enable CLKACT0 0 rw 0x1 SDIO Controller 0 Clock control.
Appendix B: Register Details Register (slcr) SPI_CLK_CTRL Name SPI_CLK_CTRL Relative Address 0x00000158 Absolute Address 0xF8000158 Width 32 bits Access Type rw Reset Value 0x00003F03 Description SPI Ref Clock Control Register SPI_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Register Details Register CAN_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:26 rw 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 25:20 rw 0x5 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider. reserved 19:14 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name CAN1_MUX Bits 21:16 Type rw Reset Value 0x0 Register Details Description CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. reserved 15:7 rw 0x0 CAN0_REF_SEL 6 rw 0x0 Reserved. Writes are ignored, read data is zero. CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field CAN0_MUX 5:0 rw 0x0 CAN 0 mux selection for MIO.
Appendix B: Field Name CPU_1XCLKACT Bits 1 Type rw Reset Value 0x1 Register Details Description Debug CPU 1x Clock active. 0 - Clocks are disabled.
Appendix B: Width 32 bits Access Type rw Reset Value 0x00000000 Description Central Interconnect Clock Control Register Details Register TOPSW_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Register Details Register (slcr) FPGA0_THR_CTRL Name FPGA0_THR_CTRL Relative Address 0x00000174 Absolute Address 0xF8000174 Width 32 bits Access Type rw Reset Value 0x00000000 Description PL Clock 0 Throttle control Register FPGA0_THR_CTRL Details Field Name Bits Type Reset Value Description reserved 31:4 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Register Details Register FPGA0_THR_CNT Details Field Name Bits Type Reset Value Description reserved 31:20 rw 0x0 Reserved. Writes are ignored, read data is zero. reserved 19:16 rw 0x0 Reserved. Do not modify. LAST_CNT 15:0 rw 0x0 Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.
Appendix B: Description Register Details PL Clock 1 Output control Register FPGA1_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:26 rw 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 25:20 rw 0x1 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide reserved 19:14 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name CNT_RST Bits 1 Type rw Reset Value 0x0 Register Details Description Reset clock throttle counter when in halt state: 0: No effect 1: Causes counter to be reset once HALT state is entered CPU_START 0 rw 0x0 Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.
Appendix B: Description Register Details PL Clock 1 Throttle Status control Register FPGA1_THR_STA Details Field Name Bits Type Reset Value Description reserved 31:17 ro 0x0 Reserved. Writes are ignored, read data is zero. RUNNING 16 ro 0x1 Current running status of FPGA clock output: 0: Clock is stopped or in normal mode (OK to change configuration). 1: Clock is running in debug mode (Keep configuration static).
Appendix B: Register Details Register (slcr) FPGA2_THR_CTRL Name FPGA2_THR_CTRL Relative Address 0x00000194 Absolute Address 0xF8000194 Width 32 bits Access Type rw Reset Value 0x00000000 Description PL Clock 2 Throttle Control Register FPGA2_THR_CTRL Details Field Name Bits Type Reset Value Description reserved 31:4 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Register Details Register FPGA2_THR_CNT Details Field Name Bits Type Reset Value Description reserved 31:20 rw 0x0 Reserved. Writes are ignored, read data is zero. reserved 19:16 rw 0x0 Reserved. Do not modify. LAST_CNT 15:0 rw 0x0 Last count value. Specifies the total number of clocks output in debug mode by the clock throttle logic.
Appendix B: Description Register Details PL Clock 3 output control Register FPGA3_CLK_CTRL Details Field Name Bits Type Reset Value Description reserved 31:26 rw 0x0 Reserved. Writes are ignored, read data is zero. DIVISOR1 25:20 rw 0x1 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide reserved 19:14 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name CNT_RST Bits 1 Type rw Reset Value 0x0 Register Details Description Reset clock throttle counter when in halt state: 0: No effect 1: Causes counter to be reset once HALT state is entered CPU_START 0 rw 0x0 Start or restart count on detection of 0 to 1 transition in the value of this bit. A read will return the written value. (Reminder that bits 2&3 must be programmed according to description.
Appendix B: Description Register Details PL Clock 3 Throttle Status Register FPGA3_THR_STA Details Field Name Bits Type Reset Value Description reserved 31:17 ro 0x0 Reserved. Writes are ignored, read data is zero. RUNNING 16 ro 0x1 Current running status of FPGA clock output: 0: Clock is stopped or in normal mode (OK to change configuration). 1: Clock is running in debug mode (Keep configuration static).
Appendix B: Access Type rw Reset Value 0x00000000 Description PS Software Reset Control Register Details Register PSS_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero. SOFT_RST 0 rw 0x0 Processing System software reset control signal.
Appendix B: Description Register Details Central Interconnect Reset Control Register TOPSW_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero. TOPSW_RST 0 rw 0x0 Central Interconnect Reset Control: 0: de-assert (no reset) 1: assert Care must be taken to ensure that the AXI interconnect does not have outstanding transactions and the bus is idle.
Appendix B: Description Register Details USB Software Reset Control Register USB_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:2 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name Bits GEM1_RX_RST 5 Type rw Reset Value 0x0 Register Details Description Gigabit Ethernet 1 Rx clock domain reset: 0: de-assert (no reset) 1: assert (held in reset) GEM0_RX_RST 4 rw 0x0 Gigabit Ethernet 0 Rx clock domain reset: 0: de-assert (no reset) 1: assert (held in reset) reserved 3:2 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name Bits SDIO1_CPU1X_RST 1 Type rw Reset Value 0x0 Register Details Description SDIO 1 master and slave AMBA interfaces reset: 0: de-assert (no reset) 1: assert (held in reset) SDIO0_CPU1X_RST 0 rw 0x0 SDIO 0 master and slave AMBA interfaces reset: 0: de-assert (no reset) 1: assert (held in reset) Register (slcr) SPI_RST_CTRL Name SPI_RST_CTRL Relative Address 0x0000021C Absolute Address 0xF800021C Width 32 bits Access Type rw Reset Value 0x00000000 Description
Appendix B: Field Name SPI1_CPU1X_RST Bits 1 Type rw Reset Value 0x0 Register Details Description SPI 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the SPI 1 subsystem will be reset. 0: No reset 1: AMBA clock portion of SPI 1 subsytem held in reset SPI0_CPU1X_RST 0 rw 0x0 SPI 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the SPI 0 subsystem will be reset.
Appendix B: Field Name Bits CAN1_CPU1X_RST 1 Type rw Reset Value 0x0 Register Details Description CAN 1 AMBA software reset. On assertion of this reset, the AMBA clock portion of the CAN 1 subsystem will be reset. 0: No reset 1: AMBA clock portion of CAN 1 subsytem held in reset CAN0_CPU1X_RST 0 rw 0x0 CAN 0 AMBA software reset. On assertion of this reset, the AMBA clock portion of the CAN 0 subsystem will be reset.
Appendix B: Register Details Register (slcr) UART_RST_CTRL Name UART_RST_CTRL Relative Address 0x00000228 Absolute Address 0xF8000228 Width 32 bits Access Type rw Reset Value 0x00000000 Description UART Software Reset Control Register UART_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:4 rw 0x0 Reserved. Writes are ignored, read data is zero. UART1_REF_RST 3 rw 0x0 UART 1 Reference software reset.
Appendix B: Description Register Details GPIO Software Reset Control Register GPIO_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero. GPIO_CPU1X_RST 0 rw 0x0 GPIO AMBA software reset. On assertion of this reset, the AMBA clock portion of the GPIO subsystem will be reset.
Appendix B: Relative Address 0x00000234 Absolute Address 0xF8000234 Width 32 bits Access Type rw Reset Value 0x00000000 Description SMC Software Reset Control Register Details Register SMC_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:2 rw 0x0 Reserved. Writes are ignored, read data is zero. SMC_REF_RST 1 rw 0x0 SMC Reference software reset. On assertion of this reset, the Reference clock portion of the SMC subsystem will be reset.
Appendix B: Register Details Register OCM_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero. OCM_RST 0 rw 0x0 OCM software reset. On assertion of this reset, the OCM subsystem will be reset.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 7:4 rw 0x0 Reserved. Writes are ignored, read data is zero. FPGA3_OUT_RST 3 rw 0x1 PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) FPGA2_OUT_RST 2 rw 0x1 PL Reset 2 (FCLKRESETN2 output signal).
Appendix B: Register Details Register A9_CPU_RST_CTRL Details Field Name Bits Type Reset Value Description reserved 31:9 rw 0x0 Reserved. Writes are ignored, read data is zero. PERI_RST 8 rw 0x0 CPU peripheral soft reset. 0: de-assert (no reset) 1: assert (held in reset) reserved 7:6 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Field Name CTRL1 Bits 1 Type rw Reset Value 0x0 Register Details Description Select the target for the APU watchdog timer 1 reset signal. Route the WDT reset to: 0: the same system level as PS_SRST_B 1: the CPU associated with the watchdog timer CTRL0 0 rw 0x0 Select the target for the APU watchdog timer 0 reset signal.
Appendix B: Field Name Bits AWDT0_RST 17 Type rw Reset Value 0x0 Register Details Description Last reset was due to APU watchdog timer 0, if set. This field is written by ROM code SWDT_RST 16 rw 0x0 Last reset was due to system watchdog timeout, if set (see watchdog status for more details). This field is written by ROM code BOOTROM_ERROR_C ODE 15:0 rw 0x0 This field is written by the BootROM to describe errors that occur during the boot proceess.
Appendix B: Register Details Register (slcr) APU_CTRL Name APU_CTRL Relative Address 0x00000300 Absolute Address 0xF8000300 Width 32 bits Access Type rw Reset Value 0x00000000 Description APU Control Register APU_CTRL Details Field Name Bits Type Reset Value Description reserved 31:3 rw 0x0 Reserved. Writes are ignored, read data is zero. CFGSDISABLE 2 rw 0x0 Disable write access to some system control processor registers, and some GIC registers. Set only.
Appendix B: Register Details Register WDT_CLK_SEL Details Field Name Bits Type Reset Value reserved 31:1 rw 0x0 SEL 0 rw 0x0 Description Reserved. Writes are ignored, read data is zero.
Appendix B: Register Details Register TZ_DMA_IRQ_NS Details Field Name Bits Type Reset Value Description reserved 31:16 rw 0x0 Should Be Zero DMA_IRQ_NS 15:0 rw 0x0 TZ security (connected to boot_irq_ns on DMAC): 0: secure, DMAC operates in the secure state. 1: non-secure, DMAC interrupt/event bit is in the non-secure state.
Appendix B: Register Details Register PSS_IDCODE Details Field Name Bits Type Reset Value Description REVISION 31:28 ro x Revision code FAMILY 27:21 ro 0x1B Family code SUBFAMILY 20:17 ro 0x9 Subfamily code DEVICE 16:12 ro x Device code 7z007s: 0x03 7z012s: 0x1c 7z014s: 0x08 7z010: 0x02 7z015: 0x1b 7z020: 0x07 7z030: 0x0c 7z035: 0x12 7z045: 0x11 7z100: 0x16 MANUFACTURER_ID 11:1 ro 0x49 Manufacturer ID reserved 0 ro 0x1 Reserved. Writes are ignored, read data is one.
Appendix B: Field Name Bits Type Reset Value Register Details Description S2_AWURGENT 2 rw 0x0 Set Write port 2 prioritization. S1_AWURGENT 1 rw 0x0 Set Write port 1 prioritization. S0_AWURGENT 0 rw 0x0 Set Write port 0 prioritization.
Appendix B: Field Name START_CAL_DLL Bits 1 Type wo Reset Value 0x0 Register Details Description This register creates a pulse that is first synchronised into the ddr_clk domain and then directly drives the co_gs_dll_calib input into the DDR controller. This signal is a command that indicates to the controller to issue a dll_calib to the DRAM. This signal should pulse for 1 ddrc_core_clk clock cycle to request a dll_calib to be issued.
Appendix B: Register Details Register (slcr) DDR_REF_START Name DDR_REF_START Relative Address 0x00000614 Absolute Address 0xF8000614 Width 32 bits Access Type mixed Reset Value 0x00000000 Description DDR Refresh Start Triggers Register DDR_REF_START Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero.
Appendix B: Register Details Register DDR_CMD_STA Details Field Name Bits Type Reset Value reserved 31:1 rw 0x0 CMD_Q_NEMPTY 0 ro 0x0 Description Reserved. Writes are ignored, read data is zero. DDR controller command store fill status. 0: indicates DDRC command store is empty. 1: indicates there are commands pending in DDRC command store. This register is a continuous monitor of the ddrc_co_q_not_empty output from the DDR controller, which is first synchronised from ddr_clk into amba1x_clk.
Appendix B: Field Name S2_ARQOS_MODE Bits 13:12 Type rw Reset Value 0x0 Register Details Description Selects between the AXI port s2_arqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s2_arurgent bit is driven from the 'S2_ARURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s2_arurgent bit is driven from the s2_arqos bit. 10: DDRC s2_arurgent bit is driven from the fabric ddr_arb[2] input.
Appendix B: Field Name Bits S2_AWQOS_MODE 5:4 Type rw Reset Value 0x0 Register Details Description Selects between the AXI port s2_awqos[3], fabric signal or static register to drive the DDRC urgent bit. 00: DDRC s2_awurgent bit is driven from the 'S2_AWURGENT' field of the DDR_URGENT_VAL register. 01: DDRC s2_awurgent bit is driven from the s2_awqos bit. 10: DDRC s2_awurgent bit is driven from the fabric ddr_arb[2] input.
Appendix B: Register Details Register DDR_DFI_STATUS Details Field Name Bits Type Reset Value Description reserved 31:1 rw 0x0 Reserved. Writes are ignored, read data is zero. DFI_CAL_ST 0 ro 0x0 This signal is intended to allow a calibration of the IOB's at a time when the DDR controller is in its calibration mode, i.e. during an idle period.
Appendix B: Field Name Speed Bits 8 Type rw Reset Value 0x0 Register Details Description Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33.
Appendix B: Field Name Bits Type Reset Value Register Details Description IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux
Appendix B: Field Name L3_SEL Bits 7:5 Type rw Reset Value 0x0 Register Details Description Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output TRI_ENABLE 0 rw 0x1 Operat
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr) MIO_PIN_04 Name MIO_PI
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr) MIO
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr) MIO
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr) MIO_PIN_07 N
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: reserved TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr) MIO_PIN_08 Name MIO_PIN_08 Relative Address 0x
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr) MIO_PIN_09 Name MIO_PIN_09 Relative Ad
Appendix B: Field Name L2_SEL Bits 4:3 Type rw Reset Value 0x0 Register Details Description Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output L1_SEL 2 rw 0x0 Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output L0_SEL 1 rw 0x0 Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE] Register (slcr)
Appendix B: Field Name L3_SEL Bits 7:5 Type rw Reset Value 0x0 Register Details Description Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output L1_SEL 2
Appendix B: Field Name Bits Type Reset Value Register Details Description IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output L2_SEL 4:3 rw 0x0 Level 2 Mux Select 00:
Appendix B: Register Details Register MIO_PIN_12 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C
Appendix B: Register Details Register MIO_PIN_13 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1
Appendix B: Description Register Details MIO Pin 14 Control Register MIO_PIN_14 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Outpu
Appendix B: Reset Value 0x00001601 Description MIO Pin 15 Control Register Details Register MIO_PIN_15 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux Select 000: GPIO
Appendix B: Access Type rw Reset Value 0x00001601 Description MIO Pin 16 Control Register Details Register MIO_PIN_16 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw 0x0 Level 3 Mux
Appendix B: Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 17 Control Register Details Register MIO_PIN_17 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed] L3_SEL 7:5 rw
Appendix B: Absolute Address 0xF8000748 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 18 Control Register Details Register MIO_PIN_18 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x0 Operates the same as MIO_PI
Appendix B: Relative Address 0x0000074C Absolute Address 0xF800074C Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 19 Control Register Details Register MIO_PIN_19 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type] Speed 8 rw 0x
Appendix B: Register Details Register (slcr) MIO_PIN_20 Name MIO_PIN_20 Relative Address 0x00000750 Absolute Address 0xF8000750 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 20 Control Register MIO_PIN_20 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_21 Name MIO_PIN_21 Relative Address 0x00000754 Absolute Address 0xF8000754 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 21 Control Register MIO_PIN_21 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_22 Name MIO_PIN_22 Relative Address 0x00000758 Absolute Address 0xF8000758 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 22 Control Register MIO_PIN_22 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_23 Name MIO_PIN_23 Relative Address 0x0000075C Absolute Address 0xF800075C Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 23 Control Register MIO_PIN_23 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_24 Name MIO_PIN_24 Relative Address 0x00000760 Absolute Address 0xF8000760 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 24 Control Register MIO_PIN_24 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_25 Name MIO_PIN_25 Relative Address 0x00000764 Absolute Address 0xF8000764 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 25 Control Register MIO_PIN_25 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_26 Name MIO_PIN_26 Relative Address 0x00000768 Absolute Address 0xF8000768 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 26 Control Register MIO_PIN_26 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_27 Name MIO_PIN_27 Relative Address 0x0000076C Absolute Address 0xF800076C Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 27 Control Register MIO_PIN_27 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_28 Name MIO_PIN_28 Relative Address 0x00000770 Absolute Address 0xF8000770 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 28 Control Register MIO_PIN_28 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_29 Name MIO_PIN_29 Relative Address 0x00000774 Absolute Address 0xF8000774 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 29 Control Register MIO_PIN_29 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_30 Name MIO_PIN_30 Relative Address 0x00000778 Absolute Address 0xF8000778 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 30 Control Register MIO_PIN_30 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_31 Name MIO_PIN_31 Relative Address 0x0000077C Absolute Address 0xF800077C Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 31 Control Register MIO_PIN_31 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_32 Name MIO_PIN_32 Relative Address 0x00000780 Absolute Address 0xF8000780 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 32 Control Register MIO_PIN_32 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_33 Name MIO_PIN_33 Relative Address 0x00000784 Absolute Address 0xF8000784 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 33 Control Register MIO_PIN_33 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_34 Name MIO_PIN_34 Relative Address 0x00000788 Absolute Address 0xF8000788 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 34 Control Register MIO_PIN_34 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_35 Name MIO_PIN_35 Relative Address 0x0000078C Absolute Address 0xF800078C Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 35 Control Register MIO_PIN_35 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_36 Name MIO_PIN_36 Relative Address 0x00000790 Absolute Address 0xF8000790 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 36 Control Register MIO_PIN_36 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_37 Name MIO_PIN_37 Relative Address 0x00000794 Absolute Address 0xF8000794 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 37 Control Register MIO_PIN_37 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_38 Name MIO_PIN_38 Relative Address 0x00000798 Absolute Address 0xF8000798 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 38 Control Register MIO_PIN_38 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_39 Name MIO_PIN_39 Relative Address 0x0000079C Absolute Address 0xF800079C Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 39 Control Register MIO_PIN_39 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_40 Name MIO_PIN_40 Relative Address 0x000007A0 Absolute Address 0xF80007A0 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 40 Control Register MIO_PIN_40 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_41 Name MIO_PIN_41 Relative Address 0x000007A4 Absolute Address 0xF80007A4 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 41 Control Register MIO_PIN_41 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_42 Name MIO_PIN_42 Relative Address 0x000007A8 Absolute Address 0xF80007A8 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 42 Control Register MIO_PIN_42 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_43 Name MIO_PIN_43 Relative Address 0x000007AC Absolute Address 0xF80007AC Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 43 Control Register MIO_PIN_43 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_44 Name MIO_PIN_44 Relative Address 0x000007B0 Absolute Address 0xF80007B0 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 44 Control Register MIO_PIN_44 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_45 Name MIO_PIN_45 Relative Address 0x000007B4 Absolute Address 0xF80007B4 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 45 Control Register MIO_PIN_45 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_46 Name MIO_PIN_46 Relative Address 0x000007B8 Absolute Address 0xF80007B8 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 46 Control Register MIO_PIN_46 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_47 Name MIO_PIN_47 Relative Address 0x000007BC Absolute Address 0xF80007BC Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 47 Control Register MIO_PIN_47 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_48 Name MIO_PIN_48 Relative Address 0x000007C0 Absolute Address 0xF80007C0 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 48 Control Register MIO_PIN_48 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_49 Name MIO_PIN_49 Relative Address 0x000007C4 Absolute Address 0xF80007C4 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 49 Control Register MIO_PIN_49 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_50 Name MIO_PIN_50 Relative Address 0x000007C8 Absolute Address 0xF80007C8 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 50 Control Register MIO_PIN_50 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_51 Name MIO_PIN_51 Relative Address 0x000007CC Absolute Address 0xF80007CC Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 51 Control Register MIO_PIN_51 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_52 Name MIO_PIN_52 Relative Address 0x000007D0 Absolute Address 0xF80007D0 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 52 Control Register MIO_PIN_52 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_PIN_53 Name MIO_PIN_53 Relative Address 0x000007D4 Absolute Address 0xF80007D4 Width 32 bits Access Type rw Reset Value 0x00001601 Description MIO Pin 53 Control Register MIO_PIN_53 Details Field Name Bits Type Reset Value Description reserved 31:14 rw 0x0 reserved DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr] PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP] IO_Type 11:9 rw 0x3 Operates the
Appendix B: Register Details Register (slcr) MIO_LOOPBACK Name MIO_LOOPBACK Relative Address 0x00000804 Absolute Address 0xF8000804 Width 32 bits Access Type rw Reset Value 0x00000000 Description Loopback function within MIO Register MIO_LOOPBACK Details Field Name Bits Type Reset Value Description reserved 31:4 rw 0x0 reserved I2C0_LOOP_I2C1 3 rw 0x0 I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping.
Appendix B: Register Details Register (slcr) MIO_MST_TRI0 Name MIO_MST_TRI0 Relative Address 0x0000080C Absolute Address 0xF800080C Width 32 bits Access Type rw Reset Value 0xFFFFFFFF Description MIO pin Tri-state Enables, 31:0 Register MIO_MST_TRI0 Details Parallel access to the master tri-state enables for MIO pins Field Name Bits Type Reset Value Description PIN_31_TRI 31 rw 0x1 Master Tri-state Enable for pin 31, active high PIN_30_TRI 30 rw 0x1 Master Tri-state Enable for
Appendix B: Field Name Bits Type Reset Value Register Details Description PIN_08_TRI 8 rw 0x1 Master Tri-state Enable for pin 8, active high PIN_07_TRI 7 rw 0x1 Master Tri-state Enable for pin 7, active high PIN_06_TRI 6 rw 0x1 Master Tri-state Enable for pin 6, active high PIN_05_TRI 5 rw 0x1 Master Tri-state Enable for pin 5, active high PIN_04_TRI 4 rw 0x1 Master Tri-state Enable for pin 4, active high PIN_03_TRI 3 rw 0x1 Master Tri-state Enable for pin 3, active high
Appendix B: Field Name Bits Type Reset Value Register Details Description PIN_43_TRI 11 rw 0x1 Master Tri-state Enable for pin 43, active high PIN_42_TRI 10 rw 0x1 Master Tri-state Enable for pin 42, active high PIN_41_TRI 9 rw 0x1 Master Tri-state Enable for pin 41, active high PIN_40_TRI 8 rw 0x1 Master Tri-state Enable for pin 40, active high PIN_39_TRI 7 rw 0x1 Master Tri-state Enable for pin 39, active high PIN_38_TRI 6 rw 0x1 Master Tri-state Enable for pin 38, acti
Appendix B: Register Details Register (slcr) SD1_WP_CD_SEL Name SD1_WP_CD_SEL Relative Address 0x00000834 Absolute Address 0xF8000834 Width 32 bits Access Type rw Reset Value 0x00000000 Description SDIO 1 WP CD select Register SD1_WP_CD_SEL Details Field Name Bits Type Reset Value Description reserved 31:22 rw 0x0 reserved SDIO1_CD_SEL 21:16 rw 0x0 SDIO 1 CD Select.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 4 rw 0x0 Reserved. Do not modify. USER_LVL_SHFTR_E N 3:0 rw 0x0 Level shifter enable to drive signals between PS and PL.
Appendix B: Access Type rw Reset Value 0x00010101 Description Reserved Register Details Register Reserved Details Field Name Bits Type Reset Value Description reserved 23:22 rw 0x0 Reserved. Do not modify. reserved 21 rw 0x0 Reserved. Do not modify. reserved 20:19 rw 0x0 Reserved. Do not modify. reserved 18:16 rw 0x1 Must be set to 2. Any other value including the reset value may lead to undefined behavior. reserved 15:14 rw 0x0 Reserved. Do not modify.
Appendix B: Register Details Register GPIOB_CTRL Details Field Name Bits Type Reset Value reserved 31:12 rw 0x0 VREF_SW_EN 11 rw 0x0 Description Reserved. Writes are ignored, read data is zero. Enables the VREF switch 0: internal 1: external reserved 10 rw 0x0 Reserved. Do not modify. reserved 9 rw 0x0 Reserved. Do not modify. reserved 8 rw 0x0 Reserved. Do not modify. reserved 7 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 18:16 rw 0x0 Reserved. Do not modify. reserved 15:12 rw 0x0 Reserved. Do not modify. reserved 11:8 rw 0x0 Reserved. Do not modify. reserved 7:4 rw 0x0 Reserved. Do not modify. reserved 3:0 rw 0x0 Reserved. Do not modify.
Appendix B: Access Type rw Reset Value 0x00000000 Description MIO GPIOB CMOS 3.3V config Register Details Register GPIOB_CFG_CMOS33 Details The only allowed values for this register are 0x00000000 (reset value) and 0x0C301166 (normal operation) Field Name Bits Type Reset Value Description reserved 31:28 rw 0x0 Reserved. Writes are ignored, read data is zero. reserved 27:25 rw 0x0 Reserved. Do not modify. reserved 24:22 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 21:19 rw 0x0 Reserved. Do not modify. reserved 18:16 rw 0x0 Reserved. Do not modify. reserved 15:12 rw 0x0 Reserved. Do not modify. reserved 11:8 rw 0x0 Reserved. Do not modify. reserved 7:4 rw 0x0 Reserved. Do not modify. reserved 3:0 rw 0x0 Reserved. Do not modify.
Appendix B: Register Details Register DDRIOB_ADDR0 Details Field Name Bits Type Reset Value Description reserved 31:12 rw 0x0 Reserved PULLUP_EN 11 rw 0x1 enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the
Appendix B: Field Name Bits INP_TYPE 2:1 Type rw Reset Value 0x0 Register Details Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. reserved 0 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits IBUF_DISABLE_MOD E 7 Type rw Reset Value 0x0 Register Details Description Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
Appendix B: Register Details Register DDRIOB_DATA0 Details Field Name Bits Type Reset Value Description reserved 31:12 rw 0x0 Reserved PULLUP_EN 11 rw 0x1 enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the
Appendix B: Field Name Bits INP_TYPE 2:1 Type rw Reset Value 0x0 Register Details Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. reserved 0 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits IBUF_DISABLE_MOD E 7 Type rw Reset Value 0x0 Register Details Description Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
Appendix B: Register Details Register DDRIOB_DIFF0 Details Field Name Bits Type Reset Value Description reserved 31:12 rw 0x0 Reserved PULLUP_EN 11 rw 0x1 enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the
Appendix B: Field Name Bits INP_TYPE 2:1 Type rw Reset Value 0x0 Register Details Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. reserved 0 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits IBUF_DISABLE_MOD E 7 Type rw Reset Value 0x0 Register Details Description Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
Appendix B: Register Details Register DDRIOB_CLOCK Details Field Name Bits Type Reset Value Description reserved 31:12 rw 0x0 Reserved PULLUP_EN 11 rw 0x1 enables pullup on output 0: no pullup 1: pullup enabled OUTPUT_EN 10:9 rw 0x0 Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf TERM_DISABLE_MO DE 8 rw 0x0 Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the
Appendix B: Field Name INP_TYPE Bits 2:1 Type rw Reset Value 0x0 Register Details Description Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. reserved 0 rw 0x0 Reserved. Do not modify.
Appendix B: Access Type rw Reset Value 0x00000000 Description Drive and Slew controls for DQ pins of the DDR Interface Register Details Register DDRIOB_DRIVE_SLEW_DATA Details Value of this register is computed by EDK after taking into account the Silicon Revision and DDR Standard and can be found in the initialization TCL file or FSBL code. Values other than the one computed by EDK are not supported Field Name Bits Type Reset Value Description reserved 31:27 rw 0x0 Reserved. Do not modify.
Appendix B: Register Details Register (slcr) DDRIOB_DRIVE_SLEW_CLOCK Name DDRIOB_DRIVE_SLEW_CLOCK Relative Address 0x00000B68 Absolute Address 0xF8000B68 Width 32 bits Access Type rw Reset Value 0x00000000 Description Drive and Slew controls for Clock pins of the DDR Interface Register DDRIOB_DRIVE_SLEW_CLOCK Details Value of this register is computed by EDK after taking into account the Silicon Revision and DDR Standard and can be found in the initialization TCL file or FSBL code.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 12 rw 0x0 Reserved. Do not modify. reserved 11:10 rw 0x0 Reserved. Do not modify. REFIO_EN 9 rw 0x0 Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio reserved 8:7 rw 0x0 Reserved. Do not modify.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 22 rw 0x0 Reserved. Do not modify. reserved 21 rw 0x0 Reserved. Do not modify. UPDATE_CONTROL 20 rw 0x0 DCI Update Mode. Use the values in the Calibration Table. PREF_OPT2 19:17 rw 0x0 DCI Calibration. Use the values in the Calibration Table. reserved 16 rw 0x0 Reserved PREF_OPT1 15:14 rw 0x0 DCI Calibration. Use the values in the Calibration Table.
Appendix B: Register Details Register DDRIOB_DCI_STATUS Details Field Name Bits Type Reset Value Description reserved 31:14 ro 0x0 Reserved. Writes are ignored, read data is zero. DONE 13 rw 0x0 DCI done signal reserved 12 rw 0x0 Reserved. Do not modify. reserved 11 rw 0x0 Reserved. Do not modify. reserved 10 ro 0x0 Reserved. Do not modify. reserved 9 ro 0x0 Reserved. Do not modify. reserved 8 ro 0x0 Reserved. Do not modify. reserved 7 ro 0x0 Reserved.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description ecc_memcfg_1 0x00000404 13 rw 0x00000043 ECC Memory Configuation Register 1 ecc_memcommand1_1 0x00000408 25 rw 0x01300080 ECC Memory Command 1 Register 1 ecc_memcommand2_1 0x0000040C 25 rw 0x01E00585 ECC Memory Command 2 Register 1 ecc_addr0_1 0x00000410 32 ro 0x00000000 ECC Address 0 Register 1 ecc_addr1_1 0x00000414 24 ro 0x00000000 ECC Address 1 Register 1 ecc_value0_1 0x00000418
Appendix B: Field Name Bits ecc_int1_en 8 Type ro Reset Value 0x0 Register Details Description NAND Flash ECC interrupt enable setting: (ECC_INT_EN1) 0: Masked 1: Enabled reserved 7 ro 0x0 Reserved. Do not modify.
Appendix B: Description Register Details SMC configuration information Register memif_cfg Details Provides information on the configuration of the memory interface. You cannot read this register in the Reset state. The state of this register cannot be changed. Field Name Bits exclusive_monitors 17:16 Type ro Reset Value 0x1 Description Return the number of exclusive access monitor resources that are implemented in the SMC.
Appendix B: Width 7 bits Access Type wo Reset Value x Description Enable interrupts and lower power state Register Details Register memc_cfg_set Details The write-only memc_cfg_set enables the SMC to be changed to low-power state, and interrupts enabled. You cannot write to this register in the Reset state. Field Name Bits ecc_int_enable1 6 Type wo Reset Value x Description NAND Flash ECC interrupt enable: (ECC_INT_ENABLE1) 0: No change 1: Enable reserved 5 wo x Reserved.
Appendix B: Field Name Bits ecc_int_disable1 6 Type wo Reset Value x Register Details Description NAND Flash ECC interrupt disable: (ECC_INT_DISABLE1) 0: No change 1: Disable reserved 5 wo x Reserved. Do not modify. int_clr_1 4 wo x 0: No effect (INT_CLR1) 1: Clear SMC Interrupt 1 as an alternative to an AXI read int_clr_0 3 wo x 0: No effect (INT_CLR0) 1: Clear SMC Interrupt 0 as an alternative to an AXI read low_power_exit 2 wo x Exit low-power mode.
Appendix B: Field Name chip_select Bits 25:23 Type wo Reset Value x Register Details Description Select register bank to update and enable chip mode register access based on CMD_TYPE: (CHIP_SELECT) 000: SRAM/NOR chip select 0. 001: SRAM/NOR chip select 1. 100: NAND Flash. others: reserved. cmd_type 22:21 wo x Select the command type: (TYPE) 00: UpdateRegs and AXI 01: ModeReg 10: UpdateRegs 11: ModeReg and UpdateRegs reserved 20 wo x Reserved. Do not modify.
Appendix B: Field Name Set_t6 Bits 23:20 Type wo Reset Value x Register Details Description Timing parameter for SRAM/NOR, bit 20 only (other bits are ignored): (SET_T6) o For asynchronous multiplexed transfers this bit controls when the SMC asserts we_n: 0: assert we_n two mclk cycles after asserting cs_n. 1: assert we_n and cs_n together. Timing parameter for NAND Flash, bits 23:20: o Busy to RE timing (t_rr), minimum permitted value = 0.
Appendix B: Absolute Address 0xE000E018 Width 16 bits Access Type mixed Reset Value x Description Stage a write to an OpMode register Register Details Register set_opmode Details This write-only register is the holding register for the opmode_ Registers. You cannot write to it in either the Reset or low-power states. Field Name Bits Type Reset Value Description reserved 15:13 wo x Reserved. Do not modify. set_bls 12 wo x NAND Flash: reserved, write zero.
Appendix B: Field Name set_rd_bl Bits 5:3 Type wo Reset Value x (SET_RD_BL) Register Details Description NAND Flash: reserved, write zero. SRAM/NOR: value written to opmode (rd_bl field). Memory Burst Length: 000: 1 beat 001: 4 beats 010: 8 beats 011: 16 beats 100: 32 beats 101: continuous others: reserved reserved 2 wo x Reserved. Do not modify.
Appendix B: Field Name period Bits 3:0 Type rw Reset Value 0x0 Register Details Description Set the number of consecutive memory bursts that are permitted, prior to the SMC deasserting chip select to enable the PSRAM to initiate a refresh cycle.
Appendix B: Field Name Bits period 3:0 Type rw Reset Value 0x0 Register Details Description Set the number of consecutive memory bursts that are permitted, prior to the SMC deasserting chip select to enable the PSRAM to initiate a refresh cycle.
Appendix B: Field Name Bits Type Reset Value Register Details Description t_wc 7:4 ro 0xC Write cycle time, refer to SET_CYCLES register. t_rc 3:0 ro 0xC Read cycle time, refer to SET_CYCLES register.
Appendix B: Register Details Register (pl353) sram_cycles0_1 Name sram_cycles0_1 Software Name IF0_CHIP_1_CONFIG Relative Address 0x00000120 Absolute Address 0xE000E120 Width 21 bits Access Type ro Reset Value 0x0002B3CC Description SRAM/NOR chip select 1 timing, active Register sram_cycles0_1 Details There is an instance of this register for each SRAM chip supported.
Appendix B: Register Details Register opmode0_1 Details Field Name Bits address_match Type Reset Value Description 31:24 ro 0xE4 see 0x120 23:16 ro 0xFE see 0x120 15:13 ro 0x0 reserved 12 ro 0x0 reserved 11 ro 0x1 reserved 10 ro 0x0 The memory uses the burst address advance signal, baa_n, when set.
Appendix B: Description Register Details NAND Flash timing, active Register nand_cycles1_0 Details There is an instance of this register for each NAND chip supported. You cannot read the read-only nand_cycles Register in the Reset state Field Name Bits Type Reset Value Description t_rr 23:20 ro 0x2 BUSY to RE, refer to SET_CYCLES register. t_ar 19:17 ro 0x2 ID read time, refer to SET_CYCLES register. t_clr 16:14 ro 0x2 Page cycle time, refer to SET_CYCLES register.
Appendix B: Field Name Bits Type Reset Value Description reserved 10 ro 0x0 Reserved. Do not modify. reserved 9:7 ro 0x0 Reserved. Do not modify. reserved 6 ro 0x0 Reserved. Do not modify. reserved 5:3 ro 0x0 Reserved. Do not modify. reserved 2 ro 0x0 Reserved. Do not modify. mw 1:0 ro 0x1 Data bus width is 8 bits, see SET_OPMODE register.
Appendix B: Register Details Register user_config Details The user_config is write-only and controls the status of the user_config[7:0] signals. You can write to this register in all operating states. Field Name Bits user_config 7:0 Type wo Reset Value x Description This value sets the state of the user_config[7:0] outputs.
Appendix B: Field Name ecc_read Bits 29:25 Type ro Reset Value 0x0 (ECC_READ) Register Details Description Read flags for ECC blocks. Indicate whether the stored ECC value for each block has been read from memory: 0: not read 1: read Bit [29] Extra block (if used). Bit [28] Block 3. Bit [27] Block 2. Bit [26] Block 1. Bit [25] Block 0.
Appendix B: Field Name Bits ecc_status 6 Type ro Reset Value 0x0 Register Details Description Status of the ECC block: (ECC_STATUS) 0: idle 1: busy 5:0 raw_int_status ro 0x0 The interrupts are: Bit [5] Abort. (ECC_STATUS_RAW_I NT_STATUS) Bit [4] Extra block (if used). Bit [3] Block 3. Bit [2] Block 2. Bit [1] Block 1. Bit [0] Block 0. To clear the interrupt, write a 1 to the bit.
Appendix B: Field Name ecc_int_abort Bits 9 Type rw Reset Value 0x0 (ECC_MEMCFG_ECC_ INT_ABORT) ecc_int_pass Register Details Description Interrupt on ECC abort: 0: don't assert 1: assert 8 rw 0x0 (ECC_MEMCFG_ECC_ INT_PASS) Interrupt when a correct ECC value is read from memory: 0: don't assert 1: assert ecc_ignore_add_eight 7 rw 0x0 (ECC_MEMCFG_IGN ORE_ADD8) Use to indicate if A8 is output with the address, required to find the aligned start of blocks: 0: A8 is output 1: A8 is not output
Appendix B: Register Details Register (pl353) ecc_memcommand1_1 Name ecc_memcommand1_1 Relative Address 0x00000408 Absolute Address 0xE000E408 Width 25 bits Access Type rw Reset Value 0x01300080 Description ECC Memory Command 1 Register 1 Register ecc_memcommand1_1 Details The ecc_memcommand1 is read-write and contains the commands that the ECC block uses to detect the start of an ECC operation.
Appendix B: Register Details Register ecc_memcommand2_1 Details The ecc_memcommand2 Register is read-write and contains the commands that the ECC block uses to access different parts of a NAND page. The reset value is suitable for ONFI 1.0 compliant devices Field Name Bits nand_rd_col_change_e nd_valid Type Reset Value Description 24 rw 0x1 Use the end command 23:16 rw 0xE0 Use the NAND command to initiate a write.
Appendix B: Relative Address 0x00000414 Absolute Address 0xE000E414 Width 24 bits Access Type ro Reset Value 0x00000000 Description ECC Address 1 Register 1 Register Details Register ecc_addr1_1 Details The ecc_addr1 Register is read-only and contains the upper 24 bits of the ECC address.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 26:24 ro 0x0 Reserved, read undefined ecc_value 23:0 ro 0x0 ECC value of check result for block, depending on ECC configuration (ECC_VALUE) Register (pl353) ecc_value1_1 Name ecc_value1_1 Relative Address 0x0000041C Absolute Address 0xE000E41C Width 32 bits Access Type ro Reset Value 0x00000000 Description ECC Value 1 Register 1 Register ecc_value1_1 Details The five ecc_value Registers are rea
Appendix B: Absolute Address 0xE000E420 Width 32 bits Access Type ro Reset Value 0x00000000 Description ECC Value 2 Register 1 Register Details Register ecc_value2_1 Details The five ecc_value Registers are read-only and contain block information for the ECC. Note: writing any value to an ecc_value Register clears the ecc_int bit.
Appendix B: Field Name ecc_int Bits Type Reset Value Register Details Description 31 ro 0x0 Interrupt flag for this value 30 ro 0x0 Indicate if this value is valid 29 ro 0x0 Indicate if the ECC value has been read from memory 28 ro 0x0 Indicate if this value has failed 27 ro 0x0 Indicate if this block is correctable reserved 26:24 ro 0x0 Reserved, read undefined ecc_value 23:0 ro 0x0 ECC value of check result for block, depending on ECC configuration (ECC_VALUE_INT) ecc_
Appendix B: Register Details B.
Appendix B: Reset Value 0x00020000 Description SPI configuration register Register Details Register Config_reg0 Details Field Name Bits Type Reset Value Description reserved 31:18 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Field Name Bits BAUD_RATE_DIV 5:3 Type rw Reset Value 0x0 Register Details Description Master mode baud rate divisor controls the amount the spi_ref_clk is divided inside the SPI block 000: not supported 001: divide by 4 010: divide by 8 011: divide by 16 100: divide by 32 101: divide by 64 110: divide by 128 111: divide by 256 CLK_PH 2 rw 0x0 Clock phase (CPHA) 1: the SPI clock is inactive outside the word 0: the SPI clock is active outside the word CLK_POL 1 rw 0x0 Clock po
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write. TX_FIFO_underflow 6 wtc 0x0 TX FIFO underflow, write one to this bit location to clear.
Appendix B: Absolute Address Register Details spi0: 0xE0006008 spi1: 0xE0007008 Width 32 bits Access Type mixed Reset Value 0x00000000 Description Interrupt Enable register Register Intrpt_en_reg0 Details Field Name Bits Type Reset Value Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Register Details Register (SPI) Intrpt_dis_reg0 Name Intrpt_dis_reg0 Software Name IDR Relative Address 0x0000000C Absolute Address spi0: 0xE000600C spi1: 0xE000700C Width 32 bits Access Type mixed Reset Value 0x00000000 Description Interrupt disable register Register Intrpt_dis_reg0 Details Field Name Bits Type Reset Value Description reserved 31:7 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Field Name Bits MODE_FAIL 1 Type wo Reset Value 0x0 Register Details Description ModeFail interrupt (IXR_MODF) enable 1: disables the interrupt 0: no effect RX_OVERFLOW 0 wo 0x0 Receive Overflow interrupt enable (IXR_RXOVR) 1: disables the interrupt 0: no effect Register (SPI) Intrpt_mask_reg0 Name Intrpt_mask_reg0 Software Name IMR Relative Address 0x00000010 Absolute Address spi0: 0xE0006010 spi1: 0xE0007010 Width 32 bits Access Type ro Reset Value 0x00000000 De
Appendix B: Field Name TX_FIFO_full Bits 3 Type ro Reset Value 0x0 Register Details Description TX FIFO full (IXR_TXFULL) enable 1: interrupt is disabled 0: interrupt is enabled TX_FIFO_not_full 2 ro 0x0 TX FIFO not full (IXR_TXOW) enable 1: interrupt is disabled 0: interrupt is enabled MODE_FAIL 1 ro 0x0 ModeFail interrupt (IXR_MODF) enable 1: interrupt is disabled 0: interrupt is enabled RX_OVERFLOW 0 ro 0x0 Receive Overflow interrupt enable (IXR_RXOVR) 1: interrupt is disable
Appendix B: Software Name DR Relative Address 0x00000018 Absolute Address spi0: 0xE0006018 Register Details spi1: 0xE0007018 Width 32 bits Access Type rw Reset Value 0x00000000 Description Delay Register Register Delay_reg0 Details Field Name d_nss Bits 31:24 Type rw Reset Value 0x0 Description Delay in SPI REFERENCE CLOCK or ext_clk cycles for the length that the master mode chip select outputs are de-asserted between words when cpha=0.
Appendix B: Register Details Register Tx_data_reg0 Details Field Name TX_FIFO_data Bits 31:0 Type wo Reset Value 0x0 Description Data to TX FIFO. Valid data bits are [7:0].
Appendix B: Register Details Register Slave_Idle_count_reg0 Details Field Name Bits Type Reset Value Description reserved 31:8 ro 0x0 Reserved, read as zero, ignored on write. Slave_Idle_coun 7:0 rw 0xFF SPI in slave mode detects a start only when the external SPI master serial clock (sclk_in) is stable (quiescent state) for SPI REFERENCE CLOCK cycles specified by slave idle count register or when the SPI is deselected.
Appendix B: Register Details Register RX_thres_reg0 Details Field Name Bits Threshold_of_RX_FIF O 31:0 Type rw Reset Value 0x1 Description Defines the level at which the RX FIFO not empty interrupt is generated Register (SPI) Mod_id_reg0 Name Mod_id_reg0 Relative Address 0x000000FC Absolute Address spi0: 0xE00060FC spi1: 0xE00070FC Width 32 bits Access Type ro Reset Value 0x00090106 Description Module ID register Register Mod_id_reg0 Details Field Name Bits Type Reset Value Descri
Appendix B: Register Details B.
Appendix B: Field Name IRQLN Bits 8:7 Type rw Reset Value 0x3 Register Details Description Interrupt request length - selects the number of pclk cycles during which an interrupt request is held active after it is invoked: 00 = 4 01 = 8 10 = 16 11 = 32 reserved 6:4 rw 0x4 Reserved reserved 3 waz 0x0 Should be zero (sbz) IRQEN 2 rw 0x0 Interrupt request enable - if set, the watchdog will issue an interrupt request when the counter reaches zero, if WDEN = 1.
Appendix B: Field Name Bits Type Reset Value Register Details Description CRV 13:2 rw 0xFFF Counter restart value - the counter is restarted with the value 0xNNNFFF, where NNN is the value of this field. CLKSEL 1:0 rw 0x0 Counter clock prescale - selects the prescaler division ratio: 00 = pclk divided by 8 01 = pclk divided by 64 10 = pclk divided by 512 11 = pclk divided by 4096 Note: If a restart signal is received the prescaler should be reset.
Appendix B: Register Details Register STATUS Details Field Name WDZ Bits 0 Type ro Reset Value 0x0 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.11) September 27, 2016 Description set when the watchdog reaches zero count www.xilinx.
Appendix B: Register Details B.
Appendix B: Register Name Interrupt_Register_1 Address 0x00000054 Width Type 6 clronr d Reset Value 0x00000000 Register Details Description Counter 1 Interval, Match, Overflow and Event interrupts Interrupt_Register_2 0x00000058 6 clronr d 0x00000000 Counter 2 Interval, Match, Overflow and Event interrupts Interrupt_Register_3 0x0000005C 6 clronr d 0x00000000 Counter 3 Interval, Match, Overflow and Event interrupts Interrupt_Enable_1 0x00000060 6 rw 0x00000000 ANDed with correspon
Appendix B: Register Details Register Clock_Control_1 Details Field Name Bits Ex_E Type Reset Value 6 rw 0x0 External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input. 5 rw 0x0 Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is pclk.
Appendix B: Register Details Register (ttc) Clock_Control_3 Name Clock_Control_3 Relative Address 0x00000008 Absolute Address ttc0: 0xF8001008 ttc1: 0xF8002008 Width 7 bits Access Type rw Reset Value 0x00000000 Description Clock Control register Register Clock_Control_3 Details Field Name Bits Ex_E Type Reset Value 6 rw 0x0 External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input.
Appendix B: Register Details Register Counter_Control_1 Details Field Name Wave_pol Bits Type Reset Value Description 6 rw 0x0 Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. 5 rw 0x1 Output waveform enable, active low.
Appendix B: Register Details Register Counter_Control_2 Details Field Name Bits Wave_pol Type Reset Value 6 rw 0x0 Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. 5 rw 0x1 Output waveform enable, active low.
Appendix B: Register Details Register Counter_Control_3 Details Field Name Bits Wave_pol Type Reset Value 6 rw 0x0 Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. 5 rw 0x1 Output waveform enable, active low.
Appendix B: Register Details Register Counter_Value_1 Details Field Name Bits Value 15:0 Type ro Reset Value 0x0 Description At any time, a Timer Counter's count value can be read from its Counter Value Register.
Appendix B: Register Details Register (ttc) Interval_Counter_1 Name Interval_Counter_1 Software Name INTERVAL_VAL Relative Address 0x00000024 Absolute Address ttc0: 0xF8001024 ttc1: 0xF8002024 Width 16 bits Access Type rw Reset Value 0x00000000 Description Interval value Register Interval_Counter_1 Details Field Name Bits Interval 15:0 Type rw Reset Value 0x0 Description If interval is enabled, this is the maximum value that the counter will count up to or down from.
Appendix B: Absolute Address Register Details ttc0: 0xF800102C ttc1: 0xF800202C Width 16 bits Access Type rw Reset Value 0x00000000 Description Interval value Register Interval_Counter_3 Details Field Name Bits Interval 15:0 Type rw Reset Value 0x0 Description If interval is enabled, this is the maximum value that the counter will count up to or down from.
Appendix B: Access Type rw Reset Value 0x00000000 Description Match value Register Details Register Match_1_Counter_2 Details Field Name Match Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.
Appendix B: Description Register Details Match value Register Match_2_Counter_1 Details Field Name Match Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.
Appendix B: Register Details Register Match_2_Counter_3 Details Field Name Match Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.
Appendix B: Register Details Register Match_3_Counter_2 Details Field Name Match Bits 15:0 Type rw Reset Value 0x0 Description When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.
Appendix B: Register Details Register Interrupt_Register_1 Details Field Name Bits Type Reset Value Description Ev 5 clronr d 0x0 Event timer overflow interrupt Ov 4 clronr d 0x0 Counter overflow 3 clronr d 0x0 Match 3 interrupt 2 clronr d 0x0 Match 2 interrupt 1 clronr d 0x0 Match 1 interrupt 0 clronr d 0x0 Interval interrupt (IXR_CNT_OVR) M3 (IXR_MATCH_2) M2 (IXR_MATCH_1) M1 (IXR_MATCH_0) Iv (IXR_INTERVAL) Register (ttc) Interrupt_Register_2 Name Interrupt_Register_2 Re
Appendix B: Field Name M1 Bits Reset Value Description 1 clronr d 0x0 Match 1 interrupt 0 clronr d 0x0 Interval interrupt (IXR_MATCH_0) Iv Type (IXR_INTERVAL) Register Details Register (ttc) Interrupt_Register_3 Name Interrupt_Register_3 Relative Address 0x0000005C Absolute Address ttc0: 0xF800105C ttc1: 0xF800205C Width 6 bits Access Type clronrd Reset Value 0x00000000 Description Counter 3 Interval, Match, Overflow and Event interrupts Register Interrupt_Register_3 Details F
Appendix B: Absolute Address Register Details ttc0: 0xF8001060 ttc1: 0xF8002060 Width 6 bits Access Type rw Reset Value 0x00000000 Description ANDed with corresponding Interrupt Register Register Interrupt_Enable_1 Details Field Name IEN Bits 5:0 Type rw Reset Value 0x0 Description Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.
Appendix B: Width 6 bits Access Type rw Reset Value 0x00000000 Description ANDed with corresponding Interrupt Register Details Register Register Interrupt_Enable_3 Details Field Name IEN Bits 5:0 Type rw Reset Value 0x0 Description Enables for bits 05:00 in Interrupt Register: corresponding bits must be set to enable the interrupt.
Appendix B: Absolute Address Register Details ttc0: 0xF8001070 ttc1: 0xF8002070 Width 3 bits Access Type rw Reset Value 0x00000000 Description Enable, pulse and overflow Register Event_Control_Timer_2 Details Field Name Bits Type Reset Value Description E_Ov 2 rw 0x0 When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.
Appendix B: Field Name Bits Type Reset Value Register Details Description E_Lo 1 rw 0x0 When this bit is high, the timer counts pclk cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk. E_En 0 rw 0x0 Enable timer: when this bit is high, the event timer is enabled.
Appendix B: Register Details Register (ttc) Event_Register_3 Name Event_Register_3 Relative Address 0x00000080 Absolute Address ttc0: 0xF8001080 ttc1: 0xF8002080 Width 16 bits Access Type ro Reset Value 0x00000000 Description pclk cycle count for event Register Event_Register_3 Details Field Name Event Bits 15:0 Type ro Reset Value 0x0 Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.
Appendix B: Register Details B.
Appendix B: Software Name CR Relative Address 0x00000000 Absolute Address uart0: 0xE0000000 Register Details uart1: 0xE0001000 Width 32 bits Access Type mixed Reset Value 0x00000128 Description UART Control Register Register Control_reg0 Details The UART Control register is used to enable and reset the transmitter and receiver blocks. It also controls the receiver timeout and the transmission of breaks.
Appendix B: Field Name RXEN Bits 2 Type rw Reset Value 0x0 Register Details Description Receive enable: (RX_EN) 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. TXRES 1 rw 0x0 Software reset for Tx data path: (TXRST) 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
Appendix B: Field Name CHMODE Bits 9:8 Type rw Reset Value 0x0 Register Details Description Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback NBSTOP 7:6 rw 0x0 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.
Appendix B: Reset Value 0x00000000 Description Interrupt Enable Register Register Details Register Intrpt_en_reg0 Details This write only register is used to enable interrupts. When any bit is written high, the corresponding interrupt is enabled. Writing a low to any bit has no effect. Field Name Bits Type Reset Value reserved 31:13 ro 0x0 TOVR 12 wo 0x0 Description Reserved, read as zero, ignored on write.
Appendix B: Field Name REMPTY Bits 1 Type wo Reset Value 0x0 Register Details Description Receiver FIFO Empty interrupt: (IXR_RXEMPTY) 0: no affect 1: enable (clears mask = 0) RTRIG 0 wo 0x0 Receiver FIFO Trigger interrupt: (IXR_RXOVR) 0: no affect 1: enable (clears mask = 0) Register (UART) Intrpt_dis_reg0 Name Intrpt_dis_reg0 Software Name IDR Relative Address 0x0000000C Absolute Address uart0: 0xE000000C uart1: 0xE000100C Width 32 bits Access Type mixed Reset Value 0x00000000
Appendix B: Field Name TIMEOUT Bits 8 Type wo Reset Value 0x0 (IXR_TOUT) Register Details Description Receiver Timeout Error interrupt: 0: no affect 1: disable (sets mask = 1) PARE 7 wo 0x0 (IXR_PARITY) Receiver Parity Error interrupt: 0: no affect 1: disable (sets mask = 1) FRAME 6 wo 0x0 (IXR_FRAMING) Receiver Framing Error interrupt: 0: no affect 1: disable (sets mask = 1) ROVR 5 wo 0x0 (IXR_OVER) Receiver Overflow Error interrupt: 0: no affect 1: disable (sets mask = 1) TFUL 4
Appendix B: Description Register Details Interrupt Mask Register Register Intrpt_mask_reg0 Details This read only register, indicates the current state of the interrupts mask. A high value indicates the interrupt is unmasked and therefore is enabled to generate an interrupt. A low value indicates the interrupt is masked and therefore is disabled from generating an interrupt. Field Name Bits Type Reset Value Description reserved 31:13 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Field Name RFUL Bits 2 Type ro Reset Value 0x0 Register Details Description Receiver FIFO Full interrupt mask status: (IXR_RXFULL) 0: interrupt is disabled 1: interrupt is enabled REMPTY 1 ro 0x0 Receiver FIFO Empty interrupt mask status: (IXR_RXEMPTY) 0: interrupt is disabled 1: interrupt is enabled RTRIG 0 ro 0x0 Receiver FIFO Trigger interrupt mask status: (IXR_RXOVR) 0: interrupt is enabled 1: interrupt is enabled Register (UART) Chnl_int_sts_reg0 Name Chnl_int_sts_re
Appendix B: Field Name TNFUL Bits 11 Type wtc Reset Value 0x0 Register Details Description Transmitter FIFO Nearly Full interrupt mask status: This event is triggered whenever a new word is pushed into the transmit FIFO causing the fill level to be such that there is not enough space for a further write of the number of bytes currently specified in the WSIZE bits in the Mode register. If this further write were currently attempted it would cause an overflow.
Appendix B: Field Name ROVR Bits 5 Type wtc Reset Value 0x0 (IXR_OVER) Register Details Description Receiver Overflow Error interrupt mask status: This event is triggered whenever the contents of the receiver shift register have not yet been transferred to the receiver FIFO and a new start bit is detected. This may be due to the FIFO being full, or due to excessive clock boundary delays.
Appendix B: Absolute Address Register Details uart0: 0xE0000018 uart1: 0xE0001018 Width 32 bits Access Type mixed Reset Value 0x0000028B Description Baud Rate Generator Register. Register Baud_rate_gen_reg0 Details The read/write baud rate generator control register controls the amount by which to divide sel_clk to generate the bit rate clock enable, baud_sample. Field Name Bits Type Reset Value Description reserved 31:16 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Register Details Register (UART) Rcvr_FIFO_trigger_level0 Name Rcvr_FIFO_trigger_level0 Software Name RXWM Relative Address 0x00000020 Absolute Address uart0: 0xE0000020 uart1: 0xE0001020 Width 32 bits Access Type mixed Reset Value 0x00000020 Description Receiver FIFO Trigger Level Register Register Rcvr_FIFO_trigger_level0 Details The read/write Receiver FIFO Trigger Level Register is used to set the value at which the receiver FIFO triggers an interrupt event.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:6 ro 0x0 Reserved, read as zero, ignored on write. FCM 5 rw 0x0 Automatic flow control mode: 0: disable Transmission is continuous regardless of the value of the EMIOUARTxCTSN input, and the EMIOUARTxRTSN output is driven completely under software control.
Appendix B: Register Details information. These bits are set to logic 1 whenever a control input from the modem changes state. In the default configuration, these delta bits are all cleared simultaneously when this register is read. This may be parameterised at compile time such that a one must be written to a bit in order to clear it and a read has no effect. Field Name Bits Type Reset Value Description reserved 31:9 ro x Reserved, read as zero, ignored on write.
Appendix B: Field Name Bits DDSR 1 Type wtc Reset Value x (MEDEMSR_DSRX) Register Details Description Delta Data Set Ready status: Indicates a change in state of the EMIOUARTxDSRN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred DCTS 0 wtc x (MEDEMSR_CTSX) Delta Clear To Send status: Indicates a change in state of the EMIOUARTxCTSN input since this bit was last cleared.
Appendix B: Field Name Bits Type Reset Value Register Details Description reserved 31:15 ro 0x0 Reserved, read as zero, ignored on write. TNFUL 14 ro 0x0 Transmitter FIFO Nearly Full continuous status: This indicates that there is not enough space for the number of bytes currently specified in the WSIZE bits in the Mode register. If a write were currently attempted it would cause an overflow.
Appendix B: Field Name REMPTY Bits 1 Type ro Reset Value 0x0 Register Details Description Receiver FIFO Full continuous status: (RXEMPTY) 0: Rx FIFO is not empty 1: Rx FIFO is empty RTRIG 0 ro 0x0 Receiver FIFO Trigger continuous status: (RXOVR) 0: Rx FIFO fill level is less than RTRIG 1: Rx FIFO fill level is greater than or equal to RTRIG Register (UART) TX_RX_FIFO0 Name TX_RX_FIFO0 Software Name FIFO Relative Address 0x00000030 Absolute Address uart0: 0xE0000030 uart1: 0xE0001030
Appendix B: Register Details Register Baud_rate_divider_reg0 Details The baud rate divider register controls how much baud_sample is divided by to generate the baud rate clock enables, baud_rx_rate and baud_tx_rate. Field Name Bits Type Reset Value Description reserved 31:8 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Width 32 bits Access Type mixed Reset Value 0x00000020 Description Transmitter FIFO Trigger Level Register Register Details Register Tx_FIFO_trigger_level0 Details The read/write Transmitter FIFO Trigger Level Register is used to set the value at which the transmitter FIFO triggers an interrupt event. Field Name Bits Type Reset Value Description reserved 31:6 ro 0x0 Reserved, read as zero, ignored on write.
Appendix B: Register Details B.
Appendix B: Register Name Address Width Type Reset Value Register Details Description USBCMD 0x00000140 24 mixed 0x00080000 USB Commands (EHCI extended) USBSTS 0x00000144 26 mixed 0x00000000 Interrupt/Raw Status (EHCI extended) (Host/Device) USBINTR 0x00000148 26 mixed 0x00000000 Interrrupts and Enables FRINDEX 0x0000014C 14 rw 0x00000000 Frame List Index PERIODICLISTBASE_ DEVICEADDR 0x00000154 32 mixed 0x00000000 Host/Device Address dual-use ASYNCLISTADDR_E NDPOINTLIST
Appendix B: Register Name Address Width Type Reset Value Register Details Description ENDPTCTRL6 0x000001D8 24 mixed 0x00000000 Endpoints 1 to 11 (Device mode) ENDPTCTRL7 0x000001DC 24 mixed 0x00000000 Endpoints 1 to 11 (Device mode) ENDPTCTRL8 0x000001E0 24 mixed 0x00000000 Endpoints 1 to 11 (Device mode) ENDPTCTRL9 0x000001E4 24 mixed 0x00000000 Endpoints 1 to 11 (Device mode) ENDPTCTRL10 0x000001E8 24 mixed 0x00000000 Endpoints 1 to 11 (Device mode) ENDPTCTRL11 0x00
Appendix B: Relative Address 0x00000004 Absolute Address usb0: 0xE0002004 Register Details usb1: 0xE0003004 Width 12 bits Access Type ro Reset Value 0x00000083 Description Misc IP config constants, read-only Register HWGENERAL Details General hardware parameters provided by the IP supplier and defined by Xilinx for synthesis. Hardwired (constant value). Bits [31:12] are reserved. Field Name SM Bits 11:10 Type ro Reset Value 0x0 Description VUSB_HS_PHY_SERIAL constant.
Appendix B: Description Register Details Host Mode IP config constants, read-only Register HWHOST Details Field Name TTPER Bits 31:24 Type ro Reset Value 0x10 Description VUSB_HS_TT_PERIODIC_CONTEXTS constant. 0x010: Sixteen periodic contexts in TT. TTASY 23:16 ro 0x2 VUSB_HS_TT_ASYNC_CONTEXTS constant. 0x02: Two asynchronous contexts in TT. NPORT 15:4 ro 0x0 reserved 3:1 ro 0x0 VUSB_HS_NUM_PORT constant. 000: one downstream port supported. HC 0 ro 0x1 VUSB_HS_HOST constant.
Appendix B: Access Type ro Reset Value 0x80060A10 Description TxBuffer IP config constants, read-only Register Details Register HWTXBUF Details Field Name Bits Type Reset Value Description reserved 31 ro 0x1 reserved reserved 30:24 ro 0x0 reserved TXCHANADD 23:16 ro 0x6 VUSB_HS_TX_CHAN_ADD constant. 0x06: Six address bits for each 64-byte endpoint TxBuffer (VBUS_HS_TX_CHAN = 64). TXADD 15:8 ro 0xA VUSB_HS_TX_ADD constant. 0x0A0: 10-bit address. TxBuffer size is 768.
Appendix B: Register Details Register (usb) GPTIMER0LD Name GPTIMER0LD Relative Address 0x00000080 Absolute Address usb0: 0xE0002080 usb1: 0xE0003080 Width 24 bits Access Type rw Reset Value 0x00000000 Description GP Timer 0 Load Value Register GPTIMER0LD Details Field Name GPTLD Bits 23:0 Type rw Reset Value 0x0 Description General Purpose Timer Load Value. This field is loaded into the usb.GPTIMERxCTRL [GPTCNT] countdown timer.
Appendix B: Field Name GPTRUN Bits 31 Type rw Reset Value 0x0 Register Details Description General Purpose Timer Enable. 0: disable. 1: enable. The setting of [GPTRUN] will not have an effect on the [GPTCNT] counter value. GPTRST 30 wo 0x0 General Purpose Timer Reset. Write 1 to reload. 0: no affect. 1: Reload the [GPTCNT] with the value in [GPTLD]. GPTMODE 29:25 ro 0x0 reserved 24 rw 0x0 Select Countdown Timer mode. 0: One Shot (single timer countdown).
Appendix B: Absolute Address Register Details usb0: 0xE000208C usb1: 0xE000308C Width 32 bits Access Type mixed Reset Value 0x00000000 Description GP Timer 1 Control Register GPTIMER1CTRL Details Field Name Bits Type Reset Value Description GPTRUN 31 rw 0x0 Refer to GPTIMER0CTRL [GPTRUN]. GPTRST 30 wo 0x0 Refer to GPTIMER0CTRL [GPTRST]. 29:25 ro 0x0 reserved GPTMODE 24 rw 0x0 Refer to GPTIMER0CTRL [GPTMODE]. GPTCNT 23:0 rw 0x0 Refer to GPTIMER0CTRL [GPTCNT].
Appendix B: Access Type ro Reset Value 0x01000040 Description EHCI Addr Space and HCI constants, read-only Register Details Register CAPLENGTH_HCIVERSION Details Field Name Bits Type Reset Value Description HCIVERSION 31:16 ro 0x100 VUSB_HS_HCIVERSION constant. Host Mode (EHCI). Read-only. CAPLENGTH 15:0 ro 0x40 Address space taken by the Capability registers. Host Mode (EHCI). Read-only.
Appendix B: Field Name N_PCC Bits 11:8 Type ro Reset Value 0x0 Register Details Description Ports supported by each Companion Controller (EHCI constant). 0: no companion controller hardware refer to the embeded Transaction Translator (TT). reserved 7:5 ro 0x0 PPC 4 ro 0x1 reserved VBUS Power Control (EHCI constant). 1: signal avaiable via EMIO, see PORTSC1 [PP]. N_PORTS 3:0 ro 0x1 Downstream ports (EHCI constant). 1: one downstream port.
Appendix B: Field Name PFL Bits 1 Type ro Reset Value 0x1 Register Details Description Programmable Frame List sizes (Host mode). Software can specify the size of the frame list for the periodic schedule. Configure the size using the usb.USBCMD [FS2] [FS0] Frame List Size field: 8, 16, 32, .... 512, 1024. ADC 0 ro 0x0 0: 32-bit system memory address.
Appendix B: Field Name Bits Type Reset Value Register Details Description HC 8 ro 0x1 1: the controller supports EHCI compatible mode. DC 7 ro 0x1 1: the controller supports Device mode. 6:5 ro 0x0 reserved 4:0 ro 0xC Number of endpoints supported in Device mode. DEN 1100: 12 endpoints; control EP0 plus EP {11:1}.
Appendix B: Field Name SUTW Bits 13 Type rw Reset Value 0x0 Register Details Description Setup TripWire (Device mode). This semaphore is between the DCD and the hardware for extracting setup data from QH with out any corruption. Refer to the chapter text for usage. reserved 12 ro 0x0 reserved ASPE 11 rw 0x0 Asynchronous Schedule Park Mode Enable (EHCI). This bit enables/disables the Asynchronous Schedule Park Mode if Asynchronous Park Capability bit in HCCPARAMS is one.
Appendix B: Field Name FS0 Bits 3:2 Type rw Reset Value 0x0 (FS01) Register Details Description Frame List Size (EHCI extended). usb.USBCMD [15] [3] [2] bits: 000: 1024 elements (4096 bytes) 001: 512 elements (2048 bytes) ... 111: 8 elements (32 bytes) RST 1 rw 0x0 Controller Reset and Status (ECHI) (Host and Device mode). RS 0 rw 0x0 Run/Stop (ECHI) (Host and Device modes). Device Mode: 0: the controller halts activity after the current packet transfer is complete.
Appendix B: Field Name TI1 Bits 25 Type rw Reset Value 0x0 (IXR_TI1) TI0 Register Details Description GP timer 1 raw interrupt (Host/Device). Refer to [TI0] bit description. 24 rw 0x0 (IXR_TI0) GP timer 0 raw interrupt status (Host/Device). Read -0: inactive. 1: active. Hardware sets this bit = 1 when the counter in the GPTIMER0CTRL register transitions to zero. Write -0: no effect. 1: clear this bit to 0. reserved 23:20 ro 0x0 reserved UPI 19 rw 0x0 Host Periodic raw interrupt status.
Appendix B: Field Name AS Bits 15 Type ro Reset Value 0x0 (IXR_AS) Register Details Description Async Schedule Processing Status (EHCI) (Host mode), read-only. 0: inactive. 1: active, async schedule is enabled. Note: This status bit is used with the usb.USBCMD [ASE] enable bit. When the software sets usb.USBCMD [ASE], this bit reflects when HW really enabled processing async schedule. PS 14 ro 0x0 (IXR_PS) Periodic Schedule Processing Status (EHCI) (Host mode), read-only. 0: inactive.
Appendix B: Field Name SRI Bits 7 Type rw Reset Value 0x0 (IXR_SR) Register Details Description SOF Received (Device and Host mode). Indicates start-of-frame detected. 0: not detected 1: SOF detected by hardware (write 1 to clear) Device mode -When the controller detects an SOF on the ULPI bus, this bit is set. This normally occurs at 1 ms or 125 us intervals. Host mode -The controller sets this bit every 125 us. Host software can use this tic for a time base.
Appendix B: Field Name PCI Bits 2 Type rw Reset Value 0x0 Register Details Description Port Change Detect. The Controller in host mode sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. (IXR_PC) The Controller in device mode sets this bit to a one when it detects resume signaling or the port controller enters the full or high-speed operational state.
Appendix B: Field Name TIE1 Bits 25 Type rw Reset Value 0x0 (IXR_TI1) Register Details Description GP Timer 1 Interrupt Enable (Host/Device). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [TI1]. TIE0 24 rw 0x0 (IXR_TI0) GP Timer 0 Interrupt Enable (Host/Device). 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [TI0]. reserved 23:20 ro 0x0 reserved UPEI 19 rw 0x0 Host Periodic Interrupt Enable (Host mode). (IXR_UP) 0: disable. 1: enable.
Appendix B: Field Name URE Bits 6 Type rw Reset Value 0x0 Register Details Description USB Reset Received Interrupt Enable (Device mode). (IXR_UR) 0: disable. 1: enable interrupt on receiving USB reset. Refer to raw interrupt status: USBSTS [URI]. AAE 5 rw 0x0 Async Advance Interrupt Enable (EHCI). (IXR_AA) 0: disable. 1: enable. Refer to raw interrupt status: USBSTS [AAI]. SEE 4 rw 0x0 System Error Interrupt Enable (EHCI). 0: disable. 1: enable.
Appendix B: Reset Value 0x00000000 Description Frame List Index Register Details Register FRINDEX Details This register is used by the host controller to index the periodic frame list. The register updates every 125 us (once each micro-frame). Field Name FRINDEX Bits 13:0 Type rw Reset Value 0x0 Description Frame Index (EHCI) (Host and Device mode). Host mode -Read: current frame index value. Write: set the frame index value. Device mode -Read-only: frame index from received packet.
Appendix B: Field Name Bits PERBASE_USBADRA 31:25 Type rw Reset Value 0x0 Register Details Description Host mode ---- Periodic List Base Address. Memory address bits [31:25]. Device Mode ---- Device Address Advance. When this bit is '0b', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register.
Appendix B: Field Name Bits ASYBASE_EPBASE 31:11 Type rw Reset Value 0x0 Register Details Description Host mode -- Async List Base Address. Memory address bits [31:11] point to the Queue Heads (QH) . Refer to [ASYBASE} bit field for [10:5] address bits. Device Mode -- Endpoint List Base Address. Memory address bits [31:11] point to the Queue Heads (QH). There are unused memory locations. The stride for the base address is for a 16-endpoint model using both IN and OUT functions.
Appendix B: Field Name Bits Type Reset Value Register Details Description TTAS 1 rw 0x0 Embedded TT Asynchronous Buffers Clear. This field will clear all pending transactions in the embedded TT Asynchronous Buffer(s). The clear will take as much time as necessary to clear buffer without interfering with a transaction in progress. TTAC will return to zero after being set by software only after the actual clear occurs. The TT supports up to two contexts.
Appendix B: Field Name TXPBURST Bits 16:8 Type rw Reset Value 0x10 Register Details Description Programmable TX Burst Length. (TX) Default is the constant VUSB_HS_TX_BURST. This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus. If field AHBBRST of register SBUSCFG is different from zero, this field TXPBURST will return the value of the INCRx length. Supported values are integer values from 4 to 128.
Appendix B: Field Name TXFIFOTHRES Bits 21:16 Type rw Reset Value 0x0 (BURST) Register Details Description FIFO Burst Threshold: This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance.
Appendix B: Register Details Register (usb) TXTTFILLTUNING Name TXTTFILLTUNING Relative Address 0x00000168 Absolute Address usb0: 0xE0002168 usb1: 0xE0003168 Width 13 bits Access Type mixed Reset Value 0x00000000 Description TT TX latency FIFO Register TXTTFILLTUNING Details This register provides a function similar to TXFILLTUNING except there is no equivalent to TXFIFOTHRES because the TT TX latency FIFO is always loaded in a single burst.
Appendix B: Field Name Bits Type Reset Value Register Details Description IC8 31 ro 0x0 Inter-Chip transceiver enable 8. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC8. Writing a '1' to each bit selects the IC_USB interface for that port.
Appendix B: Field Name IC_VDD5 Bits 18:16 Type ro Reset Value 0x0 Register Details Description Inter-Chip voltage selection 5 It selects which voltage is being supplied to the peripheral through each port This field is read-only and set to '000b' in case of device mode operation. This field is read-only and set to '000b' in case of Single port host controller. IC4 15 ro 0x0 Inter-Chip transceiver enable 4. These bits enables the Inter-Chip transceiver for each port (for the MPH case).
Appendix B: Field Name IC1 Bits 3 Type rw Reset Value 0x0 Register Details Description Inter-Chip transceiver enable 1. These bits enables the Inter-Chip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to '011b' in the PORTSC1. Writing a '1' to each bit selects the IC_USB interface for that port. If the Controller is not a MPH implementation, IC8 to IC2 will be '0' and Read-Only. IC_VDD1 2:0 rw 0x0 Inter-Chip voltage selection 1 -- Host mode.
Appendix B: Field Name ULPIWU Bits 31 Type rw Reset Value 0x0 (WU) Register Details Description ULPI Wake Up Operation. Write: 0: no affect. 1: execute the Wake Up operation (no undoing). Read: 0: operation complete. 1: operation in-progress. Note: Do not issue a ULPI Wake Up and ULPI Read/Write (via Viewport operation) with the same register write. ULPIRUN 30 rw 0x0 (RUN) ULPI Viewport Transaction. Write: 0: no affect. 1: execute the ULPI viewport transaction (no undoing).
Appendix B: Register Details Register (usb) ENDPTNAK Name ENDPTNAK Software Name EPNAKISR Relative Address 0x00000178 Absolute Address usb0: 0xE0002178 usb1: 0xE0003178 Width 32 bits Access Type wtc Reset Value 0x00000000 Description Endpoint NAK (Device mode) Register ENDPTNAK Details Field Name EPTN Bits 31:16 Type wtc Reset Value 0x0 Description TX Endpoint NAK (Device mode).
Appendix B: Access Type rw Reset Value 0x00000000 Description Endpoint NAK (Device mode) Register Details Register ENDPTNAKEN Details Field Name EPTNE Bits 31:16 Type rw Reset Value 0x0 Description TX Endpoint NAK Enable (Device mode). 0: disable. 1: enable. Each bit is an enable bit for the corresponding TX Endpoint NAK. If NAK is enabled and the corresponding TX Endpoint NAK bit is set, then the NAK Interrupt bit is set. Bit[16]: Endpoint 0. Bit[17]: Endpoint 1. ... Bit[28]: Endpoint 12.
Appendix B: Register Details Register CONFIGFLAG Details Field Name Bits reserved 31:0 Type ro Reset Value 0x1 Description reserved Register (usb) PORTSC1 Name PORTSC1 Software Name PORTSCR1 Relative Address 0x00000184 Absolute Address usb0: 0xE0002184 usb1: 0xE0003184 Width 32 bits Access Type mixed Reset Value 0x8C000004 Description Port Status & Control Register PORTSC1 Details The Controller implement one The number of port registers implemented by a particular instantiation is
Appendix B: Field Name PFSC Bits 24 Type rw Reset Value 0x0 (PORTSCR_PFSC) Register Details Description Port Force Full Speed Connect -- Debug. 0: ???? (default) 1: write a 1 to force the port to only connect at Full Speed. Writing a 1 disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. PHCD 23 ro 0x0 (PORTSCR_PHCD) PHY Low Power Clock Disable - RW. Default = 0b.
Appendix B: Field Name PTC Bits 19:16 Type rw Reset Value 0x0 (PORTSCR_PTC) Register Details Description Port Test Control. 0000: Normal operation. All others are test modes: 0001: J_STATE 0010: K_STATE 0011: SE0 (host) / NAK (device) 0100: Packet 0101: FORCE_ENABLE_HS 0110: FORCE_ENABLE_FS 0111: FORCE_ENABLE_LS Others: reserved PIC 15:14 rw 0x0 (PORTSCR_PIC) Port Indicator Control outputs (EHCI) (Host mode). 00: Port indicators are off.
Appendix B: Field Name HSP Bits 9 Type ro Reset Value 0x0 (PORTSCR_HSP) Register Details Description High-Speed Port status (Host and Device mode). 0: LS or FS mode 1: HS mode Note: [HSP] is redundant with [PSPD]. PR 8 rw 0x0 (PORTSCR_PR) Port Reset - RW. Default = 0b. This field is zero if Port Power(PP) is '0'. Host mode: 1=Port is in Reset. 0=Port is not in Reset. Device Mode: This bit is a read only status bit.
Appendix B: Field Name PEC Bits 3 Type wtc Reset Value 0x0 (PORTSCR_PEC) Register Details Description Port Enabled Change If set to '1' indicates a Port Enabled/Disabled status change. Host mode: For the root hub, this bit gets set to a '1' only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a '1' to it. This field is '0' if Port Power(PP) is '0'.
Appendix B: Field Name CSC Bits 1 Type wtc Reset Value 0x0 Register Details Description Connect Status Change (PORTSCR_CSC) If set to '1' indicates a change in Current Connect Status (CCS). Host mode: Indicates a change has occurred in the port's Current Connect Status. The Controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change.
Appendix B: Register Details * OTG Status inputs (Read Only) * OTG Controls (Read/Write) IP Config Note: The Controller implements one On-The-Go (OTG) Status and Control register. Field Name Bits Type Reset Value reserved 31 ro 0x0 DPIE 30 rw 0x0 (OTGSC_DPIE) Description reserved Data Pulse Interrupt Enable. 0: disable. 1: enable usb.OTGSC [DPIS] interrupt. 1msE 29 rw 0x0 (OTGSC_1MSE) 1 ms Timer Interrupt Enable. 0: disable. 1: enable usb.OTGSC [1msS] interrupt.
Appendix B: Field Name BSEIS Bits 20 Type wtc Reset Value 0x0 (OTGSC_BSEIS) Register Details Description B Session End Interrupt Status. 0: no event detected. 1: event detected. Write 1 to clear bit. This bit is set when VBus has fallen below the B session end threshold. BSVIS 19 wtc 0x0 (OTGSC_BSVIS) B Session Valid Interrupt Status. 0: no event detected. 1: event detected. Write 1 to clear bit. This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.
Appendix B: Field Name BSV Bits 11 Type ro Reset Value 0x0 Indicates VBus is above the B session valid threshold. 10 ro 0x0 A Session Valid (OTGSC_ASV) AVV Indicates VBus is above the A session valid threshold. 9 ro 0x0 A VBus Valid. (OTGSC_AVV) ID Description B Session Valid (OTGSC_BSV) ASV Register Details Indicates VBus is above the A VBus valid threshold. 8 ro 0x0 USB ID'0' = A device, '1' = B device. 7 rw 0x0 Hardware assisted B-Disconnect to A-connect.
Appendix B: Software Name MODE Relative Address 0x000001A8 Absolute Address usb0: 0xE00021A8 Register Details usb1: 0xE00031A8 Width 32 bits Access Type mixed Reset Value 0x00000000 Description USB Mode Selection Register USBMODE Details Field Name Bits Type Reset Value Description SRT 15 rw 0x0 Reseverd, set = 0.
Appendix B: Field Name Bits Type Reset Value Register Details Description ES 2 ro 0x0 Reseverd, set = 0. (Endian Select) CM 1:0 rw 0x0 Controller Mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host & device capability (OTG), the Controller will default to an idle state and will need to be initialized to the desired operating mode after reset.
Appendix B: Register Details Register (usb) ENDPTPRIME Name ENDPTPRIME Software Name EPPRIME Relative Address 0x000001B0 Absolute Address usb0: 0xE00021B0 usb1: 0xE00031B0 Width 32 bits Access Type wtc Reset Value 0x00000000 Description Endpoint Primer (Device mode) Register ENDPTPRIME Details For each endpoint a corresponding bit is used to request that a buffer be prepared for an operation in order to respond to a USB transaction.
Appendix B: Register Details Register (usb) ENDPTFLUSH Name ENDPTFLUSH Software Name EPFLUSH Relative Address 0x000001B4 Absolute Address usb0: 0xE00021B4 usb1: 0xE00031B4 Width 32 bits Access Type wtc Reset Value 0x00000000 Description Endpoint Flush (Device mode) Register ENDPTFLUSH Details The Flush operation of an endpoint will clear the usb.ENDPTSTAT bit and reset the RX/TX data buffer.
Appendix B: Software Name EPRDY Relative Address 0x000001B8 Absolute Address usb0: 0xE00021B8 Register Details usb1: 0xE00031B8 Width 32 bits Access Type ro Reset Value 0x00000000 Description Endpoint Buffer Ready Status (Device mode), RO Register ENDPTSTAT Details For each endpoint, there is one buffer ready status (ENDPTSTAT) bit for the TX buffer and one bit for RX buffer. An ENDPTSTAT bit is set to a 1 by the hardware in a response to receiving an EP prime command (write 1 to usb.
Appendix B: Software Name EPCOMPL Relative Address 0x000001BC Absolute Address usb0: 0xE00021BC Register Details usb1: 0xE00031BC Width 32 bits Access Type rw Reset Value 0x00000000 Description Endpoint Tx Complete (Device mode) Register ENDPTCOMPLETE Details Each bit indicates an event (Transmit/Receive) occurred and software should read the corresponding endpoint queue to determine the endpoint status.
Appendix B: Absolute Address Register Details usb0: 0xE00021C0 usb1: 0xE00031C0 Width 24 bits Access Type mixed Reset Value 0x00800080 Description Endpoint 0 (Device mode) Register ENDPTCTRL0 Details Every device controller implements Endpoint 0 as a control endpoint. Rx and Tx Endpoint Stall bits [0] and [16]: Software can write a one to a stall bit to force the endpoint to return a STALL handshake to the Host.
Appendix B: Field Name Bits Type Reset Value Description reserved 1 ro 0x0 reserved RXS 0 rw 0x0 RX Endpoint Stall. (EPCR_RXS) Register Details 0: Normal operation. 1: Force Stall handshake. Note: refer to the register description for more description.
Appendix B: Register Details Register ENDPTCTRL1 to ENDPTCTRL11 Details Field Name TXE Bits 23 Type rw Reset Value 0x0 Description TX Endpoint Enable. 0: disable. 1: enable. Enable an Endpoing after it has been configured. TXR 22 rw 0x0 TX Data Toggle Reset. Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.
Appendix B: Field Name Bits Type Reset Value reserved 4 rw 0x0 RXT 3:2 rw 0x0 Register Details Description reserved RX Endpoint Type. 00: Control 01: Isochronous 10: Bulk 11: Interrupt RXD 1 rw 0x0 RX Endpoint Data datapath. 0: dual-port memory buffer with a DMA Engine. Always write a 0. RXS 0 rw 0x0 RX Endpoint Stall. 0: Normal operation. 1: Force Stall handshake. Note: refer to the ENDPTCTRL 0 register description for more description.
Appendix B: Access Type Register Details Description w0src w: 1/0 no effect on/sets matching bit, r: clears all bits w0t w: 1/0 no effect on/toggles matching bit, r: no effect w1 w: first one after ~hard~ reset is as-is, other w have no effects, r: no effect w1crs w: 1/0 clears/no effect on matching bit, r: sets all bits w1src w: 1/0 sets/no effect on matching bit, r: clears all bits w1t w: 1/0 toggles/no effect on matching bit, r: no effect waz Write as zero wcrs w: clears all bits, r: s
