User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 100
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
No additional programming of the L2 Controller is required. Application of the pre-fetch hints to the
OCM memory space does not cause any action because, unlike caches, transfer of data into OCM
RAM requires explicit operations by software.
Full Line of Zero Write
When this feature is enabled, the Cortex-A9 processor can write entire non-coherent cache lines of
zeroes to the L2 cache, using a single write command cycle. This provides a performance
improvement as well as some power savings. The Cortex-A9 processor is likely to use this feature
when a CPU is executing a memset routine to initialize a particular memory area.
This feature is disabled by default and can be enabled by setting the “Full Line of Zero” enable bit of
the auxiliary control register for the L2 controller and the enable bit in the Cortex-A9 ACTLR register.
Care must be taken if this feature is enabled because correct behavior relies on consistent enabling
in both the Cortex-A9 processor and the controller.
To enable this feature, the following steps must be performed:
1. Enable the full line of zero feature in the L2 controller.
2. Enable the L2 cache controller.
3. Enable the full line of zero feature in the Cortex-A9.
The cache controller does not support strongly ordered write accesses with this feature. The feature
is also supported by the OCM if it is enabled in the Cortex-A9
Speculative Reads of the Cortex-A9
This is a feature unique to the Cortex-A9 MP configuration and can be enabled using a dedicated
software control bit in the SCU Control register. For this feature, the Cortex-A9 has to be in the SMP
mode through the use of the SMP bit in the ACTLR register; however, the L2 controller does not
require any specific settings. When the speculative read feature is enabled, on coherent line fills, the
SCU speculatively issues read transactions to the controller in parallel with its tag lookup. The
controller does not return data on these speculative reads and only prepares data in its line read
buffers.
If the SCU misses, it issues a confirmation line fill to the controller. The confirmation is merged with
the previous speculative read in the controller and enables the controller to return data to the L1
cache sooner than a L2 cache hit. If the SCU hits, the speculative read is naturally terminated in the
L2 controller, either after a certain number of cycles, or when a resource conflict exists. The L2
controller informs the SCU when a speculative read ends, either by confirmation or termination.
3.4.9 Pre-fetching Operation
The pre-fetch operation is the capability of attempting to fetch cache lines from memory in advance,
to improve system performance. To enable the pre-fetch feature, you set bit 29 or 28 of the auxiliary
or pre-fetch control register. When enabled, if the slave port from the SCU receives a cacheable read
transaction, a cache lookup is performed on the subsequent cache line. Bits [4:0] of the pre-fetch
control register provide the address of the subsequent cache line. If a miss occurs, the cache line is
fetched from external memory, and allocated to the L2 cache.