User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1002
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
B.10 Debug Access Port (dap)
Register Summary
Module Name Debug Access Port (dap)
Base Address 0xF8800000 debug_dap_rom
Description Debug Access Port ROM Table
Vendor Info
Register Name Address Width Type Reset Value Description
ROMENTRY00
0x00000000 32 ro 0x00001003 ROM entry 00
ROMENTRY01
0x00000004 32 ro 0x00002003 ROM entry 01
ROMENTRY02
0x00000008 32 ro 0x00003003 ROM entry 02
ROMENTRY03
0x0000000C 32 ro 0x00004003 ROM entry 03
ROMENTRY04
0x00000010 32 ro 0x00005003 ROM entry 04
ROMENTRY05
0x00000014 32 ro 0x00009003 ROM entry 05
ROMENTRY06
0x00000018 32 ro 0x0000A003 ROM entry 06
ROMENTRY07
0x0000001C 32 ro 0x0000B003 ROM entry 07
ROMENTRY08
0x00000020 32 ro 0x0000C003 ROM entry 08
ROMENTRY09
0x00000024 32 ro 0x00080003 ROM entry 09
ROMENTRY10
0x00000028 32 rw 0x00000000 ROM entry 10
ROMENTRY11
0x0000002C 32 rw 0x00000000 ROM entry 11
ROMENTRY12
0x00000030 32 rw 0x00000000 ROM entry 12
ROMENTRY13
0x00000034 32 rw 0x00000000 ROM entry 13
ROMENTRY14
0x00000038 32 rw 0x00000000 ROM entry 14
ROMENTRY15
0x0000003C 32 rw 0x00000000 ROM entry 15
PERIPHID4
0x00000FD0 8 ro 0x00000003 Peripheral ID4
PERIPHID5
0x00000FD4 8 ro 0x00000000 Peripheral ID5
PERIPHID6
0x00000FD8 8 ro 0x00000000 Peripheral ID6
PERIPHID7
0x00000FDC 8 ro 0x00000000 Peripheral ID7
PERIPHID0
0x00000FE0 8 ro 0x000000B2 Peripheral ID0
PERIPHID1
0x00000FE4 8 ro 0x00000093 Peripheral ID1
PERIPHID2
0x00000FE8 8 ro 0x00000028 Peripheral ID2
PERIPHID3
0x00000FEC 8 ro 0x00000007 Peripheral ID3