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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 103
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
3.5 APU Interfaces
3.5.1 PL Co-processing Interfaces
ACP Interface
The accelerator coherency port (ACP) is a 64-bit AXI slave interface on the SCU that provides an
asynchronous cache-coherent access point directly from the PL to the Cortex-A9 MP-Core processor
subsystem. A range of system PL masters can use this interface to access the caches and the memory
subsystem exactly the way the APU processors do to simplify software, increase overall system
performance, or improve power consumption. This interface acts as a standard AXI slave and
supports all standard read and write transactions without any additional coherency requirements
placed on the PL components. Therefore, the ACP provides cache-coherent access from the PL to
ARM caches while any memory local to the PL are non-coherent with the ARM.
Any read transactions through the ACP to a coherent region of memory interact with the SCU to
check whether the required information is stored within the processor L1 caches. If it is, the data is
returned directly to the requesting component. If it misses in the L1 cache, then there is also the
opportunity to hit in L2 cache before finally being forwarded to the main memory. For write
transactions to any coherent memory region, the SCU enforces coherence before the write is
forwarded to the memory system. The transaction can also optionally allocate into the L2 cache,
removing the power and performance impact of writing through to the off-chip memory.
ACP Requests
The read and write requests performed on the ACP behave differently depending on whether the
request is coherent or not. This behavior is as follows:
ACP coherent read requests: An ACP read request is coherent when ARUSER[0] = 1 and
ARCACHE[1] = 1 alongside ARVALID. In this case, the SCU enforces coherency. When the data is
present in one of the Cortex-A9 processors, the data is read directly from the relevant processor and
returned to the ACP port. When the data is not present in any of the Cortex-A9 processors, the read
request is issued on one of the SCU AXI master ports, along with all its AXI parameters, with the
exception of the locked attribute.
ACP non-coherent read requests: An ACP read request is non-coherent when ARUSER[0] = 0 or
ARCACHE[1] =0 alongside ARVALID. In this case, the SCU does not enforce coherency, and the read
request is directly forwarded to one of the available SCU AXI master ports to the L2 cache controller
or OCM.
ACP coherent write requests: An ACP write request is coherent when AWUSER[0] = 1 and
AWCACHE[1] =1 alongside AWVALID. In this case, the SCU enforces coherency. When the data is
present in one of the Cortex-A9 processors, the data is first cleaned and invalidated from the
relevant CPU. When the data is not present in any of the Cortex-A9 processors, or when it has been
cleaned and invalidated, the write request is issued on one of the SCU AXI master ports, along with
all corresponding AXI parameters with the exception of the locked attribute.