User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 105
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
ACP Limitations
The accelerator coherency port (ACP) has these limitations:
• Exclusive accesses are not allowed for coherent memory.
• Locked accesses are not allowed for coherent memory.
• Optimized coherent read and write transfers when byte strobes are not all set. More specifically,
write transactions with AWLEN = 3, AWSIZE = 3, and WSTRB not equal to 11111111 are not
supported and can cause the L1 cache line in the CPUs to be corrupted. Potential user
workarounds include:
°
Perform smaller, non-optimized, and coherent accesses.
°
Perform a read/modify/write sequence where the write has all byte strobes set.
°
Align user software data structures to avoid needing to deassert any write strobes,
overwriting the bytes instead.
• Continuous access to the OCM over the ACP can starve accesses from other AXI masters. To
allow access from other masters, the ACP bandwidth to OCM should be moderated to less than
the peak OCM bandwidth. This can be accomplished by regulating burst sizes to less than eight
64-bit words.
• Blocks, such as PCIe, which prioritize write requests over read requests should not be connected
to the ACP port, as they might create deadlock. Connecting these devices to the other the GP
and HP AXI ports does not manifest the mentioned deadlock issue.
Note: The Xilinx HDL wrapper around the PS7 primitive provides a function to flag the third
limitation (cache lines being corrupted). If enabled, the Xilinx ACP adapter watches for transactions
that could potentially corrupt the cache and generate an error response to the master that is
requesting the write request. The write transaction is allowed to proceed to the ACP interface, so the
possibility of cache corruption is NOT eliminated. The master is notified of the possible issue to take
the appropriate action. The ACP adapter can also generate an interrupt signal to the CPUs, which can
be used by the software to detect such a situation.
Event Interface
The event bus provides a low-latency and direct mechanism to transfer status and implement a wake
mechanism between the APU and the PL. The event input and output signals on this interface use
toggle signaling in which an event is communicated by toggling the signal to the opposite logic level
on both edges. The event bus includes these signals:
ACP write – S (shared) Data is written to external memory through one of two AXI master
interfaces. L1 cache previously with S status is changed to I state
ACP write – E (exclusive) Data is written to external memory through one of two AXI master
interfaces. Any L1 cache previously with S status is changed to I status.
Table 3-7: ACP Read and Write Behavior (Cont’d)
Action Description