User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 106
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
The event bus can be used to implement PL-based accelerators. The event output can be used to
trigger an ACP accelerator to read from a predefined address. Further on in the process, the event
input can be used to communicate that the data has been written back over the ACP and is ready to
be consumed by a CPU. A detailed description of this example follows:
1. CPU0 generates the data that is required by the accelerator in the L1/L2 cache. This data can
contain both commands and information to be processed.
2. CPU0 issues an SEV (send event) instruction, causing EVENTEVENTO to toggle to the PL. The
signal is connected to an accelerator IP implemented in the PL.
3. CPU0 next issues a WFE (wait For event) instruction, placing the CPU in a lower-power standby
state. This is reflected in the EVENTSTANDBYWFE[0] status output to the PL.
4. The accelerator notices the toggled EVENTEVENTO signal and realizes that CPU0 is waiting. The
accelerator fetches data from a prearranged address and data format through the ACP interface
and begins processing.
5. After writing the result data back through the ACP, the accelerator asserts the EVENTEVENTI
input to indicate that processing is complete and wakes up CPU0.
6. CPU0 wakes from its standby state, which is reflected in the EVENTSTANDBYWFE[0] output, and
CPU0 continues execution using the processed data.
3.5.2 Interrupt Interface
The PS general interrupt controller (GIC) supports 64 interrupt input lines that are driven from other
blocks within the PS or the PL. Six of the 64 interrupt inputs are driven from within the APU. These
include the L1 parity fail, L2 interrupt (all reasons), and PMU (performance monitor unit) interrupt.
The interrupt output of the GIC drives either the IRQ or FIQ inputs of each of the Cortex-A9
processors. The selection as to which processor is interrupted is accomplished through an SCU
register within the APU. Table 3-8 defines the interrupts specific to the APU.
EVENTEVENTO A toggle output signal indicating that either CPU is executing the SEV
instruction.
EVENTEVENTI A toggle input signal that wakes up either one or both CPUs if they
are in a standby state initiated by the WFE instruction.
EVENTSTANDBYWFE[1:0] Two-level output signals indicating the state of the two CPUs. A bit is
asserted if the corresponding CPU is in standby state following the
execution of the WFE (wait for event) instruction.
EVENTSTANDBYWFI[1:0] Two-level output signals indicating the state of the two CPUs. A bit is
asserted if the corresponding CPU is in standby state following the
execution of the WFI (wait for interrupt) instruction.
Table 3-8: APU Interrupts
Interrupt Description
32 Any of the L1 instruction cache, L1 data cache, TLB, GHB, and BTAC parity errors from CPU 0
33 Any of the L1 instruction cache, L1 data cache, TLB, GHB, and BTAC parity errors from CPU 1
34 Any errors, including parity errors, from the L2 controller
92 Any of the parity errors from SCU generate a third interrupt