User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1073
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
StimPort23 0x0000005C 32 rw 0x00000000 Stimulus Port Register 23
StimPort24
0x00000060 32 rw 0x00000000 Stimulus Port Register 24
StimPort25
0x00000064 32 rw 0x00000000 Stimulus Port Register 25
StimPort26
0x00000068 32 rw 0x00000000 Stimulus Port Register 26
StimPort27
0x0000006C 32 rw 0x00000000 Stimulus Port Register 27
StimPort28
0x00000070 32 rw 0x00000000 Stimulus Port Register 28
StimPort29
0x00000074 32 rw 0x00000000 Stimulus Port Register 29
StimPort30
0x00000078 32 rw 0x00000000 Stimulus Port Register 30
StimPort31
0x0000007C 32 rw 0x00000000 Stimulus Port Register 31
TER
0x00000E00 32 rw 0x00000000 Trace Enable Register
TTR
0x00000E20 32 rw 0x00000000 Trace Trigger Register
CR
0x00000E80 24 mixed 0x00000004 Control Register
SCR
0x00000E90 12 rw 0x00000400 Synchronization Control
Register
ITTRIGOUTACK
0x00000EE4 1 ro 0x00000000 Integration Test Trigger Out
Acknowledge Register
ITTRIGOUT
0x00000EE8 1 wo 0x00000000 Integration Test Trigger Out
Register
ITATBDATA0
0x00000EEC 2 wo 0x00000000 Integration Test ATB Data
Register 0
ITATBCTR2
0x00000EF0 1 ro 0x00000001 Integration Test ATB Control
Register 2
ITATABCTR1
0x00000EF4 7 wo 0x00000000 Integration Test ATB Control
Register 1
ITATBCTR0
0x00000EF8 2 wo 0x00000000 Integration Test ATB Control
Register 0
IMCR
0x00000F00 1 rw 0x00000000 Integration Mode Control
Register
CTSR
0x00000FA0 8 rw 0x000000FF Claim Tag Set Register
CTCR
0x00000FA4 8 rw 0x00000000 Claim Tag Clear Register
LAR
0x00000FB0 32 wo 0x00000000 Lock Access Register
LSR
0x00000FB4 3 ro 0x00000003 Lock Status Register
ASR
0x00000FB8 8 ro 0x00000088 Authentication Status Register
DEVID
0x00000FC8 13 ro 0x00000020 Device ID
DTIR
0x00000FCC 8 ro 0x00000043 Device Type Identifier Register
PERIPHID4
0x00000FD0 8 ro 0x00000004 Peripheral ID4
PERIPHID5
0x00000FD4 8 ro 0x00000000 Peripheral ID5
Register Name Address Width Type Reset Value Description