User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 109
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
• The L2 cache can be put in the standby mode when the CPUs are in that mode.
• Clock gating is extensively used in all the sub-blocks within the module. Dynamic clock gating in
the Cortex-A9 can be enabled in the CP15 power control register. If enabled, the clocks to the
CPU internal blocks are dynamically disabled in idle periods. The gated blocks include the
integer core, the system control block, and the data engine.
• Accurate branch and return prediction reduces the number of incorrect instruction fetch and
decode operations.
• Physically addressed caches reduce the number of cache flushes and refills, saving energy in the
system.
• The CPUs implement micro TLBs for local address translation which reduces the power
consumed in translation and protection look-ups.
• The tag RAMs and data RAMs are accessed sequentially to eliminate accesses to the unwanted
data RAMs, and thus minimize unnecessary power consumption.
• To reduce power consumption in the L1 caches, the number of full cache reads is reduced by
taking advantage of the sequential nature of memory accesses. If a cache read is sequential to
the previous cache read, and the address is within the same cache line, only the data RAM set
that was previously read is accessed.
• If an instruction loop fits in four BTAC entries, then instruction cache accesses are turned off to
lower power consumption.
• The clock to the NEON engine is dynamically controlled by the CPU and the engine gets clocked
only when a NEON instruction is issued.
Note: Power to the APU or any of its sub-blocks cannot be turned off while the PS is powered on.
3.8.2 Standby Mode
In the standby mode of operation, the device is still powered-up, but most of its clocks are gated off.
This means that the processor is in a static state and the only power drawn is due to leakage currents
and the clocking of the small amount of logic which looks out for the wake-up condition.
This mode is entered using either the WFI (wait for interrupt) or WFE (wait for event) instructions. It
is recommended that a DSB memory barrier be used before WFI or WFE, to ensure that pending
memory transactions complete.
The processor stops execution until a wake-up event is detected. The wake-up condition is
dependent on the entry instruction. For WFI, an interrupt or external debug request wakes the
processor. For WFE, several specified events exist, including another processor in an MP system
executing the SEV instruction. A request from the SCU can also wake up the clock for a cache
coherency operation in an MP system. This means that the cache of a processor which is in standby
state continues to be coherent with caches of other processors. A processor reset always forces the
processor to exit from the standby condition.
The standby mode in the SCU is enabled by setting the corresponding bit in the
mpcore.SCU_CONTROL_REGISTER. When this feature is enabled, the SCU stops its internal clocks
when the following conditions are met:
•CPUs are in WFI mode
• No pending requests on the ACP