User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 110
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
• No remaining activity in the SCU
The SCU resumes normal operation when a CPU leaves WFI mode or a request on the ACP occurs.
The standby mode of the L2 cache controller can be enabled by setting bit 0 of the L2 controller
power control register (l2cpl310.reg15_power_ctrl). This mode is used in conjunction with the wait
state (WFI/WFE) of the processor that drives the controller. Before entering the wait state, the
Cortex-A9 processor must set its status field in the CPU power status register of the SCU to signal its
entering standby mode. The Cortex-A9 processor then executes a WFI or WFE entry instruction. The
SCU CPU power status register bits can also be read by a Cortex-A9 processor exiting low-power
mode to determine its state before executing its reset setup.
If the MP system is in the standby mode, the SCU signals to the L2 cache controller to gate its clock
and the controller honors that when the L2 becomes idle. Any transaction from the SCU to the L2
restarts the clock and triggers a response with 2-3 clock cycles of delay.
3.8.3 Dynamic Clock Gating in the L2 Controller
Bit 1 of the L2 Controller Power Control register enables the dynamic clock gating feature within the
controller. If this feature is enabled, the cache controller stops its clock when it is idle for 32 clock
cycles. The controller stops the clock until there is a transaction on its slave interface from the SCU.
If this interface detects a transaction, it restarts its clock and accepts the new transaction with two to
three cycles of delay.
3.9 CPU Initialization Sequence
Typically, these are the following steps to initialize CPU:
1. Set the vector base address register.
2. Invalidate L1 caches, TLB, branch predictor array (refer to Initialization of L1 Caches).
3. Invalidate L2 cache.
4. Prepare page tables and load into physical memory. (For more information on page tables, refer
to Translation Table Base Register 0 and 1.)
5. Setup the stack.
6. Load the page table base address into the translation table base register (refer to Translation
Table Base Register 0 and 1).
7. Set the MMU enable bit of the system control register.
8. Initialize and enable L2 cache (refer to L2-Cache, section 3.4.10 Programming Model).
9. Enable L1 caches by writing to the system control register.
10. Jump to entry of application.