User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1146
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
PCFG_POR_CNT_4K 29 rw 0x0 This register controls which POR timer the PL will
use for power-up.
0 - Use 64k timer
1 - Use 4k timer
reserved 28 rw 0x0 Reserved
PCAP_PR 27 rw 0x1 After the initial configuration of the PL, a partial
reconfiguration can be performed using either the
ICAP or PCAP interface.
These interfaces are mutually exclusive and
cannot be used simultaneously.
Switching between ICAP and PCAP is possible
but users should ensure that no commands or
data are being transmitted or received before
changing interfaces.
Failure to do this could lead to unexpected
behavior.
This bit selects between ICAP and PCAP for PL
reconfiguration.
0 - ICAP is selected for reconfiguration
1 - PCAP is selected for reconfiguration
PCAP_MODE 26 rw 0x1 This bit enables the PCAP interface
QUARTER_PCAP_RA
TE_EN
(PCAP_RATE_EN)
25 rw 0x0 This bit is used to reduce the PCAP data
transmission to once every 4 clock cycles.
This bit MUST be set when the AES engine is
being used to decrypt configuration data for
either the PS or PL.
Setting this bit for non-encrypted PCAP data
transmission is allowed but not recommended.
0 - PCAP data transmitted every clock cycle
1 - PCAP data transmitted every 4th clock cycle
(must be used for encrypted data)
MULTIBOOT_EN 24 rw 0x0 This bit enables multi-boot out of reset. This bit is
only cleared by a PS_POR_B reset,
0 - Boot from default boot image base address
1 - Boot from multi-boot offset address
JTAG_CHAIN_DIS 23 rw 0x0 This bit is used to disable the JTAG scan chain.
The primary purpose is to protect the PL from
unwanted JTAG accesses.
The JTAG connection to the PS DAP and PL TAP
will be disabled when this bit is set.
reserved 22:16 rw 0x0 Reserved
reserved 15 wo 0x0 Reserved. Do not modify.
reserved 14 rw 0x1 Reserved - always write with 1
Field Name Bits Type Reset Value Description