User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1155
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register STATUS Details
Reset Value 0x40000820
Description Status Register: This register contains miscellaneous status.
Field Name Bits Type Reset Value Description
DMA_CMD_Q_F 31 ro 0x0 DMA command queue full, if set
DMA_CMD_Q_E 30 ro 0x1 DMA command queue empty, if set
DMA_DONE_CNT 29:28 clron
wr
0x0 Number of completed DMA transfers that have
not been acknowledged by software:
00 - all finished transfers have been
acknowledged
01 - one finished transfer outstanding
10 - two finished transfers outstanding
11 - three or more finished transfers outstanding
A finished transfer is acknowledged by clearing
the DMA_DONE_INT interrupt status flag of the
interrupt status register 0x00C.
This count is cleared by writing a 1 to either bit
location.
reserved 27:25 rw 0x0 Reserved
RX_FIFO_LVL 24:20 ro 0x0 This register is used to indicate how many valid
32-Bit words in the Rx FIFO, max. is 31
reserved 19 rw 0x0 Reserved
TX_FIFO_LVL 18:12 ro 0x0 This register is used to indicate how many valid
32-Bit words in the Tx FIFO, max. is 127
PSS_GTS_USR_B 11 ro 0x1 Tri-state IO during HIZ, active low
PSS_FST_CFG_B 10 ro 0x0 First PL configuration done, active low.
PSS_GPWRDWN_B 9 ro 0x0 Global power down, active low
PSS_GTS_CFG_B 8 ro 0x0 Tri-state IO during config, active low. This signal
will only be low when the PL CFG block is being
used to configure the PL.
0 - IO are tri-stated by CFG block
SECURE_RST 7 ro 0x0 This bit is used to indicate a secure lockdown.
Can only be cleared by a PS_POR_B reset.
ILLEGAL_APB_ACCE
SS
6 ro 0x0 Indicates the UNLOCK register was not written
with the correct unlock word.
If set all secure boot features will be disabled, the
DAP will be disabled and writing to the DEVCI
registers will be disabled.
The illegal access mode can only be cleared with a
PS_POR_B reset.
PSS_CFG_RESET_B 5 ro 0x1 PL configuration reset, active low.