User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1166
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
B.17 DMA Controller (dmac)
Register Summary
Module Name DMA Controller (dmac)
Software Name XDMAPS
Base Address 0xF8004000 dmac0_ns
0xF8003000 dmac0_s
Description Direct Memory Access Controller, PL330
Vendor Info ARM PL330
Register Name Address Width Type Reset Value Description
DSR
0x00000000 32 mixed 0x00000000 DMA Manager Status
DPC
0x00000004 32 mixed 0x00000000 DMA Program Counter
INTEN
0x00000020 32 mixed 0x00000000 DMASEV Instruction Response
Control
INT_EVENT_RIS
0x00000024 32 mixed 0x00000000 Event Interrupt Raw Status
INTMIS
0x00000028 32 mixed 0x00000000 Interrupt Status
INTCLR
0x0000002C 32 mixed 0x00000000 Interrupt Clear
FSRD
0x00000030 32 mixed 0x00000000 Fault Status DMA Manager
FSRC
0x00000034 32 mixed 0x00000000 Fault Status DMA Channel
FTRD
0x00000038 32 mixed 0x00000000 Fault Type DMA Manager
FTR0
0x00000040 32 mixed 0x00000000 Default Type DMA Channel 0
FTR1
0x00000044 32 mixed 0x00000000 Default Type DMA Channel 1
FTR2
0x00000048 32 mixed 0x00000000 Default Type DMA Channel 2
FTR3
0x0000004C 32 mixed 0x00000000 Default Type DMA Channel 3
FTR4
0x00000050 32 mixed 0x00000000 Default Type DMA Channel 4
FTR5
0x00000054 32 mixed 0x00000000 Default Type DMA Channel 5
FTR6
0x00000058 32 mixed 0x00000000 Default Type DMA Channel 6
FTR7
0x0000005C 32 mixed 0x00000000 Default Type DMA Channel 7
CSR0
0x00000100 32 mixed 0x00000000 Channel Status DMA Channel 0
CPC0
0x00000104 32 mixed 0x00000000 Channel PC for DMA Channel 0
CSR1
0x00000108 32 mixed 0x00000000 Channel Status DMA Channel 1
CPC1
0x0000010C 32 mixed 0x00000000 Channel PC for DMA Channel 1
CSR2
0x00000110 32 mixed 0x00000000 Channel Status DMA Channel 2