User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 120
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
X-Ref Target - Figure 5-1
Figure 5-1: Interconnect Block Diagram
OCM
Interconnect
Master Interconnect
for Slave Peripherals
APB
Slaves
Registers
Slaves
Reg & Data
General Purpose
AXI Controllers
(S_AXI_GP[1:0])
Cortex A9
NEON/FPU
Jazelle, Thumb-2,
MMUs,
L1 i/dCaches
Snoop Control Unit
(SCU)
M0
M1
M
L2 Cache
Controller
M0 M1
S
512 kB
M
S
Central
Interconnect
S1
M1
S1S0S2S3
S
M
M2M0
M0
M1
Slave Interconnect
for Master Peripherals
M
S3
S0
S1
S2
DevC
DAP
M
S0
M2M0 M1
General Purpose
AXI Controllers
(M_AXI_GP[1:0])
S1S0
S1
S0 S2
M3
S
DDR Memory Controller
32-bit
CPU_2x
CPU_1x
CPU_2x
64-bit
Cache
Coherent
ACP port
(S_AXI_ACP)
AHB/APB
Clock
cpu_1x
CPU_1x
ASYNC
ASYNC
ASYNC ASYNC
PL Logic
DDR_3x Clock
PL Logic
CPU_2x
CPU_1x
Masters
Data
DMA
Controller
CPU_6x4x
CPU_6x4x
CPU_6x4x
8
Read/Write Request Capability
ASYNC
Async
crossing
4
8
81
88
88
88 4 1
32-bit
32-bit
8
High Performance
AXI Controllers
(AXI_HP[3:0])
S3S2S1S0
M2M0 M1
M3M2M1M0
FIFOFIFOFIFOFIFO
PL clocks
ASYNCASYNCASYNCASYNC
888
88
256 kB
S1 S0
S0
M
S1
64-bit
PL Fabric
PL Fabric
64-bit
DDR_2x
ASYNC ASYNC
64-bit
ASYNC
32-bit
64-bit
ASYNC
ASYNC
CPU_2x
Memory
Interconnect
64-bit
M
32- / 64-bit
Cache Tag
RAM
CPU, L1
Clock
cpu_6x4x
CPU_2x
DDR Clock
ddr_2x
DDR Clock
ddr_3x
Each of the eight
AXI interfaces are
asynchronous to
all else.
OCM
Clock
cpu_2x
64-bit
PL
64-bit 64-bit
UG585_c5_01_120813
CPU_6x4x
CPU_2x
On-chip
RAM
32-bit
64-bit
8
8,3
4
ASYNC
SS
QoS
QoS QoS
4,4
7,3
7,3
(e.g. 1 number: 8 reads, 8 writes)
(e.g. 2 numbers: 7 reads, 3 writes)
Synchronous CPU clock domain
is asynchronous to all else.
Asynchronous to
all else.