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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 121
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
L2 Cache Controller
The functionality of the L2 cache controller is described in Chapter 3, Application Processing Unit.
The address filtering feature of the L2 cache controller makes the L2 cache controller function like a
switch from the perspective of the traffic from its AXI slave ports to its AXI master ports.
Interconnect Slaves
The interconnect slaves are shown toward the bottom of Figure 5-1. The Interconnect slaves include:
•On-chip RAM (OCM)
• DDR DRAM
• General purpose PL interfaces, M_AXI_GP{1:0}
• AHB slaves (IOP with local DMA units)
• APB slaves (programmable registers in various blocks)
• GPV (programmable registers of the interconnect, not shown in Figure 5-1)
5.1.3 Datapaths
Table 5-1 lists the major datapaths used by the PS interconnect.
Table 5-1: Interconnect Datapaths
Source Destination Type
Clock
at source
Clock
at destination
Sync
or
Async
(1)
Data
width
R/W
Request
Capability
Advanced
QoS
CPU SCU AXI CPU_6x4x CPU_6x4x Sync 64 7, 12 -
AXI_ACP SCU AXI SAXIACPACLK CPU_6x4x Async 64 7, 3 -
AXI_HP FIFO AXI SAXIHPnACLK DDR_2x Async 32/64
14-70,
8-32
(2)
-
S_AXI_GP
Master
interconnect
AXI SAXIGPnACLK CPU_2x Async 32 8, 8 -
DevC
Master
interconnect
AXI CPU_1x CPU_2x Sync 32 8, 4 -
DAP
Master
interconnect
AHB CPU_1x CPU_2x Sync 32 1, 1 -
AHB masters
Central
interconnect
AXI CPU_1x CPU_2x Sync 32 8, 8 X
DMA
controller
Central
interconnect
AXI CPU_2x CPU_2x Sync 64 8, 8 X
Master
interconnect
Central
interconnect
AXI CPU_2x CPU_2x Sync 64 - -
FIFO
Memory
interconnect
AXI DDR_2x DDR_2x Sync 64 8, 8 -
SCU L2 Cache AXI CPU_6X4x CPU_6x4x Sync 64 8, 3 -