User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 122
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
5.1.4 Clock Domains
The interconnect, masters, and slaves use the clocks shown inTable 5-2.:
Memory
interconnect
OCM
interconnect
AXI DDR_2x CPU_2x Async 64 - -
Central
interconnect
OCM
interconnect
AXI CPU_2x CPU_2x Sync 64 - -
L2 Cache
Slave
interconnect
AXI CPU_6x4x CPU_2x Sync 64 8, 8 -
Central
interconnect
Slave
interconnect
AXI CPU_2x CPU_2x Sync 64 - -
SCU
On-chip
RAM
AXI CPU_6x4x CPU_2x Sync 64 4, 4 -
OCM
interconnect
On-chip
RAM
AXI CPU_2x CPU_2x Sync 64 4, 4 -
Slave
interconnect
APB slaves APB CPU_2x CPU_1x Sync 32 1, 1 -
Slave
interconnect
AHB slaves AXI CPU_2x CPU_1x Sync 32 4, 4 -
Slave
interconnect
AXI_GP AXI CPU_2x MAXIGPnACLK Async 32 8, 8 -
L2 cache
DDR
controller
AXI CPU_6x4x DDR_3x Async 64 8, 8 X
Central
interconnect
DDR
controller
AXI CPU_2x DDR_3x Async 64 8, 8 -
Memory
interconnect
DDR
controller
AXI DDR_2x DDR_3x Async 64 8, 8 -
Slave
interconnect
GPV
(3)
CPU_2x (multiple) - - - -
Notes:
1. Each asynchronous path includes an asynchronous bridge for clock domain crossing.
2. Burst-length dependent (see AXI_HP Interfaces).
3. The path from the slave interconnect to GPV is an internal path within the entire interconnect structure. When accessing
GPV, ensure that all clocks are on.
Table 5-1: Interconnect Datapaths (Cont’d)
Source Destination Type
Clock
at source
Clock
at destination
Sync
or
Async
(1)
Data
width
R/W
Request
Capability
Advanced
QoS
Table 5-2: Clocks used by Interconnect, Masters, and Slaves
CPU_6x4x: CPUs, SCU, L2 Cache controller, On-Chip RAM
CPU_2x Central interconnect, master interconnect, slave interconnect, OCM interconnect
CPU_1x AHB masters, AHB slaves, APB slaves, DevC, DAP
DDR_3x DDR Memory Controller
DDR_2x Memory interconnect, FIFOs