User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1271
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
spec_addr3_top 0x0000009C 32 mixed 0x00000000 Specific Address 3 Top [47:32]
spec_addr4_bot
0x000000A0 32 rw 0x00000000 Specific Address 4 Bottom [31:0]
spec_addr4_top
0x000000A4 32 mixed 0x00000000 Specific Address 4 Top [47:32]
type_id_match1
0x000000A8 32 mixed 0x00000000 Type ID Match 1
type_id_match2
0x000000AC 32 mixed 0x00000000 Type ID Match 2
type_id_match3
0x000000B0 32 mixed 0x00000000 Type ID Match 3
type_id_match4
0x000000B4 32 mixed 0x00000000 Type ID Match 4
wake_on_lan
0x000000B8 32 mixed 0x00000000 Wake on LAN Register
ipg_stretch
0x000000BC 32 mixed 0x00000000 IPG stretch register
stacked_vlan
0x000000C0 32 mixed 0x00000000 Stacked VLAN Register
tx_pfc_pause
0x000000C4 32 mixed 0x00000000 Transmit PFC Pause Register
spec_addr1_mask_bot
0x000000C8 32 rw 0x00000000 Specific Address Mask 1 Bottom
[31:0]
spec_addr1_mask_top
0x000000CC 32 mixed 0x00000000 Specific Address Mask 1 Top
[47:32]
module_id
0x000000FC 32 ro 0x00020118 Module ID
octets_tx_bot
0x00000100 32 ro 0x00000000 Octets transmitted [31:0] (in
frames without error)
octets_tx_top
0x00000104 32 ro 0x00000000 Octets transmitted [47:32] (in
frames without error)
frames_tx
0x00000108 32 ro 0x00000000 Frames Transmitted
broadcast_frames_tx
0x0000010C 32 ro 0x00000000 Broadcast frames Tx
multi_frames_tx
0x00000110 32 ro 0x00000000 Multicast frames Tx
pause_frames_tx
0x00000114 32 ro 0x00000000 Pause frames Tx
frames_64b_tx
0x00000118 32 ro 0x00000000 Frames Tx, 64-byte length
frames_65to127b_tx
0x0000011C 32 ro 0x00000000 Frames Tx, 65 to 127-byte length
frames_128to255b_tx
0x00000120 32 ro 0x00000000 Frames Tx, 128 to 255-byte
length
frames_256to511b_tx
0x00000124 32 ro 0x00000000 Frames Tx, 256 to 511-byte
length
frames_512to1023b_tx
0x00000128 32 ro 0x00000000 Frames Tx, 512 to 1023-byte
length
frames_1024to1518b_tx
0x0000012C 32 ro 0x00000000 Frame Tx, 1024 to 1518-byte
length
tx_under_runs
0x00000134 32 ro 0x00000000 Transmit under runs
single_collisn_frames
0x00000138 32 ro 0x00000000 Single Collision Frames
multi_collisn_frames
0x0000013C 32 ro 0x00000000 Multiple Collision Frames
Register Name Address Width Type Reset Value Description