User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1274
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register net_ctrl Details
The network control register contains general MAC control functions for both receiver and transmitter.
Field Name Bits Type Reset Value Description
reserved 31:19 ro 0x0 Reserved, read as zero, ignored on write.
flush_next_rx_dpram_
pkt
18 wo 0x0 Flush the next packet from the external RX
DPRAM.
Writing one to this bit will only have an effect if
the DMA is not currently writing a packet already
stored in the DPRAM to memory.
tx_pfc_pri_pri_pause_f
rame
17 wo 0x0 Transmit PFC Priority Based Pause Frame. Takes
the values stored in the Transmit PFC Pause
Register
en_pfc_pri_pause_rx 16 wo 0x0 Enable PFC Priority Based Pause Reception
capabilities.
Setting this bit will enable PFC negotiation and
recognition of priority based pause frames.
str_rx_timestamp 15 rw 0x0 Store receive time stamp to memory. Setting this
bit to one will cause the CRC of every received
frame to be replaced with the value of the
nanoseconds field of the 1588 timer that was
captured as the receive frame passed the message
time stamp point. Set to zero for normal
operation.
reserved 14 rw 0x0 Reserved. Do not modify.
reserved 13 wo 0x0 Reserved. Do not modify.
tx_zeroq_pause_frame
(ZEROPAUSETX)
12 wo 0x0 Transmit zero quantum pause frame. Writing one
to this bit causes a pause frame with zero
quantum to be transmitted.
tx_pause_frame
(PAUSETX)
11 wo 0x0 Transmit pause frame - writing one to this bit
causes a pause frame to be transmitted.
tx_halt
(HALTTX)
10 wo 0x0 Transmit halt - writing one to this bit halts
transmission as soon as any ongoing frame
transmission ends.
start_tx
(STARTTX)
9 wo 0x0 Start transmission - writing one to this bit starts
transmission.
back_pressure 8 rw 0x0 Back pressure - if set in 10M or 100M half duplex
mode will force collisions on all received frames.
wren_stat_regs
(STATWEN)
7 rw 0x0 Write enable for statistics registers - setting this bit
to one means the statistics registers can be written
for functional test purposes.
incr_stat_regs
(STATINC)
6 wo 0x0 Incremental statistics registers - this bit is write
only.
Writing a one increments all the statistics registers
by one for test purposes.