User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1276
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register net_cfg Details
The network configuration register contains functions for setting the mode of operation for the Gigabit
Ethernet MAC
Field Name Bits Type Reset Value Description
unidir_en 31 rw 0x0 NA.
ignore_ipg_rx_er 30 rw 0x0 Ignore IPG rx_er. When set rx_er has no effect on
the GEM's operation when rx_dv is low. Set this
when using the RGMII wrapper in half-duplex
mode.
rx_bad_preamble
(BADPREAMBEN)
29 rw 0x0 Receive bad preamble. When set frames with
non-standard preamble are not rejected.
ipg_stretch_en
(IPDSTRETCH)
28 rw 0x0 IPG stretch enable - when set the transmit IPG can
be increased above 96 bit times depending on the
previous frame length using the IPG stretch
register.
sgmii_en 27 rw 0x0 SGMII mode enable - changes behavior of the
auto-negotiation advertisement and link partner
ability registers to meet the requirements of
SGMII and reduces the duration of the link timer
from 10 ms to 1.6 ms
ignore_rx_fcs
(FCSIGNORE)
26 rw 0x0 Ignore RX FCS - when set frames with FCS/CRC
errors will not be rejected. FCS error statistics will
still be collected for frames with bad FCS and FCS
status will be recorded in frame's DMA
descriptor.
For normal operation this bit must be set to zero.
rx_hd_while_tx
(HDRXEN)
25 rw 0x0 Enable frames to be received in half-duplex mode
while transmitting.
rx_chksum_offld_en
(RXCHKSUMEN)
24 rw 0x0 Receive checksum offload enable - when set, the
receive checksum engine is enabled. Frames with
bad IP, TCP or UDP checksums are discarded.
dis_cp_pause_frame
(PAUSECOPYDI)
23 rw 0x0 Disable copy of pause frames - set to one to
prevent valid pause frames being copied to
memory. When set, pause frames are not copied to
memory regardless of the state of the copy all
frames bit; whether a hash match is found or
whether a type ID match is identified. If a
destination address match is found the pause
frame will be copied to memory.
Note that valid pause frames received will still
increment pause statistics and pause the
transmission of frames as required.