User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1278
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
pause_en
(PAUSEEN)
13 rw 0x0 Pause enable - when set, transmission will pause
if a non zero 802.3 classic pause frame is received
and PFC has not been negotiated.
retry_test
(RETRYTESTEN)
12 rw 0x0 Retry test - must be set to zero for normal
operation.
If set to one the backoff between collisions will
always be one slot time. Setting this bit to one
helps test the too many retries condition. Also
used in the pause frame tests to reduce the pause
counter's decrement time from 512 bit times, to
every rx_clk cycle.
pcs_sel 11 rw 0x0 NA
0: GMII/MII interface enabled, TBI disabled
1: TBI enabled, GMII/MII disabled
gige_en
(1000)
10 rw 0x0 Gigabit mode enable - setting this bit configures
the GEM for 1000 Mbps operation.
0: 10/100 operation using MII or TBI interface
1: Gigabit operation using GMII or TBI interface
ext_addr_match_en
(EXTADDRMATCHEN
)
9 rw 0x0 External address match enable - when set the
external address match interface can be used to
copy frames to memory.
rx_1536_byte_frames
(1536RXEN)
8 rw 0x0 Receive 1536 byte frames - setting this bit means
the GEM will accept frames up to 1536 bytes in
length. Normally the GEM would reject any
frame above 1518 bytes.
uni_hash_en
(UCASTHASHEN)
7 rw 0x0 Unicast hash enable - when set, unicast frames
will be accepted when the 6 bit hash function of
the destination address points to a bit that is set in
the hash register.
multi_hash_en
(MCASTHASHEN)
6 rw 0x0 Multicast hash enable - when set, multicast
frames will be accepted when the 6 bit hash
function of the destination address points to a bit
that is set in the hash register.
no_broadcast
(BCASTDI)
5 rw 0x0 No broadcast - when set to logic one, frames
addressed to the broadcast address of all ones will
not be accepted.
copy_all
(COPYALLEN)
4 rw 0x0 Copy all frames - when set to logic one, all valid
frames will be accepted.
reserved 3 rw 0x0 Reserved. Do not modify.
disc_non_vlan
(NVLANDISC)
2 rw 0x0 Discard non-VLAN frames - when set only VLAN
tagged frames will be passed to the address
matching logic.
Field Name Bits Type Reset Value Description