User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 128
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
(through L2 cache), the DMA controller, and the IOP masters can interfere with traffic from the PL.
The QoS modules allow you to throttle these PS masters to ensure expected/consistent throughput
and latency for the user design in the PL or specific PS masters.
This is especially useful for video,
which requires guaranteed maximum latency. By regulating the “irregular” masters such as
CPUs,
the DMA controller, and IOP masters, it is possible to guarantee maximum latency for
PL-based video.
5.2.3 DDR Port Arbitration
The PS interconnect uses all four QoS signals except where it attaches to the DDR memory controller,
which takes only the most significant QoS signal. A 3-input mux selects among this QoS signal,
another signal from the SLCR.DDR_URGENT register, and a DDRARB signal directly from the PL to
determine if a request is urgent. Refer to Chapter 10, DDR Memory Controller for more details.
5.3 AXI_HP Interfaces
The four AXI_HP interfaces provide PL bus masters with high bandwidth datapaths to the DDR and
OCM memories. Each interface includes two FIFO buffers for read and write traffic. The PL to memory
interconnect routes the high-speed AXI_HP ports to two DDR memory ports or the OCM. The AXI_HP
interfaces are also referenced as AFI (AXI FIFO interface), to emphasize their buffering capabilities.
The PL level shifters must be enabled through LVL_SHFTR_EN before PL logic communication can
occur.
5.3.1 Features
The interfaces are designed to provide a high throughput datapath between PL masters and PS
memories, including the DDR and on-chip RAM. The main features include:
• 32- or 64-bit data wide master interfaces (independently programmed per port)
• Efficient dynamic upsizing to 64-bits for aligned transfers in 32-bit interface mode, controllable
through AxCACHE[1]
• Automatic expansion to 64-bits for unaligned 32-bit transfers in 32-bit interface mode
• Programmable release threshold of write commands
• Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS
• Smoothing out of “long-latency” transfers using 1 KB (128 by 64 bit) data FIFOs for both reads
and writes
• QoS signaling available from PL ports
• Command and data FIFO fill-level counts available to the PL
• Standard AXI 3.0 interfaces supported
• Programmable command issuance to the interconnect, separately for read and write commands
• Large slave interface read acceptance capability in the range of 14 to 70 commands (burst
length dependent)