User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1281
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
csum_gen_offload_en
(TCPCKSUM)
11 rw 0x0 Transmitter IP, TCP and UDP checksum
generation offload enable. When set, the
transmitter checksum generation engine is
enabled, to calculate and substitute checksums for
transmit frames. When clear, frame data is
unaffected.
If the GEM is not configured to use the DMA
packet buffer, this bit is not implemented and will
be treated as reserved, read as zero, ignored on
write.
Zynq uses packet buffer.
tx_pktbuf_memsz_sel
(TXSIZE)
10 rw 0x1 Transmitter packet buffer memory size select -
Having this bit at zero halves the amount of
memory used for the transmit packet buffer. This
reduces the amount of memory used by the GEM.
It is important to set this bit to one if the full
configured physical memory is available. The
value in brackets below represents the size that
would result for the default maximum configured
memory size of 4 kB.
1: Use full configured addressable space (4 kB)
0: Do not use top address bit (2 kB)
If the GEM is not configured to use the DMA
packet buffer, this bit is not implemented and will
be treated as reserved, read as zero, ignored on
write. Zynq uses packet buffer.
rx_pktbuf_memsz_sel
(RXSIZE)
9:8 rw 0x3 Receiver packet buffer memory size select -
Having these bits at less than 11 reduces the
amount of memory used for the receive packet
buffer. This reduces the amount of memory used
by the GEM. It is important to set these bits both
to one if the full configured physical memory is
available. The value in brackets below represents
the size that would result for the default
maximum configured memory size of 8 kBs.
00: Do not use top three address bits (1 kB)
01: Do not use top two address bits (2 kB)
10: Do not use top address bit (4 kB)
11: Use full configured addressable space (8 kB)
If the controller is not configured to use the DMA
packet buffer, these bits are not implemented and
will be treated as reserved, read as zero, ignored
on write. Zynq uses packet buffer.
ahb_endian_swp_pkt_
en
(ENDIAN)
7 rw 0x1 AHB endian swap mode enable for packet data
accesses - When set, selects swapped endianism
for AHB transfers. When clear, selects little endian
mode.
Field Name Bits Type Reset Value Description