User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1283
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Field Name Bits Type Reset Value Description
reserved 31:9 ro 0x0 Reserved, read as zero, ignored on write.
hresp_not_ok
(HRESPNOK)
8 wtc 0x0 Hresp not OK - set when the DMA block sees
hresp not OK. Cleared by writing a one to this bit.
late_collision 7 wtc 0x0 Late collision occurred - only set if the condition
occurs in gigabit mode, as retry is not attempted.
Cleared by writing a one to this bit.
tx_under_run
(URUN)
6 wtc 0x0 Transmit under run - this bit is set if the
transmitter was forced to terminate a frame that it
had already began transmitting due to further
data being unavailable.
This bit is set if a transmitter status write back has
not completed when another status write back is
attempted.
When using the DMA interface configured for
internal FIFO mode, this bit is also set when the
transmit DMA has written the SOP data into the
FIFO and either the AHB bus was not granted in
time for further data, or because an AHB not OK
response was returned, or because a used bit was
read.
When using the DMA interface configured for
packet buffer mode, this bit will never be set.
When using the external FIFO interface, this bit is
also set when the tx_r_underflow input is
asserted during a frame transfer. Cleared by
writing a 1.
tx_complete
(TXCOMPL)
5 wtc 0x0 Transmit complete - set when a frame has been
transmitted. Cleared by writing a one to this bit.
tx_corr_ahb_err
(BUFEXH)
4 wtc 0x0 Transmit frame corruption due to AHB error - set
if an error occurs whilst midway through reading
transmit frame from the AHB, including HRESP
errors and buffers exhausted mid frame (if the
buffers run out during transmission of a frame
then transmission stops, FCS shall be bad and
tx_er asserted).
Also set in DMA packet buffer mode if single
frame is too large for configured packet buffer
memory size.
Cleared by writing a one to this bit.
tx_go
(TXGO)
3 ro 0x0 Transmit go - if high transmit is active.
When using the exposed FIFO interface, this bit
represents bit 3 of the network control register.
When using the DMA interface this bit represents
the tx_go variable as specified in the transmit
buffer description.