User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 131
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
5.3.5 Register Overview
A partial list of registers related to the high performance AXI port is listed in Table 5-6
5.3.6 Bandwidth Management Features
For applications requiring multiple programmable logic masters on multiple high performance AXI
interface ports simultaneously, and in the presence of a medium or heavily loaded PS system, the
management of the bandwidth per programmable logic port or “thread” becomes more difficult.
For example, if real-time type traffic is required on one thread, possibly mixed with non real-time
traffic on other threads/ports, the standard AXI 3.0 bus protocol does not explicitly provide methods
to manage priority.
The high performance AXI interface module does provide several functions to assist priority and
queue management. The majority of management functions are provided to both the programmable
logic design as PL signals and the PS as registers, as performance optimization is application
dependent. This allows maximum flexibility, while simplifying the high performance AXI interface
requirements.
The additional signals provided to the PL in addition to standard AXI3 signals are provided in
Table 5-7. The priority and occupancy management functions provided are discussed in the
following sections.
Table 5-6: High Performance (AFI) AXI Register Overview
Module Register Name Overview
AXI_HP
AFI_RDCHAN_CTRL
AFI_WRCHAN_CTRL
Select 64- or 32-bit interface width mode.
Various bandwidth management control settings.
AFI_RDCHAN_ISSUINGCAP
AFI_WRCHAN_ISSUINGCAP
Maximum outstanding read/write commands
AFI_RDQOS
AFI_WRQOS
Read/write register-based quality of service (QoS)
priority value
AFI_RDDATAFIFO_LEVEL
AFI_WRDATAFIFO_LEVEL
Read/write data FIFO register occupancy
OCM
OCM_CONTROL
Change arbitration priority of HP (and central
interconnect) accesses at OCM with respect to SCU
writes.
DDRC
axi_priority_rd_port2
axi_priority_wr_port2
Various priority settings for arbitration at DDR
controller for AXI_HP (AFI) ports 2 and 3
axi_priority_rd_port3
axi_priority_wr_port3
Various priority settings for arbitration at DDR
controller for AXI_HP (AFI) ports 0 and 1
SLCR
LVL_SHFTR_EN
Level shifters. Must be enabled before using any of the
PL AXI interfaces.