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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 132
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
QoS Priority
The AXI QoS input signals can be used to assign an arbitration priority to the read and write
commands.
Note that the PS interconnect allows either master control or programmable (register) control as a
configuration option. For the AFI, it is desirable to have the ability for masters to dynamically change
the QOS inputs. However, to provide flexibility the register field axi_hp.AFI_RDCHAN_CTRL
[FabricQosEn] is provided. This allows a static QoS value to be programmed through the high
performance AXI interface port, ignoring the PL AXI QoS inputs.
FIFO Occupancy
The level of the data and command FIFOs for both read and write are exported to the PL, allowing
you to take advantage of the QOS feature supported by the top-level interconnect. Based on the
relative levels of these FIFOs, a PL controller could dynamically change the priority of the individual
read and write requests into the high performance AXI interface block(s). For example, if a particular
PL master read data FIFO is getting too empty, the priority of the read requests could be increased.
The filling of this FIFO now takes priority over the other three FIFOs. When the FIFO reaches an
acceptable fill-level, the priority typically is reduced again. The exact scheme used to control the
relative priorities is flexible, as it must be performed in the programmable logic. Note that the “FIFO
Level” should be used as a relative level, as opposed to an exact level, because clock domain crossing
is involved.
Another possible application of the FIFO levels is using them to “look ahead” at the data fill level to
determine if data can be read or written without having to use AXI RVALID/WREADY handshake
signals. This could potentially simplify the AXI interface design logic, enabling higher speeds of
operation.
Table 5-7: Additional per-port HP PL Signals
Type PS-PL Signal Name I/O Description
FIFO occupancy
SAXIHP{0-3}RCOUNT[7:0] O Fill level of the RdData channel FIFO
SAXIHP{0-3}WCOUNT[7:0] O Fill level of the WrData channel FIFO
SAXIHP{0-3}RACOUNT[2:0] O Fill level of the RdAddr channel FIFO
SAXIHP{0-3}WACOUNT[5:0] O Fill level of the WrAddr channel FIFO
Quality of service
SAXIHP{0-3}AWQOS[3:0] I
WrAddr channel QOS input. Qualified by
SAXIHP{0-3}AWVALID
SAXIHP{0-3}ARQOS[3:0] I
RdAddr channel QOS input. Qualified by
SAXIHP{0-3}ARVALID
Interconnect
issuance
throttling
SAXIHP{0-3}RDISSUECAP1EN I
When asserted (1), indicates that the maximum
outstanding read commands (issuing capability)
should be derived from the “rdIssueCap1” register.
SAXIHP{0-3}WRISSUECAP1EN I
When asserted (1), indicates that the maximum
outstanding write commands (issuing capability)
should be derived from the “wrIssueCap1” register.