User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 133
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
Interconnect Issuance Throttling
To optimize the latency or throughput of other masters in the system such as the CPUs, it might be
desirable to constrain the number of outstanding transactions that a high-performance port
requests to the system interconnect. Issuing capability is the maximum number of outstanding
commands that a HP can request at any one time.
Control of the read and write command issuing capability of the high performance AXI interface is
available as a primary input from the logic. This option can be enabled by means o the
axi_hp.AFI_{RD, WR}CHAN_CTRL [FabricOutCmdEn] register fields.
The logic signals, SAXIHP{0-3}RDISSUECAP1_EN and SAXIHP{0-3}WRISSUECAP1_EN allow you to
change the issuing capability of the AFI block to the PS dynamically between two levels.
Write FIFO Store and Forward
The write channels can be configured to store and forward write commands or allow them to pass
through with no storage. The following two registers control the mode of write, store, and forward:
• axi_hp.AFI_WRCHAN_CTRL [WrCmdReleaseMode]
• axi_hp.AFI_WRCHAN_CTRL [WrDataThreshold]
The mode register selects between a complete AXI burst store and forward, a partial AXI burst store
and forward, or a pass through (no store at all). If absolute minimum latency for write commands is
required, the pass-through mode could be selected. However, in cases where multiple masters are
competing for the system slaves, better system performance can likely be achieved using at least the
partial AXI burst store and forward mode. This is because once an AXI write is committed at each
point throughout the PS, the entire burst must be processed before any other write data from other
write commands can be processed.
For example, using pass-through mode, if one HP port with a slow clock rate issues a long burst, a
second port with a faster clock rate might need to wait until the entire slower write data burst has
been transferred, even if all of the write data on the fast clock is available. This is different from the
case of reads, where read data interleaving is permitted.
32-bit Interface Considerations
Each physical high performance PL AXI interface is programmable to be either a 32-bit or 64-bit
interface through the register field axi_hp.AFI_{RD, WR}CHAN_CTRL [32BitEn]. Note that the read and
write channels have separate enables and can therefore be configured differently.
Upsizing and Expansion
In 32-bit mode, some form of translation between the 32-bit port and the 64-bit port is required. For
write data, the 32-bit data (and write strobes) must be aligned correctly onto the appropriate lanes
in the 64-bit domain. For read data, the appropriate lanes of the 64-bit data must be aligned onto
the 32-bit data bus. This data alignment between different width interfaces are automatically dealt
with by the high performance AXI interface module.