User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 134
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
For the 32-bit mode, an “expansion” or “upsizing” must be performed to the 64-bit bus. These are
defined as follows:
• Expansion. The AxSIZE[] and AxLEN[] signals remain unchanged on the 64-bit bus. The number
of data beats in the 64-bit domain is therefore the same as the number of data beats in the
32-bit domain. This is the simplest option but also the most inefficient in terms of bandwidth
utilization.
• Upsizing. This is an optimization that makes better use of the 64-bit bus available bandwidth.
The AxSIZE[] signal can be changed to `64-BIT (expansion case it is `32-BIT or less) and the
AxLEN[] field can potentially be adjusted to make use of the 64-bit bus. For a full width transfer,
the number of data beats in the 64-bit domain is now, at best, half the number of data beats in
the 32-bit domain. For example, a burst of 16x32-bit is upsized to a burst of 8×64-bit.
Note: Upsizing only occurs if the AxCACHE[1] bit is set; if it is not, expansion of the command
occurs. This means that you can dynamically control, on a per-command basis, whether to
expand or upsize.
Note: In 64-bit mode, there is no translation between the programmable logic transactions and the
internal 64-bit PS transactions. Whatever appears at the PL port is passed as is to the PS port. In
64-bit mode, no upsizing or expansion is performed. This also applies to narrow transactions in the
64-bit mode.
32-bit Interface Limitations
The high performance AXI interface imposes the following constraints:
1. In 32-bit mode, only burst multiples of 2, incremental burst read commands, aligned to 64-bit
boundaries are upsized. All other 32-bit commands are expanded. These include all narrow
transactions (wrap as well as fixed burst types).
2. Whenever an expanded read command is accepted from the programmable logic by the AFI, this
command is blocked until all outstanding high performance AXI interface read commands in the
pipeline are flushed. The flushing occurs automatically under control of the AFI.
The implication is that for expanded commands, performance is very limited, as command pipelining
is essentially disabled.
Note: All valid AXI command are still supported, just not optimized to take advantage of the 64-bit
bus bandwidth.
In the case of write commands completing out-of-order, no performance penalty is incurred because
the BRESP can be issued in any order directly back to the PL ports.
To be symmetric across read and write operations, the high performance AXI interface also only
upsizes 64-bit aligned burst multiples of 2, incremental burst write commands, in 32-bit mode.
However, in the case of writes, no “blocking” of expanded commands occurs. Write performance for
expanded commands in 32-bit mode is therefore much higher than read performance.