User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 136
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
5.3.9 Performance Optimization Summary
This section summarizes the most important considerations when using the high performance AXI
interface module from a software or user perspective.
• For general purpose AXI transfers, use the general purpose PS AXI ports and not these ports.
These ports are optimized for high throughput applications, but have various limitations.
• Table 5-8 summarizes the different command types issued to the high performance AXI
interface module from the PL and the way in which they are dealt with.
• When using 32-bit mode, it is strongly recommended not to use commands of the type shown
in line 6 of Table 5-8, as this impacts performance significantly.
• The QoS PL inputs can be controlled from physical programmable logic signals or statically
configured in APB registers. The signals allow QoS values to be changed on a per-command
basis. The register control is static for all commands.
• The AxCACHE[1] must be set for upsizing to occur. If this bit is not set, expansion always occurs.
• If the PL design demands a continuous read data flow after the first data beat has been read,
the design must first allow the read data FIFO to fill with the complete transaction data before
popping the first data beat out. The FIFO level is exported to the PL for this purpose. This
behavior might be useful if the PL master is not able to be throttled by RVALID after the first
data exits the read FIFO.
• Wait states can be inserted if write commands are not asserted at least one cycle ahead of the
corresponding first write data beat in 32-bit AXI channel slave interface mode.
• The PL masters should be able to handle read data interleaving. If it is desired that they not deal
with this issue, they should not issue multi-threaded read commands to both the OCM and DDR
from the same port by using the same ARID value for all outstanding read requests.
• The relationship of write FIFO occupancy to the write data ready to accept signal (WREADY)
varies as follows:
°
In 64-bit AXI mode, FIFO not full (SAXIHP0WCOUNT << 128) always implies WREADY=1.
°
In 32-bit AXI mode, there is a dependency between the write address (AWVALID) and the
write data (WVALID). If the write address is presented at least one cycle before the first beat
of any given write data burst, then the FIFO not full (SAXIHP0WCOUNT << 128) implies
WREADY=1. If not, then WREADY is deasserted until the write address is produced. The
reason for this back pressure is that in 32-bit mode, expansion/upsizing is performed on the
data into the write data FIFO.
• Write response (BVALID) latency is dependent on many factors, such as DDR latency, DDR
transaction reordering, and other conflicting traffic (including higher-priority transactions).
Write commands and data are sent the entire path to the slave (DDR or OCM) and the response
is issued by the slave to return to the high performance AXI interface. Transactions issued after
reception of the write response is guaranteed to be committed later at the slave than the
responded write transaction. Note that by default, all PS peripherals are set to secure Trustzone
mode. This means that any non-secure accesses indicated with AxPROT[1]=1 will received a
DECERR response.