User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1399
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
reg7_clean_inv_way 0x000007FC 32 mixed 0x00000000 Clean and Invalidate by Way
Writes each line of the specified
L2 cache ways to L3 main
memory if the line is marked
as valid and dirty. The lines are
marked as not valid. Completes
as a background task with
the way, or ways, locked,
preventing allocation.
reg9_d_lockdown0
0x00000900 32 mixed 0x00000000 All reg9 registers can prevent
new addresses from being
allocated and can also prevent
data from being evicted out of
the L2 cache.
Each register pair
(reg9_d_lockdown<n>,
reg9_i_lockdown<n>) is for
accesses coming from a
particular master.
Each bit of each register sets
lockdown for a corresponding
way, i.e. bit 0 for way 0, bit 1 for
way 1, etc.
0 allocation can occur in the
corresponding way.
1 there is no allocation in the
corresponding way.
reg9_i_lockdown0
0x00000904 32 mixed 0x00000000 instruction lock down 0
reg9_d_lockdown1
0x00000908 32 mixed 0x00000000 data lock down 1
reg9_i_lockdown1
0x0000090C 32 mixed 0x00000000 instruction lock down 1
reg9_d_lockdown2
0x00000910 32 mixed 0x00000000 data lock down 2
reg9_i_lockdown2
0x00000914 32 mixed 0x00000000 instruction lock down 2
reg9_d_lockdown3
0x00000918 32 mixed 0x00000000 data lock down 3
reg9_i_lockdown3
0x0000091C 32 mixed 0x00000000 instruction lock down 3
reg9_d_lockdown4
0x00000920 32 mixed 0x00000000 data lock down 4
reg9_i_lockdown4
0x00000924 32 mixed 0x00000000 instruction lock down 4
reg9_d_lockdown5
0x00000928 32 mixed 0x00000000 data lock down 5
reg9_i_lockdown5
0x0000092C 32 mixed 0x00000000 instruction lock down 5
reg9_d_lockdown6
0x00000930 32 mixed 0x00000000 data lock down 6
reg9_i_lockdown6
0x00000934 32 mixed 0x00000000 instruction lock down 6
reg9_d_lockdown7
0x00000938 32 mixed 0x00000000 data lock down 7
reg9_i_lockdown7
0x0000093C 32 mixed 0x00000000 instruction lock down 7
Register Name Address Width Type Reset Value Description