User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 142
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
5.6.2 AXI Clocks and Resets
Each interface has a single clock for all five channels that make up an interface. This clock is provided
by the PL.
All clocks must be active and all resets must be inactive on all PS-PL AXI interfaces for the GPV to
function properly. The entire PS might hang if this condition is not satisfied and a GPV access is
MAXIGP{0,1}WID[11:0] O SAXIGP{0,1}WID[5:0]
SAXIHP{0:3}WID[5:0]
SAXIACPWID[2:0]
I
MAXIGP{0,1}WLAST O SAXIGP{0,1}WLAST
SAXIHP{0:3}WLAST
SAXIACPWLAST
I
MAXIGP{0,1}WSTRB[3:0] O SAXIGP{0,1}WSTRB[3:0]
SAXIHP{0:3}WSTRB[7:0]
SAXIACPWSTRB[7:0]
I
~~
SAXIHP{0:3}WCOUNT[7:0]
~
O
~~
SAXIHP{0:3}WACOUNT[5:0]
~
O
~~
SAXIHP{0:3}WRISSUECAP1EN
~
I
Write Response
MAXIGP{0,1}BVALID I SAXIGP{0,1}BVALID
SAXIHP{0:3}BVALID
SAXIACPBVALID
O
MAXIGP{0,1}BREADY O SAXIGP{0,1}BREADY
SAXIHP{0:3}BREADY
SAXIACPBREADY
I
MAXIGP{0,1}BID[11:0] I SAXIGP{0,1}BID[5:0]
SAXIHP{0:3}BID[5:0]
SAXIACPBID[2:0]
O
MAXIGP{0,1}BRESP[1:0] I SAXIGP{0,1}BRESP[1:0]
SAXIHP{0:3}BRESP[1:0]
SAXIACPBRESP[1:0]
O
Table 5-9: AXI Signals Summary (Cont’d)
AXI Channel
AXI PS Masters AXI PS Slaves
M_AXI_GP{0,1} I/O
S_AXI_GP{0,1}
S_AXI_HP{0:3}
S_AXI_ACP
I/O