User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1435
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
ICCIDR 0x000001FC 32 ro 0x3901243B CPU Interface Implementer
Identification Register
Global_Timer_Counter
_Register0
0x00000200 32 rw 0x00000000 Global Timer Counter Register 0
Global_Timer_Counter
_Register1
0x00000204 32 rw 0x00000000 Global Timer Counter Register 1
Global_Timer_Control_
Register
0x00000208 32 rw 0x00000000 Global Timer Control Register
Global_Timer_Interrup
t_Status_Register
0x0000020C 32 rw 0x00000000 Global Timer Interrupt Status
Register
Comparator_Value_Re
gister0
0x00000210 32 rw 0x00000000 Comparator Value Register_0
Comparator_Value_Re
gister1
0x00000214 32 rw 0x00000000 Comparator Value Register_1
Auto_increment_Regis
ter
0x00000218 32 rw 0x00000000 Auto-increment Register
Private_Timer_Load_R
egister
0x00000600 32 rw 0x00000000 Private Timer Load Register
Private_Timer_Counter
_Register
0x00000604 32 rw 0x00000000 Private Timer Counter Register
Private_Timer_Control
_Register
0x00000608 32 rw 0x00000000 Private Timer Control Register
Private_Timer_Interru
pt_Status_Register
0x0000060C 32 rw 0x00000000 Private Timer Interrupt Status
Register
Watchdog_Load_Regis
ter
0x00000620 32 rw 0x00000000 Watchdog Load Register
Watchdog_Counter_Re
gister
0x00000624 32 rw 0x00000000 Watchdog Counter Register
Watchdog_Control_Re
gister
0x00000628 32 rw 0x00000000 Watchdog Control Register
Watchdog_Interrupt_St
atus_Register
0x0000062C 32 rw 0x00000000 Watchdog Interrupt Status
Register
Watchdog_Reset_Statu
s_Register
0x00000630 32 rw 0x00000000 Watchdog Reset Status Register
Watchdog_Disable_Re
gister
0x00000634 32 rw 0x00000000 Watchdog Disable Register
ICDDCR
0x00001000 32 rw 0x00000000 Distributor Control Register
ICDICTR
0x00001004 32 ro 0x0000FC22 Interrupt Controller Type
Register
ICDIIDR
0x00001008 32 ro 0x0102043B Distributor Implementer
Identification Register
Register Name Address Width Type Reset Value Description