User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1438
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
ICDIPTR12 0x00001830 32 rw 0x00000000 Interrupt Processor Targets
Register 12
ICDIPTR13
0x00001834 32 rw 0x00000000 Interrupt Processor Targets
Register 13
ICDIPTR14
0x00001838 32 rw 0x00000000 Interrupt Processor Targets
Register 14
ICDIPTR15
0x0000183C 32 rw 0x00000000 Interrupt Processor Targets
Register 15
ICDIPTR16
0x00001840 32 rw 0x00000000 Interrupt Processor Targets
Register 16
ICDIPTR17
0x00001844 32 rw 0x00000000 Interrupt Processor Targets
Register 17
ICDIPTR18
0x00001848 32 rw 0x00000000 Interrupt Processor Targets
Register 18
ICDIPTR19
0x0000184C 32 rw 0x00000000 Interrupt Processor Targets
Register 19
ICDIPTR20
0x00001850 32 rw 0x00000000 Interrupt Processor Targets
Register 20
ICDIPTR21
0x00001854 32 rw 0x00000000 Interrupt Processor Targets
Register 21
ICDIPTR22
0x00001858 32 rw 0x00000000 Interrupt Processor Targets
Register 22
ICDIPTR23
0x0000185C 32 rw 0x00000000 Interrupt Processor Targets
Register 23
ICDICFR0
0x00001C00 32 ro 0x00000000 Interrupt Configuration
Register 0
ICDICFR1
0x00001C04 32 rw 0x00000000 Interrupt Configuration
Register 1
ICDICFR2
0x00001C08 32 rw 0x00000000 Interrupt Configuration
Register 2
ICDICFR3
0x00001C0C 32 rw 0x00000000 Interrupt Configuration
Register 3
ICDICFR4
0x00001C10 32 rw 0x00000000 Interrupt Configuration
Register 4
ICDICFR5
0x00001C14 32 rw 0x00000000 Interrupt Configuration
Register 5
ppi_status
0x00001D00 32 ro 0x00000000 PPI Status Register
spi_status_0
0x00001D04 32 ro 0x00000000 SPI Status Register 0
spi_status_1
0x00001D08 32 ro 0x00000000 SPI Status Register 1
ICDSGIR
0x00001F00 32 rw 0x00000000 Software Generated Interrupt
Register
Register Name Address Width Type Reset Value Description