User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 145
UG585 (v1.11) September 27, 2016
Chapter 5: Interconnect
To use the L1 exclusive monitor, the addressed MMU region must be set to be inner cacheable and
inner cache write-back with write-allocate. This allows an address targeted by a particular exclusive
access to always be allocated to L1 cache.
To use the L3 exclusive monitor, the access must not terminate at the APU L2 cache. From the ARM
CPU perspective, this means the address must be shareable, normal and non-cacheable. Also, the L2
cache controller shared override option (bit 22 in the L2 auxiliary control register) must be set in the
auxiliary control register. By default in the APU L2 cache controller, any non-cacheable shared reads
are treated as cacheable non-allocatable, while non-cacheable shared writes are treated as cacheable
write-through/no write-allocate. The L2 cache controller shared override option in the PL310
auxiliary control register overrides this behavior and prevents allocation into L2 cache.
5.8.2 ACP
The PL ACP port does not support exclusive access to coherent memory. Therefore, if the ACP needs
to perform exclusive accesses with the CPUs, the access must go to L3: DDR or PL.
5.8.3 DDRC
The following are the supported features for exclusive accesses to the PS DDR controller:
• The AXI port supports concurrent monitoring of two exclusive addresses (with different IDs).
• Burst type INCR/WRAP, length='h0 - 'hF, is supported.
• The slave supports OKAY and EXOKAY responses for exclusive accesses.
°
According to the AXI specification, the slave sends out an EXOKAY response for successful
exclusive access transactions. For DDRC, this includes reads (up to two active) and writes
that match a preceding exclusive read transaction, if the monitored location(s) is still valid.
°
If a monitored location is overwritten by another exclusive or non-exclusive write
transaction through any slave port before its corresponding exclusive write, the slave
returns an OKAY response for the exclusive write and will not update the corresponding
memory locations.
The DDRC exclusive monitor uses AXI bus ID to determine which master is doing the exclusive load
and store. While it is possible for a master to generate different IDs, a particular ID will always
originate from the same master. The master should also make sure to use the same ID for their LDREX
and STREX pair. Cortex-A9 processor will generate the same ID for its LDREX/STREX pair.
There are a some limitations:
1. While only two address locations (ranges) can be monitored concurrently by the DDRC, either of
these locations can be updated by another exclusive read transaction while the current
transactions have not been completed by their corresponding exclusive writes. In this case, the
exclusive write for an earlier monitored address location will receive an OKAY response. The