User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 148
UG585 (v1.11) September 27, 2016
Chapter 6
Boot and Configuration
6.1 Introduction
Immediately after the PS_POR_B reset pin deasserts, the hardware samples the boot strap pins and
optionally enables the PS clock PLLs. Then, the PS begins executing the BootROM code in the
on-chip ROM to boot the system. The POR resets the entire device with no previous state saved. The
non-POR type resets also cause the BootROM to execute, but without the hardware sampling the
strap pins. After a non-POR reset, some registers values are preserved and the device is aware of its
previous security mode. Non-POR resets include the PS_SRST_B pin and several internal reset
sources.
The BootROM is the first software to run in the APU. The BootROM executes on CPU 0 and CPU 1
executes the wait-for-event (WFE) instruction. The main tasks of the BootROM are to configure the
system, copy the Boot Image FSBL/User code from the boot device to the OCM, and then branch the
code execution to the OCM. Optionally, the FSBL/User code can be executed directly from a
Quad-SPI or NOR device in a non-secure environment.
The PS Master boot device holds one or more boot images. A boot image is made up of the
BootROM Header and the first stage boot loader (FSBL). The boot device can also hold a bitstream
to configure the PL and an embedded operating system, but these are not accessed by the
BootROM. The flash memory device for boot can be Quad-SPI, NAND, NOR, or SD card.
The BootROM execution flow is affected by the pin strap settings, the BootROM Header, and what it
discovers about the system. The BootROM can execute in a secure environment with encrypted
FSBL/User code, or a non-secure environment. After the BootROM executes, the FSBL/User code
takes responsibility of the system as described in UG821
, Zynq-7000 All Programmable SoC Software
Developers Guide.
For development, the system can be booted in JTAG mode. Or, JTAG can be enabled after a
non-secure flash device boot. JTAG always implies a non-secure environment, but it allows for access
to the ARM debug access port (DAP) controller in the CPU complex (APU) and the Xilinx test access
port (TAP) controller in the PL.
PS Master Boot Mode
In master boot mode, the system boots from a flash memory device. Here, the BootROM configures
the PS to access the boot device, reads the boot header, validates the header, and then usually copies
the FSBL/User code to the OCM memory. Master mode can be a secure or non-secure environment.