User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 149
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
In secure mode, the boot image is always written to OCM memory by the CPU. From there, it is sent
(using DMA) in and out of the AES/HMAC units for decryption and authentication. The decrypted
boot image is written back to OCM memory and executed after the BootROM is finished. Security
hardware is described in this chapter and in Chapter 32, Device Secure Boot.
In non-secure mode, the BootROM header can instruct the PS to execute the boot image directly
from a Quad-SPI or NOR boot device that supports the execute-in-place option. In other cases, the
FSBL/User code is copied to the OCM memory for execution.
If the BootROM header in the flash device is invalid, the BootROM searches for another header. The
header search continues until a valid header is found or the entire range has been searched. The
BootROM header search is supported for Quad-SPI, NAND, and NOR boot modes. For SD card boot
mode, only one header is read.
JTAG Slave Boot
In JTAG boot mode, the BootROM does minimal system configuration and enables a JTAG interface.
Then, the system goes into an idle state waiting for the DAP controller to restart CPU 0. The cascade
JTAG boot mode loops the DAP and TAP controllers, and is the most common JTAG boot mode. The
independent JTAG boot mode connects the TAP controller to the PL JTAG pins and gives time for the
user to configure the PL using the TAP controller to connect the DAP controller to the EMIO JTAG
interface. The paths are shown in Figure 6-7, page 189.
In non-secure master boot mode, the JTAG interface is enabled for debug when the PL is
powered-up. The JTAG interface can be used to access the TAP and DAP controllers.
Boot and Configuration Subsections
Boot and Configuration is divided into the following sections:
• Figure 6-1
°
Overview of bring-up and configuration
• Device Start-up
°
Power-up, resets, clocks, Boot mode pins
• BootROM
°
Execution flow, BootROM header
°
Boot modes, image search, multiboot
°
Error codes, system state post-BootROM
• Device Boot and PL Configuration
°
PL initialization, configuration, and enable
°
PS/PL bring-up examples
°
PCAP bridge, JTAG (cascade/independent)
• Reference Section
°
PL bring-up time factors, register overview, and device IDs