User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 151
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
from the boot device (execute-in-place). All of the header parameters are described in section
6.3.2 BootROM Header.
The last two functions of the BootROM are to disable access to its ROM code and transfer CPU code
execution to the FSBL/User code. The execution of the BootROM is detailed in section
6.3.1 BootROM Flowchart.
PL Initialization and Configuration
The PL must be powered-up before it can be initialized and then configured with the bitstream. The
power-up and bring-up stages of the PL operate independently of the PS, but PL power up needs to
maintain a certain timing relationship with the POR reset signal of the PS. For more details refer to
section 6.3.3 BootROM Performance: PS_POR_B De-assertion Guidelines, page 177.
The PL can be under the control of FSBL/User code using GPIOs or serial interfaces to external
devices. Internally, the BootROM and FSBL/User code can determine the state of the PL power.
FSBL/User code can receive interrupts when the PL power state changes.
The PL boot process has four stages: start-up, initialize, configure, and enable. The start-up stage is
self-timed after power is ramped-up to a stable state. The initialization stage clears the SRAM cells in
the PL to prepare it for programming by the bitstream (configuration stage). The functional PS-PL
interfaces are then enabled under PS software control. The BootROM does not configure the PL, but
it can read its status to determine when it can enable the PL JTAG chain and also when it needs to use
the HMAC/AES decryption hardware.
Secure PS Images and PL Bitstreams
The secure environment starts with an encrypted boot process where the PS software acts as the
system master and the BootROM reads an encrypted FSBL/user code image from the selected flash
memory device and processes it using the hardened, PL based Hash-based Message Authentication
Code (HMAC) and an Advanced Encryption Standard (AES) module with a Cipher Block Chaining
Mode (CBC). These modules are accessed from the PS through the DevC interface and the
downstream Processor Configuration Access Port (PCAP) located in the PL.
The BootROM verifies that the PL has power before attempting to decrypt the FSBL/User code. After
the PS has finished executing the BootROM, the PL can be configured by the FSBL/user software
using an encrypted bitstream or the PL can be configured or reconfigured later.
The low-level secure environment starts at the I/O pin activity and all potential access points to the
PS operating environment. The secure operating environment is maintained through the BootROM
execution and transferred to a secure software operating environment.
Various device configuration functions and operating examples are described in section 6.4 Device
Boot and PL Configuration. The details of secure boot are covered in Chapter 32, Device Secure Boot.
Security at the operating system level are described in WP429
, TrustZone Technology Support in
Zynq-7000 All Programmable SoC. The BootROM can also authenticate files using RSA, refer to section
32.2.5 RSA Authentication.