User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 152
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
Software Developers Guide and Kit
The boot modes and operations are summarized in chapter 3 of the UG821 Zynq-7000 Software
Developers Guide. The chapter describes boot methods and ways to program the hardware using the
FSBL. The software developers guide also discusses software architectures, tools, and various boot
environments, including Linux U-Boot.
The software developers kit (SDK) can be used to develop and debug bare-metal applications. It can
also be used to create FSBL/User code boot images and application programs running on an
operating system.
6.1.1 PS Hardware Boot Stages
The PS hardware boot stages include power supply ramping, clocking, resets, pin strap sampling and
PLL initialization. The PL can be powered up while the PS boots up. The PL boot process is described
in section 6.1.7 PL Boot Process.
External PS Control Pins
Within several clock cycles of the PS_CLK reference clock, the hardware samples the seven Boot
Mode strap pins (see Figure 6-4) and stores their settings in read-only registers. The strap pins
define the initial voltage sensitivity for the MIO input buffers, select the JTAG chain route, and select
the flash device that contains the boot image. Development boards automatically deassert the
PS_POR_B reset pin after the board is powered-up. These boards also include a POR reset button that
can be used to generate a POR reset. A non-POR system reset can be generated using the PS_SRST_B
reset pin. The details of the PS hardware boot functions are described in section 6.2 Device Start-up.
PS PLL Initialization
The PS PLLs are enabled by MIO pin 6, the BOOT_MODE[4] strap pin. When the PLLs are enabled, the
execution of the BootROM is delayed until the PLL outputs lock. If the PLLs are not enabled, the
PS_CLK reference clock input pin is bypassed around the PLLs and the clock subsystem is driven at
the frequency of PS_CLK input. The PLL clocks are described in section 6.2.3 Clocks and PLLs and in
Chapter 25, Clocks.
6.1.2 PS Software Boot Stages
The PS software boot process is controlled by the BootROM and then the FSBL/User code. The
BootROM operation is influenced by the boot strap pins, the BootROM Header, and what the
BootROM detects in the system.
Stage 0 (BootROM: BootROM Header)
Hard-coded BootROM executes on the primary CPU (CPU 0) after a power-on reset (POR) or
non-POR system reset (PS_SRST_B, debug, watchdog, software). The BootROM reads the BootROM
Header programmed into the boot flash device to determine the boot flow and transitions to
stage 1. After the hardware boot sequence, both CPUs start executing the same BootROM code