User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 154
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
JTAG (Slave Mode Boot)
The JTAG boot mode is considered a Slave Mode boot and is always a non-secure boot mode. The
JTAG chain can be configured in cascade or independent mode. During the boot sequence, the chain
is configured according to the setting of the MIO [2] boot strapping pin. Normally, the system is
configured for cascade mode. When the TRM refers to JTAG boot mode, it means JTAG cascade mode
unless stated otherwise. The JTAG interface is enabled in all non-secure boot modes.
• Cascade JTAG chain (most popular):
°
Access DAP and TAP controllers through PL JTAG.
• Independent JTAG chain (common):
°
Access TAP controller through PL JTAG.
°
Access DAP controller through EMIO JTAG via SelectIO pins after configuring the PL with a
bitstream.
• Independent JTAG chain (rarely used):
°
Access TAP controller through PL JTAG.
°
Access DAP controller through MIO PJTAG.
The JTAG interfaces are discussed in section 6.4.5 PL Control via User-JTAG and detailed in
Chapter 27, JTAG and DAP Subsystem.
6.1.5 BootROM Execution
The BootROM execution begins soon after a POR or non-POR reset. A POR reset causes the Hardware
Boot stage to occur and then starts the BootROM execution. A non-POR reset skips the hardware
stage and starts the BootROM execution almost immediately.
The BootROM executes the on-chip ROM code to perform the system boot process. The BootROM
disables all access to the ROM code before transferring code execution over to the FSBL/User code.
Details of how the system memory is remapped are shown in Figure 6-11, page 202.
Early in the BootROM execution, it sets up the APU and performs some self-checking. It reads the
boot mode pin information and, if the boot mode is not JTAG, the BootROM configures the controller
for the selected boot device. The BootROM reads the BootROM Header to further configure the
system for the desired boot process. In addition to the BootROM Header, the boot device provides
the first stage boot loader (FSBL) and/or user code that takes over system control when the
BootROM is done.
The boot device can also provide an image for the operating system, refer to UG821
, Zynq-7000 All
Programmable SoC Software Developers Guide. BootROM execution is detailed in section
6.3.1 BootROM Flowchart. The BootROM Header is described in 6.3.2 BootROM Header.
Secure Boot
The BootROM can operate in non-secure or secure mode depending on the configuration setup by
the BootROM Header. In secure mode, the FSBL/User code is moved from the flash device, decrypted
and written into the OCM memory. The CPU executes the code from the OCM.