User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1540
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register (sdio) SDMA_system_address_register
Register SDMA_system_address_register Details
This register contains the system memory address for a DMA transfer. When the Host Controller (HC)
stops a DMA transfer, this register shall point to the system address of the next contiguous data position.
It can be accessed only if no transaction is executing (i.e. after a transaction has stopped). Read operations
during transfer return an invalid value. The Host Driver (HD) shall initialize this register before starting a
DMA transaction. After DMA has stopped, the next system address of the next contiguous data position
can be read from this register. The DMA transfer waits at every boundary specified by the Host DMA
Normal_interrupt_sign
al_enable_Error_interr
upt_signal_enable
0x00000038 30 mixed 0x00000000 Normal interrupt signal enable
register
Error interrupt signal enable
register
Auto_CMD12_error_st
atus
0x0000003C 8 ro 0x00000000 Auto CMD12 error status
register
Capabilities
0x00000040 31 ro 0x69EC0080 Capabilities register
Maximum_current_cap
abilities
0x00000048 24 ro 0x00000001 Maximum current capabilities
register
Force_event_for_Auto
Cmd12_Error_Status_F
orce_event_register_for
_error_interrupt_status
0x00000050 32 mixed 0x00000000 Force event register for Auto
CMD12 error status register
Force event register for error
interrupt status
ADMA_error_status
0x00000054 3 mixed 0x00000000 ADMA error status register
ADMA_system_addres
s
0x00000058 32 rw 0x00000000 ADMA system address register
Boot_Timeout_control
0x00000060 32 rw 0x00000000 Boot Timeout control register
Debug_Selection
0x00000064 1 wo 0x00000000 Debug Selection Register
SPI_interrupt_support
0x000000F0 8 rw 0x00000000 SPI interrupt support register
Slot_interrupt_status_
Host_controller_versio
n
0x000000FC 32 ro 0x89010000 Slot interrupt status register and
Host controller version register
Name SDMA_system_address_register
Relative Address 0x00000000
Absolute Address sd0: 0xE0100000
sd1: 0xE0101000
Width 32 bits
Access Type rw
Reset Value 0x00000000
Description System DMA Address Register
Register Name Address Width Type Reset Value Description