User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 155
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
If the system is booted in secure mode and then reset by a non-POR reset with a BootROM Header
that indicates a non-secure boot, then the system goes into a secure lockdown with error code
0x201A.
BootROM Header Search
If the BootROM does not detect a valid BootROM Header, the BootROM performs a search function
to find another BootROM Header. The search function is described in section 6.3.10 BootROM
Header Search. BootROM Header search is supported for Quad-SPI, NAND and NOR boot modes.
The BootROM Header is never encrypted and the search functions work with an encrypted or
un-encrypted FSBL/User code images.
BootROM Execution Influencers
The BootROM is influenced by different conditions. Some are intentional, others are not.
• Pin strapping
• Reset signal pins
• Validity of the BootROM Header (checksum for header search)
• BootROM Header boot mode and conflicts that cause lockdown errors
Error Detection, Device Lockdown and Error Codes
If the BootROM detects an error while executing the BootROM Header, it locks down the system and
generate an error code. There are two lockdown types:
• Secure Lockdown (no access to device, requires a POR to restart the system).
• Non-secure Lockdown (JTAG might be enabled and any system reset can restart the system to
run the BootROM again).
When a lockdown occurs, the error code is written into the slcr.REBOOT_STATUS register. The error
codes are listed in Table 6-20, page 198.
6.1.6 FSBL / User Code Execution
The FSBL/User code executes after the BootROM is finished. The FSBL/User code reconfigures the PS
as needed and optionally configures the PL. The BootROM loads the FSBL/User code into the OCM
unless the execute-in-place option is enabled. The FSBL/User code operations:
• Initialize the PS using the PS7 Init data that is generated by Vivado tools (MIO, DDR, etc.)
• Program the PL using a bitstream (if provided).
• Load the second stage bootloader or bare-metal application code into DDR memory.
• Hand off system control to the second stage bootloader or bare-metal application.
The FSBL/User code requirements are explained in UG821
, Zynq-7000 All Programmable SoC Software
Developers Guide. FSBL code can be generated by the Vivado SDK for bare-metal applications.