User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1580
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
B.28 System Level Control Registers (slcr)
Register Summary
Module Name System Level Control Registers (slcr)
Base Address 0xF8000000 slcr
Description System Level Control Registers
Vendor Info Xilinx Zynq slcr
Register Name Address Width Type Reset Value Description
SCL
0x00000000 32 rw 0x00000000 Secure Configuration Lock
SLCR_LOCK
0x00000004 32 wo 0x00000000 SLCR Write Protection Lock
SLCR_UNLOCK
0x00000008 32 wo 0x00000000 SLCR Write Protection Unlock
SLCR_LOCKSTA
0x0000000C 32 ro 0x00000001 SLCR Write Protection Status
ARM_PLL_CTRL
0x00000100 32 rw 0x0001A008 ARM PLL Control
DDR_PLL_CTRL
0x00000104 32 rw 0x0001A008 DDR PLL Control
IO_PLL_CTRL
0x00000108 32 rw 0x0001A008 IO PLL Control
PLL_STATUS
0x0000010C 32 ro 0x0000003F PLL Status
ARM_PLL_CFG
0x00000110 32 rw 0x00177EA0 ARM PLL Configuration
DDR_PLL_CFG
0x00000114 32 rw 0x00177EA0 DDR PLL Configuration
IO_PLL_CFG
0x00000118 32 rw 0x00177EA0 IO PLL Configuration
ARM_CLK_CTRL
0x00000120 32 rw 0x1F000400 CPU Clock Control
DDR_CLK_CTRL
0x00000124 32 rw 0x18400003 DDR Clock Control
DCI_CLK_CTRL
0x00000128 32 rw 0x01E03201 DCI clock control
APER_CLK_CTRL
0x0000012C 32 rw 0x01FFCCCD AMBA Peripheral Clock Control
USB0_CLK_CTRL
0x00000130 32 rw 0x00101941 USB 0 ULPI Clock Control
USB1_CLK_CTRL
0x00000134 32 rw 0x00101941 USB 1 ULPI Clock Control
GEM0_RCLK_CTRL
0x00000138 32 rw 0x00000001 GigE 0 Rx Clock and Rx Signals
Select
GEM1_RCLK_CTRL
0x0000013C 32 rw 0x00000001 GigE 1 Rx Clock and Rx Signals
Select
GEM0_CLK_CTRL
0x00000140 32 rw 0x00003C01 GigE 0 Ref Clock Control
GEM1_CLK_CTRL
0x00000144 32 rw 0x00003C01 GigE 1 Ref Clock Control
SMC_CLK_CTRL
0x00000148 32 rw 0x00003C21 SMC Ref Clock Control
LQSPI_CLK_CTRL
0x0000014C 32 rw 0x00002821 Quad SPI Ref Clock Control