User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1582
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
GEM_RST_CTRL 0x00000214 32 rw 0x00000000 Gigabit Ethernet SW Reset
Control
SDIO_RST_CTRL
0x00000218 32 rw 0x00000000 SDIO Software Reset Control
SPI_RST_CTRL
0x0000021C 32 rw 0x00000000 SPI Software Reset Control
CAN_RST_CTRL
0x00000220 32 rw 0x00000000 CAN Software Reset Control
I2C_RST_CTRL
0x00000224 32 rw 0x00000000 I2C Software Reset Control
UART_RST_CTRL
0x00000228 32 rw 0x00000000 UART Software Reset Control
GPIO_RST_CTRL
0x0000022C 32 rw 0x00000000 GPIO Software Reset Control
LQSPI_RST_CTRL
0x00000230 32 rw 0x00000000 Quad SPI Software Reset
Control
SMC_RST_CTRL
0x00000234 32 rw 0x00000000 SMC Software Reset Control
OCM_RST_CTRL
0x00000238 32 rw 0x00000000 OCM Software Reset Control
FPGA_RST_CTRL
0x00000240 32 rw 0x01F33F0F FPGA Software Reset Control
A9_CPU_RST_CTRL
0x00000244 32 rw 0x00000000 CPU Reset and Clock control
RS_AWDT_CTRL
0x0000024C 32 rw 0x00000000 Watchdog Timer Reset Control
REBOOT_STATUS
0x00000258 32 rw 0x00400000 Reboot Status, persistent
BOOT_MODE
0x0000025C 32 mixed x Boot Mode Strapping Pins
APU_CTRL
0x00000300 32 rw 0x00000000 APU Control
WDT_CLK_SEL
0x00000304 32 rw 0x00000000 SWDT clock source select
TZ_DMA_NS
0x00000440 32 rw 0x00000000 DMAC TrustZone Config
TZ_DMA_IRQ_NS
0x00000444 32 rw 0x00000000 DMAC TrustZone Config for
Interrupts
TZ_DMA_PERIPH_NS
0x00000448 32 rw 0x00000000 DMAC TrustZone Config for
Peripherals
PSS_IDCODE
0x00000530 32 ro x PS IDCODE
DDR_URGENT
0x00000600 32 rw 0x00000000 DDR Urgent Control
DDR_CAL_START
0x0000060C 32 mixed 0x00000000 DDR Calibration Start Triggers
DDR_REF_START
0x00000614 32 mixed 0x00000000 DDR Refresh Start Triggers
DDR_CMD_STA
0x00000618 32 mixed 0x00000000 DDR Command Store Status
DDR_URGENT_SEL
0x0000061C 32 rw 0x00000000 DDR Urgent Select
DDR_DFI_STATUS
0x00000620 32 mixed 0x00000000 DDR DFI status
MIO_PIN_00
0x00000700 32 rw 0x00001601 MIO Pin 0 Control
MIO_PIN_01
0x00000704 32 rw 0x00001601 MIO Pin 1 Control
MIO_PIN_02
0x00000708 32 rw 0x00000601 MIO Pin 2 Control
MIO_PIN_03
0x0000070C 32 rw 0x00000601 MIO Pin 3 Control
Register Name Address Width Type Reset Value Description