User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1584
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
MIO_PIN_38 0x00000798 32 rw 0x00001601 MIO Pin 38 Control
MIO_PIN_39
0x0000079C 32 rw 0x00001601 MIO Pin 39 Control
MIO_PIN_40
0x000007A0 32 rw 0x00001601 MIO Pin 40 Control
MIO_PIN_41
0x000007A4 32 rw 0x00001601 MIO Pin 41 Control
MIO_PIN_42
0x000007A8 32 rw 0x00001601 MIO Pin 42 Control
MIO_PIN_43
0x000007AC 32 rw 0x00001601 MIO Pin 43 Control
MIO_PIN_44
0x000007B0 32 rw 0x00001601 MIO Pin 44 Control
MIO_PIN_45
0x000007B4 32 rw 0x00001601 MIO Pin 45 Control
MIO_PIN_46
0x000007B8 32 rw 0x00001601 MIO Pin 46 Control
MIO_PIN_47
0x000007BC 32 rw 0x00001601 MIO Pin 47 Control
MIO_PIN_48
0x000007C0 32 rw 0x00001601 MIO Pin 48 Control
MIO_PIN_49
0x000007C4 32 rw 0x00001601 MIO Pin 49 Control
MIO_PIN_50
0x000007C8 32 rw 0x00001601 MIO Pin 50 Control
MIO_PIN_51
0x000007CC 32 rw 0x00001601 MIO Pin 51 Control
MIO_PIN_52
0x000007D0 32 rw 0x00001601 MIO Pin 52 Control
MIO_PIN_53
0x000007D4 32 rw 0x00001601 MIO Pin 53 Control
MIO_LOOPBACK
0x00000804 32 rw 0x00000000 Loopback function within MIO
MIO_MST_TRI0
0x0000080C 32 rw 0xFFFFFFFF MIO pin Tri-state Enables, 31:0
MIO_MST_TRI1
0x00000810 32 rw 0x003FFFFF MIO pin Tri-state Enables, 53:32
SD0_WP_CD_SEL
0x00000830 32 rw 0x00000000 SDIO 0 WP CD select
SD1_WP_CD_SEL
0x00000834 32 rw 0x00000000 SDIO 1 WP CD select
LVL_SHFTR_EN
0x00000900 32 rw 0x00000000 Level Shifters Enable
OCM_CFG
0x00000910 32 rw 0x00000000 OCM Address Mapping
Reserved
0x00000A1C 32 rw 0x00010101 Reserved
GPIOB_CTRL
0x00000B00 32 rw 0x00000000 PS IO Buffer Control
GPIOB_CFG_CMOS18
0x00000B04 32 rw 0x00000000 MIO GPIOB CMOS 1.8V config
GPIOB_CFG_CMOS25
0x00000B08 32 rw 0x00000000 MIO GPIOB CMOS 2.5V config
GPIOB_CFG_CMOS33
0x00000B0C 32 rw 0x00000000 MIO GPIOB CMOS 3.3V config
GPIOB_CFG_HSTL
0x00000B14 32 rw 0x00000000 MIO GPIOB HSTL config
GPIOB_DRVR_BIAS_C
TRL
0x00000B18 32 mixed 0x00000000 MIO GPIOB Driver Bias Control
DDRIOB_ADDR0
0x00000B40 32 rw 0x00000800 DDR IOB Config for A[14:0],
CKE and DRST_B
Register Name Address Width Type Reset Value Description