User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1585
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register (slcr) SCL
DDRIOB_ADDR1 0x00000B44 32 rw 0x00000800 DDR IOB Config for BA[2:0],
ODT, CS_B, WE_B, RAS_B and
CAS_B
DDRIOB_DATA0
0x00000B48 32 rw 0x00000800 DDR IOB Config for Data 15:0
DDRIOB_DATA1
0x00000B4C 32 rw 0x00000800 DDR IOB Config for Data 31:16
DDRIOB_DIFF0
0x00000B50 32 rw 0x00000800 DDR IOB Config for DQS 1:0
DDRIOB_DIFF1
0x00000B54 32 rw 0x00000800 DDR IOB Config for DQS 3:2
DDRIOB_CLOCK
0x00000B58 32 rw 0x00000800 DDR IOB Config for Clock
Output
DDRIOB_DRIVE_SLE
W_ADDR
0x00000B5C 32 rw 0x00000000 Drive and Slew controls for
Address and Command pins of
the DDR Interface
DDRIOB_DRIVE_SLE
W_DATA
0x00000B60 32 rw 0x00000000 Drive and Slew controls for DQ
pins of the DDR Interface
DDRIOB_DRIVE_SLE
W_DIFF
0x00000B64 32 rw 0x00000000 Drive and Slew controls for DQS
pins of the DDR Interface
DDRIOB_DRIVE_SLE
W_CLOCK
0x00000B68 32 rw 0x00000000 Drive and Slew controls for
Clock pins of the DDR Interface
DDRIOB_DDR_CTRL
0x00000B6C 32 rw 0x00000000 DDR IOB Buffer Control
DDRIOB_DCI_CTRL
0x00000B70 32 rw 0x00000020 DDR IOB DCI Config
DDRIOB_DCI_STATU
S
0x00000B74 32 mixed 0x00000000 DDR IO Buffer DCI Status
Name SCL
Relative Address 0x00000000
Absolute Address 0xF8000000
Width 32 bits
Access Type rw
Reset Value 0x00000000
Description Secure Configuration Lock
Register Name Address Width Type Reset Value Description