User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 1596
UG585 (v1.11) September 27, 2016
Appendix B: Register Details
Register APER_CLK_CTRL Details
Please note that these clocks must be enabled if you want to read from the peripheral register space.
Access Type rw
Reset Value 0x01FFCCCD
Description AMBA Peripheral Clock Control
Field Name Bits Type Reset Value Description
reserved 31:25 rw 0x0 Reserved. Writes are ignored, read data is zero.
SMC_CPU_1XCLKAC
T
24 rw 0x1 SMC AMBA Clock control
0: disable, 1: enable
LQSPI_CPU_1XCLKA
CT
23 rw 0x1 Quad SPI AMBA Clock control
0: disable, 1: enable
GPIO_CPU_1XCLKAC
T
22 rw 0x1 GPIO AMBA Clock control
0: disable, 1: enable
UART1_CPU_1XCLKA
CT
21 rw 0x1 UART 1 AMBA Clock control
0: disable, 1: enable
UART0_CPU_1XCLKA
CT
20 rw 0x1 UART 0 AMBA Clock control
0: disable, 1: enable
I2C1_CPU_1XCLKAC
T
19 rw 0x1 I2C 1 AMBA Clock control
0: disable, 1: enable
I2C0_CPU_1XCLKAC
T
18 rw 0x1 I2C 0 AMBA Clock control
0: disable, 1: enable
CAN1_CPU_1XCLKA
CT
17 rw 0x1 CAN 1 AMBA Clock control
0: disable, 1: enable
CAN0_CPU_1XCLKA
CT
16 rw 0x1 CAN 0 AMBA Clock control
0: disable, 1: enable
SPI1_CPU_1XCLKACT 15 rw 0x1 SPI 1 AMBA Clock control
0: disable, 1: enable
SPI0_CPU_1XCLKACT 14 rw 0x1 SPI 0 AMBA Clock control
0: disable, 1: enable
reserved 13 rw 0x0 Reserved. Writes are ignored, read data is zero.
reserved 12 rw 0x0 Reserved. Writes are ignored, read data is zero.
SDI1_CPU_1XCLKAC
T
11 rw 0x1 SDIO controller 1 AMBA Clock control
0: disable, 1: enable
SDI0_CPU_1XCLKAC
T
10 rw 0x1 SDIO controller 0 AMBA Clock
0: disable,
1: enable
reserved 9 rw 0x0 Reserved. Writes are ignored, read data is zero.