User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 160
UG585 (v1.11) September 27, 2016
Chapter 6: Boot and Configuration
6.1.10 Starting Code on CPU 1
CPU 0 is in charge of starting code execution on CPU 1. The BootROM puts CPU 1 into the Wait for
Event mode. Nothing has been enabled and only a few general purpose registers have been
modified to place it in a state where it is waiting at the WFE instruction.
There is a small amount of protocol required for CPU 0 to start an application on CPU1. When CPU 1
receives a system event, it immediately reads the contents of address
0xFFFFFFF0 and jumps to that
address. If the SEV is issued prior to updating the destination address location (
0xFFFFFFF0), CPU 1
continues in the WFE state because
0xFFFFFFF0 has the address of the WFE instruction as a safety
net. If the software that is written to address
0xFFFFFFF0 is invalid or points to uninitialized memory,
results are unpredictable.
Only ARM-32 ISA code is supported for the initial jump on CPU 1. Thumb and Thumb-II code is not
supported at the destination of the jump. This means that the destination address must be 32-bit
aligned and must be a valid ARM-32 instruction. If these conditions are not met, results are
unpredictable.
The steps for CPU 0 to start an application on CPU 1 are as follows:
1. Write the address of the application for CPU 1 to
0xFFFFFFF0.
2. Execute the SEV instruction to cause CPU 1 to wake up and jump to the application.
The address range
0xFFFFFE00 to 0xFFFFFFF0 is reserved and not available for use until the stage 1
or above application is fully functional. Any access to these regions prior to the successful start-up
of the second CPU causes unpredictable results.
6.1.11 Development Environment
For development and debug, the JTAG interface provides access to the DAP and TAP controllers for
system control. These controllers provide a wide range of capabilities for the developer. The
developer also has the optional ability to access the ARM Test Port User Interface (TPUI) to have a
high bandwidth debug datapath from the APU to the debug tools. These test and debug features are
described in Chapter 27, JTAG and DAP Subsystem.
In JTAG boot mode, a flash device is not required, but can be part of the system. When booting from
a flash device in non-secure mode, the JTAG interface and DAP/TAP controllers can be enabled for
debug and test.
In JTAG boot mode, the BootROM disables access to the hard-coded ROM memory, as usual, and
then executes the WFE instruction in the CPU. JTAG boot mode has control flexibility for a
development environment with access to the PS AXI interconnect via the DAP controller shown in
Figure 5-1, page 120.
The JTAG I/O connections are explained in Chapter 27, JTAG and DAP Subsystem. The debug
environment is described in Chapter 28, System Test and Debug.